JP5089383B2 - 埋め込みｐ＋シリコン・ゲルマニウム層の陽極酸化による歪みシリコン・オン・インシュレータ - Google Patents

埋め込みｐ＋シリコン・ゲルマニウム層の陽極酸化による歪みシリコン・オン・インシュレータ Download PDF

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JP5089383B2
JP5089383B2 JP2007518571A JP2007518571A JP5089383B2 JP 5089383 B2 JP5089383 B2 JP 5089383B2 JP 2007518571 A JP2007518571 A JP 2007518571A JP 2007518571 A JP2007518571 A JP 2007518571A JP 5089383 B2 JP5089383 B2 JP 5089383B2
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semiconductor layer
layer
relaxed
doped
strained
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Japanese (ja)
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JP2008504704A (ja
JP2008504704A5 (enExample
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アダム、トーマス、エヌ
ベデル、ステファン、ダヴリュ
デソウザ、ジョエル、ピー
フォゲル、キース、イー
レツニセク、アレキサンダー
サダナ、デヴェンドラ、ケイ
シャヒディ、ガヴァム
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International Business Machines Corp
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International Business Machines Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
    • H01L21/76259—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along a porous layer
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/967—Semiconductor on specified insulator

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Recrystallisation Techniques (AREA)
  • Element Separation (AREA)
  • Thin Film Transistor (AREA)
JP2007518571A 2004-07-02 2005-05-27 埋め込みｐ＋シリコン・ゲルマニウム層の陽極酸化による歪みシリコン・オン・インシュレータ Expired - Fee Related JP5089383B2 (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US10/883,887 2004-07-02
US10/883,887 US7172930B2 (en) 2004-07-02 2004-07-02 Strained silicon-on-insulator by anodization of a buried p+ silicon germanium layer
PCT/EP2005/052424 WO2006003061A1 (en) 2004-07-02 2005-05-27 STRAINED SILICON-ON-INSULATOR BY ANODIZATION OF A BURIED p+ SILICON GERMANIUM LAYER

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JP2008504704A JP2008504704A (ja) 2008-02-14
JP2008504704A5 JP2008504704A5 (enExample) 2008-05-29
JP5089383B2 true JP5089383B2 (ja) 2012-12-05

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JP2007518571A Expired - Fee Related JP5089383B2 (ja) 2004-07-02 2005-05-27 埋め込みｐ＋シリコン・ゲルマニウム層の陽極酸化による歪みシリコン・オン・インシュレータ

Country Status (7)

Country Link
US (3) US7172930B2 (enExample)
EP (1) EP1779423A1 (enExample)
JP (1) JP5089383B2 (enExample)
KR (1) KR100961815B1 (enExample)
CN (1) CN101120442A (enExample)
TW (1) TWI359477B (enExample)
WO (1) WO2006003061A1 (enExample)

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US8975125B2 (en) 2013-03-14 2015-03-10 International Business Machines Corporation Formation of bulk SiGe fin with dielectric isolation by anodization
US9590077B2 (en) 2015-05-14 2017-03-07 International Business Machines Corporation Local SOI fins with multiple heights
US9385023B1 (en) 2015-05-14 2016-07-05 Globalfoundries Inc. Method and structure to make fins with different fin heights and no topography
US9627536B2 (en) 2015-06-25 2017-04-18 International Busines Machines Corporation Field effect transistors with strained channel features
US9559120B2 (en) 2015-07-02 2017-01-31 International Business Machines Corporation Porous silicon relaxation medium for dislocation free CMOS devices

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Publication number Publication date
US20070111463A1 (en) 2007-05-17
EP1779423A1 (en) 2007-05-02
CN101120442A (zh) 2008-02-06
TWI359477B (en) 2012-03-01
JP2008504704A (ja) 2008-02-14
TW200616141A (en) 2006-05-16
US7592671B2 (en) 2009-09-22
US20080277690A1 (en) 2008-11-13
US7172930B2 (en) 2007-02-06
WO2006003061A1 (en) 2006-01-12
KR100961815B1 (ko) 2010-06-08
US20060003555A1 (en) 2006-01-05
KR20070037483A (ko) 2007-04-04

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