KR100961815B1 - 매립 p+ 실리콘 게르마늄층의 양극화에 의한 스트레인드실리콘 온 절연체 - Google Patents

매립 p+ 실리콘 게르마늄층의 양극화에 의한 스트레인드실리콘 온 절연체 Download PDF

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KR100961815B1
KR100961815B1 KR1020077000058A KR20077000058A KR100961815B1 KR 100961815 B1 KR100961815 B1 KR 100961815B1 KR 1020077000058 A KR1020077000058 A KR 1020077000058A KR 20077000058 A KR20077000058 A KR 20077000058A KR 100961815 B1 KR100961815 B1 KR 100961815B1
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semiconductor layer
layer
relaxed
substrate
strained
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KR20070037483A (ko
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토마스 엔 아담
스티븐 더블유. 베델
조엘 피. 드 소우자
케이스 이. 포겔
알렉산더 레츠니첵
데벤드라 케이. 사다나
가밤 샤히디
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인터내셔널 비지네스 머신즈 코포레이션
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76Making of isolation regions between components
    • H01L21/762Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76251Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
    • H01L21/76259Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along a porous layer
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10STECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00Semiconductor device manufacturing: process
    • Y10S438/967Semiconductor on specified insulator

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Recrystallisation Techniques (AREA)
  • Element Separation (AREA)
  • Thin Film Transistor (AREA)
KR1020077000058A 2004-07-02 2005-05-27 매립 p+ 실리콘 게르마늄층의 양극화에 의한 스트레인드실리콘 온 절연체 Expired - Fee Related KR100961815B1 (ko)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US10/883,887 2004-07-02
US10/883,887 US7172930B2 (en) 2004-07-02 2004-07-02 Strained silicon-on-insulator by anodization of a buried p+ silicon germanium layer

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KR20070037483A KR20070037483A (ko) 2007-04-04
KR100961815B1 true KR100961815B1 (ko) 2010-06-08

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US (3) US7172930B2 (enExample)
EP (1) EP1779423A1 (enExample)
JP (1) JP5089383B2 (enExample)
KR (1) KR100961815B1 (enExample)
CN (1) CN101120442A (enExample)
TW (1) TWI359477B (enExample)
WO (1) WO2006003061A1 (enExample)

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US7833884B2 (en) * 2007-11-02 2010-11-16 International Business Machines Corporation Strained semiconductor-on-insulator by Si:C combined with porous process
US7772096B2 (en) * 2008-07-10 2010-08-10 International Machines Corporation Formation of SOI by oxidation of silicon with engineered porosity gradient
JP5444899B2 (ja) * 2008-09-10 2014-03-19 ソニー株式会社 固体撮像装置の製造方法、および固体撮像装置の製造基板
US20100221867A1 (en) * 2009-05-06 2010-09-02 International Business Machines Corporation Low cost soi substrates for monolithic solar cells
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US8518807B1 (en) * 2012-06-22 2013-08-27 International Business Machines Corporation Radiation hardened SOI structure and method of making same
US8975125B2 (en) 2013-03-14 2015-03-10 International Business Machines Corporation Formation of bulk SiGe fin with dielectric isolation by anodization
US9590077B2 (en) 2015-05-14 2017-03-07 International Business Machines Corporation Local SOI fins with multiple heights
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US20030119280A1 (en) 2001-12-03 2003-06-26 Jung-Il Lee Method for forming SOI substrate

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US20030119280A1 (en) 2001-12-03 2003-06-26 Jung-Il Lee Method for forming SOI substrate

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US20070111463A1 (en) 2007-05-17
EP1779423A1 (en) 2007-05-02
CN101120442A (zh) 2008-02-06
TWI359477B (en) 2012-03-01
JP2008504704A (ja) 2008-02-14
TW200616141A (en) 2006-05-16
US7592671B2 (en) 2009-09-22
US20080277690A1 (en) 2008-11-13
US7172930B2 (en) 2007-02-06
WO2006003061A1 (en) 2006-01-12
JP5089383B2 (ja) 2012-12-05
US20060003555A1 (en) 2006-01-05
KR20070037483A (ko) 2007-04-04

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