KR100961815B1 - 매립 p+ 실리콘 게르마늄층의 양극화에 의한 스트레인드실리콘 온 절연체 - Google Patents
매립 p+ 실리콘 게르마늄층의 양극화에 의한 스트레인드실리콘 온 절연체 Download PDFInfo
- Publication number
- KR100961815B1 KR100961815B1 KR1020077000058A KR20077000058A KR100961815B1 KR 100961815 B1 KR100961815 B1 KR 100961815B1 KR 1020077000058 A KR1020077000058 A KR 1020077000058A KR 20077000058 A KR20077000058 A KR 20077000058A KR 100961815 B1 KR100961815 B1 KR 100961815B1
- Authority
- KR
- South Korea
- Prior art keywords
- semiconductor layer
- layer
- relaxed
- substrate
- strained
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
- H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
- H01L21/76259—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along a porous layer
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S438/00—Semiconductor device manufacturing: process
- Y10S438/967—Semiconductor on specified insulator
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Recrystallisation Techniques (AREA)
- Element Separation (AREA)
- Thin Film Transistor (AREA)
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US10/883,887 | 2004-07-02 | ||
| US10/883,887 US7172930B2 (en) | 2004-07-02 | 2004-07-02 | Strained silicon-on-insulator by anodization of a buried p+ silicon germanium layer |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| KR20070037483A KR20070037483A (ko) | 2007-04-04 |
| KR100961815B1 true KR100961815B1 (ko) | 2010-06-08 |
Family
ID=34969794
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1020077000058A Expired - Fee Related KR100961815B1 (ko) | 2004-07-02 | 2005-05-27 | 매립 p+ 실리콘 게르마늄층의 양극화에 의한 스트레인드실리콘 온 절연체 |
Country Status (7)
| Country | Link |
|---|---|
| US (3) | US7172930B2 (enExample) |
| EP (1) | EP1779423A1 (enExample) |
| JP (1) | JP5089383B2 (enExample) |
| KR (1) | KR100961815B1 (enExample) |
| CN (1) | CN101120442A (enExample) |
| TW (1) | TWI359477B (enExample) |
| WO (1) | WO2006003061A1 (enExample) |
Families Citing this family (15)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7172930B2 (en) * | 2004-07-02 | 2007-02-06 | International Business Machines Corporation | Strained silicon-on-insulator by anodization of a buried p+ silicon germanium layer |
| US7235812B2 (en) * | 2004-09-13 | 2007-06-26 | International Business Machines Corporation | Method of creating defect free high Ge content (>25%) SiGe-on-insulator (SGOI) substrates using wafer bonding techniques |
| RU2331949C1 (ru) * | 2006-12-21 | 2008-08-20 | Институт физики полупроводников Сибирского отделения Российской академии наук | Способ получения структуры "кремний-на-изоляторе" |
| US7833884B2 (en) * | 2007-11-02 | 2010-11-16 | International Business Machines Corporation | Strained semiconductor-on-insulator by Si:C combined with porous process |
| US7772096B2 (en) * | 2008-07-10 | 2010-08-10 | International Machines Corporation | Formation of SOI by oxidation of silicon with engineered porosity gradient |
| JP5444899B2 (ja) * | 2008-09-10 | 2014-03-19 | ソニー株式会社 | 固体撮像装置の製造方法、および固体撮像装置の製造基板 |
| US20100221867A1 (en) * | 2009-05-06 | 2010-09-02 | International Business Machines Corporation | Low cost soi substrates for monolithic solar cells |
| US20120091100A1 (en) * | 2010-10-14 | 2012-04-19 | S.O.I.Tec Silicon On Insulator Technologies | Etchant for controlled etching of ge and ge-rich silicon germanium alloys |
| EP2498280B1 (en) | 2011-03-11 | 2020-04-29 | Soitec | DRAM with trench capacitors and logic back-biased transistors integrated on an SOI substrate comprising an intrinsic semiconductor layer and manufacturing method thereof |
| US8518807B1 (en) * | 2012-06-22 | 2013-08-27 | International Business Machines Corporation | Radiation hardened SOI structure and method of making same |
| US8975125B2 (en) | 2013-03-14 | 2015-03-10 | International Business Machines Corporation | Formation of bulk SiGe fin with dielectric isolation by anodization |
| US9590077B2 (en) | 2015-05-14 | 2017-03-07 | International Business Machines Corporation | Local SOI fins with multiple heights |
| US9385023B1 (en) | 2015-05-14 | 2016-07-05 | Globalfoundries Inc. | Method and structure to make fins with different fin heights and no topography |
| US9627536B2 (en) | 2015-06-25 | 2017-04-18 | International Busines Machines Corporation | Field effect transistors with strained channel features |
| US9559120B2 (en) | 2015-07-02 | 2017-01-31 | International Business Machines Corporation | Porous silicon relaxation medium for dislocation free CMOS devices |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20030003679A1 (en) * | 2001-06-29 | 2003-01-02 | Doyle Brian S. | Creation of high mobility channels in thin-body SOI devices |
| US20030119280A1 (en) | 2001-12-03 | 2003-06-26 | Jung-Il Lee | Method for forming SOI substrate |
Family Cites Families (43)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4104090A (en) * | 1977-02-24 | 1978-08-01 | International Business Machines Corporation | Total dielectric isolation utilizing a combination of reactive ion etching, anodic etching, and thermal oxidation |
| JPS5831730B2 (ja) * | 1979-10-15 | 1983-07-08 | 松下電器産業株式会社 | 半導体装置の製造方法 |
| US6469357B1 (en) * | 1994-03-23 | 2002-10-22 | Agere Systems Guardian Corp. | Article comprising an oxide layer on a GaAs or GaN-based semiconductor body |
| JPH0864674A (ja) * | 1994-08-04 | 1996-03-08 | Lg Semicon Co Ltd | 半導体素子の絶縁方法 |
| US6043166A (en) * | 1996-12-03 | 2000-03-28 | International Business Machines Corporation | Silicon-on-insulator substrates using low dose implantation |
| US6090689A (en) * | 1998-03-04 | 2000-07-18 | International Business Machines Corporation | Method of forming buried oxide layers in silicon |
| US5930643A (en) * | 1997-12-22 | 1999-07-27 | International Business Machines Corporation | Defect induced buried oxide (DIBOX) for throughput SOI |
| US6486037B2 (en) * | 1997-12-22 | 2002-11-26 | International Business Machines Corporation | Control of buried oxide quality in low dose SIMOX |
| US6376859B1 (en) * | 1998-07-29 | 2002-04-23 | Texas Instruments Incorporated | Variable porosity porous silicon isolation |
| US6607948B1 (en) * | 1998-12-24 | 2003-08-19 | Kabushiki Kaisha Toshiba | Method of manufacturing a substrate using an SiGe layer |
| US5950094A (en) | 1999-02-18 | 1999-09-07 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method for fabricating fully dielectric isolated silicon (FDIS) |
| TW591132B (en) * | 1999-06-17 | 2004-06-11 | Taiwan Semiconductor Mfg | Method of growing SiGe epitaxy |
| JP4212228B2 (ja) * | 1999-09-09 | 2009-01-21 | 株式会社東芝 | 半導体装置の製造方法 |
| JP2003158075A (ja) * | 2001-08-23 | 2003-05-30 | Sumitomo Mitsubishi Silicon Corp | 半導体基板の製造方法及び電界効果型トランジスタの製造方法並びに半導体基板及び電界効果型トランジスタ |
| US7101772B2 (en) * | 2000-12-30 | 2006-09-05 | Texas Instruments Incorporated | Means for forming SOI |
| JP2002305293A (ja) * | 2001-04-06 | 2002-10-18 | Canon Inc | 半導体部材の製造方法及び半導体装置の製造方法 |
| US6602757B2 (en) * | 2001-05-21 | 2003-08-05 | International Business Machines Corporation | Self-adjusting thickness uniformity in SOI by high-temperature oxidation of SIMOX and bonded SOI |
| US6541356B2 (en) * | 2001-05-21 | 2003-04-01 | International Business Machines Corporation | Ultimate SIMOX |
| US6846727B2 (en) * | 2001-05-21 | 2005-01-25 | International Business Machines Corporation | Patterned SOI by oxygen implantation and annealing |
| US6855436B2 (en) * | 2003-05-30 | 2005-02-15 | International Business Machines Corporation | Formation of silicon-germanium-on-insulator (SGOI) by an integral high temperature SIMOX-Ge interdiffusion anneal |
| US20020190318A1 (en) * | 2001-06-19 | 2002-12-19 | International Business Machines Corporation | Divot reduction in SIMOX layers |
| US7138649B2 (en) * | 2001-08-09 | 2006-11-21 | Amberwave Systems Corporation | Dual-channel CMOS transistors with differentially strained channels |
| US6495429B1 (en) * | 2002-01-23 | 2002-12-17 | International Business Machines Corporation | Controlling internal thermal oxidation and eliminating deep divots in SIMOX by chlorine-based annealing |
| KR100476901B1 (ko) * | 2002-05-22 | 2005-03-17 | 삼성전자주식회사 | 소이 반도체기판의 형성방법 |
| JP3873012B2 (ja) * | 2002-07-29 | 2007-01-24 | 株式会社東芝 | 半導体装置の製造方法 |
| FR2844634B1 (fr) * | 2002-09-18 | 2005-05-27 | Soitec Silicon On Insulator | Formation d'une couche utile relaxee a partir d'une plaquette sans couche tampon |
| JP4546021B2 (ja) * | 2002-10-02 | 2010-09-15 | ルネサスエレクトロニクス株式会社 | 絶縁ゲート型電界効果型トランジスタ及び半導体装置 |
| US6812116B2 (en) * | 2002-12-13 | 2004-11-02 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method of fabricating a wafer with strained channel layers for increased electron and hole mobility for improving device performance |
| JP4344517B2 (ja) * | 2002-12-27 | 2009-10-14 | 富士通株式会社 | 半導体基板及びその製造方法 |
| WO2004073043A2 (en) | 2003-02-13 | 2004-08-26 | Massachusetts Institute Of Technology | Semiconductor-on-insulator article and method of making same |
| WO2004073044A2 (en) * | 2003-02-13 | 2004-08-26 | Massachusetts Institute Of Technology | Finfet device and method to make same |
| US7329923B2 (en) * | 2003-06-17 | 2008-02-12 | International Business Machines Corporation | High-performance CMOS devices on hybrid crystal oriented substrates |
| US7071052B2 (en) * | 2003-08-18 | 2006-07-04 | Taiwan Semiconductor Manufacturing Company, Ltd. | Resistor with reduced leakage |
| US7125458B2 (en) * | 2003-09-12 | 2006-10-24 | International Business Machines Corporation | Formation of a silicon germanium-on-insulator structure by oxidation of a buried porous silicon layer |
| US7034362B2 (en) * | 2003-10-17 | 2006-04-25 | International Business Machines Corporation | Double silicon-on-insulator (SOI) metal oxide semiconductor field effect transistor (MOSFET) structures |
| US7023055B2 (en) * | 2003-10-29 | 2006-04-04 | International Business Machines Corporation | CMOS on hybrid substrate with different crystal orientations using silicon-to-silicon direct wafer bonding |
| US7183593B2 (en) * | 2003-12-05 | 2007-02-27 | Taiwan Semiconductor Manufacturing Company, Ltd. | Heterostructure resistor and method of forming the same |
| US7202133B2 (en) * | 2004-01-21 | 2007-04-10 | Chartered Semiconductor Manufacturing, Ltd. | Structure and method to form source and drain regions over doped depletion regions |
| US7923782B2 (en) * | 2004-02-27 | 2011-04-12 | International Business Machines Corporation | Hybrid SOI/bulk semiconductor transistors |
| JP4177775B2 (ja) * | 2004-03-16 | 2008-11-05 | 株式会社東芝 | 半導体基板及びその製造方法並びに半導体装置 |
| US7087965B2 (en) * | 2004-04-22 | 2006-08-08 | International Business Machines Corporation | Strained silicon CMOS on hybrid crystal orientations |
| US7172930B2 (en) * | 2004-07-02 | 2007-02-06 | International Business Machines Corporation | Strained silicon-on-insulator by anodization of a buried p+ silicon germanium layer |
| US7585792B2 (en) * | 2005-02-09 | 2009-09-08 | S.O.I.Tec Silicon On Insulator Technologies | Relaxation of a strained layer using a molten layer |
-
2004
- 2004-07-02 US US10/883,887 patent/US7172930B2/en not_active Expired - Fee Related
-
2005
- 2005-05-27 WO PCT/EP2005/052424 patent/WO2006003061A1/en not_active Ceased
- 2005-05-27 EP EP05752768A patent/EP1779423A1/en not_active Withdrawn
- 2005-05-27 JP JP2007518571A patent/JP5089383B2/ja not_active Expired - Fee Related
- 2005-05-27 CN CNA2005800225131A patent/CN101120442A/zh active Pending
- 2005-05-27 KR KR1020077000058A patent/KR100961815B1/ko not_active Expired - Fee Related
- 2005-06-30 TW TW094122166A patent/TWI359477B/zh not_active IP Right Cessation
-
2007
- 2007-01-06 US US11/620,663 patent/US7592671B2/en not_active Expired - Fee Related
-
2008
- 2008-07-21 US US12/176,624 patent/US20080277690A1/en not_active Abandoned
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20030003679A1 (en) * | 2001-06-29 | 2003-01-02 | Doyle Brian S. | Creation of high mobility channels in thin-body SOI devices |
| US20030119280A1 (en) | 2001-12-03 | 2003-06-26 | Jung-Il Lee | Method for forming SOI substrate |
Also Published As
| Publication number | Publication date |
|---|---|
| US20070111463A1 (en) | 2007-05-17 |
| EP1779423A1 (en) | 2007-05-02 |
| CN101120442A (zh) | 2008-02-06 |
| TWI359477B (en) | 2012-03-01 |
| JP2008504704A (ja) | 2008-02-14 |
| TW200616141A (en) | 2006-05-16 |
| US7592671B2 (en) | 2009-09-22 |
| US20080277690A1 (en) | 2008-11-13 |
| US7172930B2 (en) | 2007-02-06 |
| WO2006003061A1 (en) | 2006-01-12 |
| JP5089383B2 (ja) | 2012-12-05 |
| US20060003555A1 (en) | 2006-01-05 |
| KR20070037483A (ko) | 2007-04-04 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US7592671B2 (en) | Strained silicon-on-insulator by anodization of a buried p+ silicon germanium layer | |
| CN100416792C (zh) | 一种制造硅绝缘体衬底结构的方法 | |
| US20050221591A1 (en) | Method of forming high-quality relaxed SiGe alloy layers on bulk Si substrates | |
| US7842940B2 (en) | Structure and method to form semiconductor-on-pores (SOP) for high device performance and low manufacturing cost | |
| US7833884B2 (en) | Strained semiconductor-on-insulator by Si:C combined with porous process | |
| JP4856544B2 (ja) | 埋込多孔質シリコン層の酸化によるシリコン・ゲルマニウムオンインシュレータ構造の形成 | |
| US7187059B2 (en) | Compressive SiGe <110> growth and structure of MOSFET devices | |
| JP2008504704A5 (enExample) | ||
| US7718231B2 (en) | Thin buried oxides by low-dose oxygen implantation into modified silicon | |
| JP2010040931A (ja) | 半導体基板の製造方法及び半導体基板 | |
| KR100405015B1 (ko) | 반도체 장치의 제조 방법 | |
| JP4272607B2 (ja) | 多孔質シリコンの酸化によるsoi |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PA0105 | International application |
St.27 status event code: A-0-1-A10-A15-nap-PA0105 |
|
| PG1501 | Laying open of application |
St.27 status event code: A-1-1-Q10-Q12-nap-PG1501 |
|
| A201 | Request for examination | ||
| P11-X000 | Amendment of application requested |
St.27 status event code: A-2-2-P10-P11-nap-X000 |
|
| P13-X000 | Application amended |
St.27 status event code: A-2-2-P10-P13-nap-X000 |
|
| PA0201 | Request for examination |
St.27 status event code: A-1-2-D10-D11-exm-PA0201 |
|
| R18-X000 | Changes to party contact information recorded |
St.27 status event code: A-3-3-R10-R18-oth-X000 |
|
| R18-X000 | Changes to party contact information recorded |
St.27 status event code: A-3-3-R10-R18-oth-X000 |
|
| E902 | Notification of reason for refusal | ||
| PE0902 | Notice of grounds for rejection |
St.27 status event code: A-1-2-D10-D21-exm-PE0902 |
|
| P11-X000 | Amendment of application requested |
St.27 status event code: A-2-2-P10-P11-nap-X000 |
|
| P13-X000 | Application amended |
St.27 status event code: A-2-2-P10-P13-nap-X000 |
|
| E701 | Decision to grant or registration of patent right | ||
| PE0701 | Decision of registration |
St.27 status event code: A-1-2-D10-D22-exm-PE0701 |
|
| GRNT | Written decision to grant | ||
| PR0701 | Registration of establishment |
St.27 status event code: A-2-4-F10-F11-exm-PR0701 |
|
| PR1002 | Payment of registration fee |
St.27 status event code: A-2-2-U10-U12-oth-PR1002 Fee payment year number: 1 |
|
| PG1601 | Publication of registration |
St.27 status event code: A-4-4-Q10-Q13-nap-PG1601 |
|
| LAPS | Lapse due to unpaid annual fee | ||
| PC1903 | Unpaid annual fee |
St.27 status event code: A-4-4-U10-U13-oth-PC1903 Not in force date: 20130529 Payment event data comment text: Termination Category : DEFAULT_OF_REGISTRATION_FEE |
|
| PC1903 | Unpaid annual fee |
St.27 status event code: N-4-6-H10-H13-oth-PC1903 Ip right cessation event data comment text: Termination Category : DEFAULT_OF_REGISTRATION_FEE Not in force date: 20130529 |
|
| P22-X000 | Classification modified |
St.27 status event code: A-4-4-P10-P22-nap-X000 |