JP2008504679A - ナノクラスタ電荷蓄積デバイスを形成する方法 - Google Patents

ナノクラスタ電荷蓄積デバイスを形成する方法 Download PDF

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Publication number
JP2008504679A
JP2008504679A JP2007518062A JP2007518062A JP2008504679A JP 2008504679 A JP2008504679 A JP 2008504679A JP 2007518062 A JP2007518062 A JP 2007518062A JP 2007518062 A JP2007518062 A JP 2007518062A JP 2008504679 A JP2008504679 A JP 2008504679A
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Japan
Prior art keywords
layer
forming
gate
gate material
material layer
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Pending
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JP2007518062A
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English (en)
Japanese (ja)
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JP2008504679A5 (enExample
Inventor
エイ． ラオ、ラジェシュ
ムラリダー、ラマチャンドラン
エフ． スタイムル、ロバート
エル． チンダロア、ゴーリシャンカー
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NXP USA Inc
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NXP USA Inc
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Publication of JP2008504679A publication Critical patent/JP2008504679A/ja
Publication of JP2008504679A5 publication Critical patent/JP2008504679A5/ja
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/40—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
    • H10B41/42—Simultaneous manufacture of periphery and memory cells
    • H10B41/49—Simultaneous manufacture of periphery and memory cells comprising different types of peripheral transistor
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B82—NANOTECHNOLOGY
    • B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
    • B82Y10/00—Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/40—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/30—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/40—EEPROM devices comprising charge-trapping gate insulators characterised by the peripheral circuit region
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/68—Floating-gate IGFETs
    • H10D30/6891—Floating-gate IGFETs characterised by the shapes, relative sizes or dispositions of the floating gate electrode
    • H10D30/6893—Floating-gate IGFETs characterised by the shapes, relative sizes or dispositions of the floating gate electrode wherein the floating gate has multiple non-connected parts, e.g. multi-particle floating gate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/01—Manufacture or treatment
    • H10D64/031—Manufacture or treatment of data-storage electrodes
    • H10D64/035—Manufacture or treatment of data-storage electrodes comprising conductor-insulator-conductor-insulator-semiconductor structures
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/01—Manufacture or treatment
    • H10D64/031—Manufacture or treatment of data-storage electrodes
    • H10D64/037—Manufacture or treatment of data-storage electrodes comprising charge-trapping insulators

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  • Engineering & Computer Science (AREA)
  • Chemical & Material Sciences (AREA)
  • Nanotechnology (AREA)
  • Physics & Mathematics (AREA)
  • Mathematical Physics (AREA)
  • Theoretical Computer Science (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Manufacturing & Machinery (AREA)
  • Non-Volatile Memory (AREA)
  • Semiconductor Memories (AREA)
  • Formation Of Insulating Films (AREA)
JP2007518062A 2004-06-25 2005-05-11 ナノクラスタ電荷蓄積デバイスを形成する方法 Pending JP2008504679A (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US10/876,820 US7091130B1 (en) 2004-06-25 2004-06-25 Method of forming a nanocluster charge storage device
PCT/US2005/016252 WO2006007069A2 (en) 2004-06-25 2005-05-11 Method of forming a nanocluster charge storage device

Publications (2)

Publication Number Publication Date
JP2008504679A true JP2008504679A (ja) 2008-02-14
JP2008504679A5 JP2008504679A5 (enExample) 2008-05-08

Family

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Family Applications (1)

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JP2007518062A Pending JP2008504679A (ja) 2004-06-25 2005-05-11 ナノクラスタ電荷蓄積デバイスを形成する方法

Country Status (6)

Country Link
US (1) US7091130B1 (enExample)
EP (1) EP1759405A4 (enExample)
JP (1) JP2008504679A (enExample)
CN (1) CN100435286C (enExample)
TW (1) TWI375318B (enExample)
WO (1) WO2006007069A2 (enExample)

Cited By (4)

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JP2010517306A (ja) * 2007-01-26 2010-05-20 フリースケール セミコンダクター インコーポレイテッド 高電圧トランジスタ、不揮発性メモリトランジスタ、およびロジックトランジスタを備えた半導体デバイスを製造する方法
JP2013157604A (ja) * 2012-01-31 2013-08-15 Freescale Semiconductor Inc 密度の異なるナノ結晶を有する異なる複数の不揮発性メモリを有する半導体デバイスおよびそのための方法
JP2014140069A (ja) * 2014-04-14 2014-07-31 Renesas Electronics Corp 半導体装置の製造方法
JP2017523595A (ja) * 2015-03-09 2017-08-17 サイプレス セミコンダクター コーポレーション Оｎｏスタックの形成方法

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US7589029B2 (en) 2002-05-02 2009-09-15 Micron Technology, Inc. Atomic layer deposition and conversion
US7588988B2 (en) 2004-08-31 2009-09-15 Micron Technology, Inc. Method of forming apparatus having oxide films formed using atomic layer deposition
US7361543B2 (en) * 2004-11-12 2008-04-22 Freescale Semiconductor, Inc. Method of forming a nanocluster charge storage device
KR100688504B1 (ko) * 2004-11-15 2007-03-02 삼성전자주식회사 이온주입을 이용한 비휘발성 메모리 소자 제조 방법 및이에 따른 소자
US20060131633A1 (en) * 2004-12-21 2006-06-22 Micron Technology, Inc. Integrated two device non-volatile memory
US7183159B2 (en) * 2005-01-14 2007-02-27 Freescale Semiconductor, Inc. Method of forming an integrated circuit having nanocluster devices and non-nanocluster devices
US7662729B2 (en) 2005-04-28 2010-02-16 Micron Technology, Inc. Atomic layer deposition of a ruthenium layer to a lanthanide oxide dielectric layer
US7572695B2 (en) 2005-05-27 2009-08-11 Micron Technology, Inc. Hafnium titanium oxide films
US7927948B2 (en) 2005-07-20 2011-04-19 Micron Technology, Inc. Devices with nanocrystals and methods of formation
US7575978B2 (en) * 2005-08-04 2009-08-18 Micron Technology, Inc. Method for making conductive nanoparticle charge storage element
US7410910B2 (en) 2005-08-31 2008-08-12 Micron Technology, Inc. Lanthanum aluminum oxynitride dielectric films
KR100698086B1 (ko) * 2005-12-29 2007-03-23 동부일렉트로닉스 주식회사 반도체소자의 제조방법
US7560769B2 (en) 2006-08-03 2009-07-14 Micron Technology, Inc. Non-volatile memory cell device and methods
US7955935B2 (en) 2006-08-03 2011-06-07 Micron Technology, Inc. Non-volatile memory cell devices and methods
US8093680B1 (en) * 2006-09-14 2012-01-10 Spansion Llc Metal-insulator-metal-insulator-metal (MIMIM) memory device
US7687349B2 (en) 2006-10-30 2010-03-30 Atmel Corporation Growth of silicon nanodots having a metallic coating using gaseous precursors
FR2910176B1 (fr) 2006-12-15 2009-10-23 Commissariat Energie Atomique Procede de realisation d'un dispositif a base de nanocristaux recouverts d'une couche de nitrure deposee par cvd
US7763511B2 (en) * 2006-12-29 2010-07-27 Intel Corporation Dielectric barrier for nanocrystals
US20080269746A1 (en) * 2007-04-24 2008-10-30 Osteolign, Inc. Conformable intramedullary implant with nestable components
US9299568B2 (en) 2007-05-25 2016-03-29 Cypress Semiconductor Corporation SONOS ONO stack scaling
US8614124B2 (en) 2007-05-25 2013-12-24 Cypress Semiconductor Corporation SONOS ONO stack scaling
US8367506B2 (en) 2007-06-04 2013-02-05 Micron Technology, Inc. High-k dielectrics with gold nano-particles
US7846793B2 (en) * 2007-10-03 2010-12-07 Applied Materials, Inc. Plasma surface treatment for SI and metal nanocrystal nucleation
US9431549B2 (en) 2007-12-12 2016-08-30 Cypress Semiconductor Corporation Nonvolatile charge trap memory device having a high dielectric constant blocking region
US7871886B2 (en) * 2008-12-19 2011-01-18 Freescale Semiconductor, Inc. Nanocrystal memory with differential energy bands and method of formation
US7799634B2 (en) * 2008-12-19 2010-09-21 Freescale Semiconductor, Inc. Method of forming nanocrystals
US8071453B1 (en) 2009-04-24 2011-12-06 Cypress Semiconductor Corporation Method of ONO integration into MOS flow
US9102522B2 (en) 2009-04-24 2015-08-11 Cypress Semiconductor Corporation Method of ONO integration into logic CMOS flow
US8202778B2 (en) * 2010-08-31 2012-06-19 Freescale Semiconductor, Inc. Patterning a gate stack of a non-volatile memory (NVM) with simultaneous etch in non-NVM area
US9230977B2 (en) 2013-06-21 2016-01-05 Taiwan Semiconductor Manufacturing Company, Ltd. Embedded flash memory device with floating gate embedded in a substrate
US8883624B1 (en) 2013-09-27 2014-11-11 Cypress Semiconductor Corporation Integration of a memory transistor into high-K, metal gate CMOS process flow
CN107978606B (zh) * 2017-11-20 2020-08-25 上海华力微电子有限公司 一种嵌入式闪存工艺集成方法
TWI704648B (zh) * 2019-11-20 2020-09-11 華邦電子股份有限公司 記憶體裝置的製造方法

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JP2000077618A (ja) * 1998-06-15 2000-03-14 Mitsubishi Electric Corp 半導体装置およびその製造方法
JP2003086766A (ja) * 2001-06-28 2003-03-20 Toshiba Corp 半導体装置及びその製造方法
JP2003218245A (ja) * 2002-01-25 2003-07-31 Sony Corp 不揮発性半導体メモリ装置の製造方法
JP2003218212A (ja) * 2002-01-25 2003-07-31 Hitachi Ltd 半導体装置
JP2004104009A (ja) * 2002-09-12 2004-04-02 Fujitsu Ltd 半導体装置及びその製造方法
JP2004349680A (ja) * 2003-04-28 2004-12-09 Renesas Technology Corp 半導体装置およびその製造方法

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US6297095B1 (en) 2000-06-16 2001-10-02 Motorola, Inc. Memory device that includes passivated nanoclusters and method for manufacture
JP2002009168A (ja) * 2000-06-19 2002-01-11 Nec Corp 半導体装置及びその製造方法
JP4096507B2 (ja) * 2000-09-29 2008-06-04 富士通株式会社 半導体装置の製造方法
US6444545B1 (en) 2000-12-19 2002-09-03 Motorola, Inc. Device structure for storing charge and method therefore
JP2003309182A (ja) 2002-04-17 2003-10-31 Hitachi Ltd 半導体装置の製造方法及び半導体装置
US7115949B2 (en) * 2002-05-30 2006-10-03 Freescale Semiconductor, Inc. Method of forming a semiconductor device in a semiconductor layer and structure thereof
US7189606B2 (en) * 2002-06-05 2007-03-13 Micron Technology, Inc. Method of forming fully-depleted (FD) SOI MOSFET access transistor
US6958265B2 (en) * 2003-09-16 2005-10-25 Freescale Semiconductor, Inc. Semiconductor device with nanoclusters
US7098502B2 (en) 2003-11-10 2006-08-29 Freescale Semiconductor, Inc. Transistor having three electrically isolated electrodes and method of formation

Patent Citations (6)

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Publication number Priority date Publication date Assignee Title
JP2000077618A (ja) * 1998-06-15 2000-03-14 Mitsubishi Electric Corp 半導体装置およびその製造方法
JP2003086766A (ja) * 2001-06-28 2003-03-20 Toshiba Corp 半導体装置及びその製造方法
JP2003218245A (ja) * 2002-01-25 2003-07-31 Sony Corp 不揮発性半導体メモリ装置の製造方法
JP2003218212A (ja) * 2002-01-25 2003-07-31 Hitachi Ltd 半導体装置
JP2004104009A (ja) * 2002-09-12 2004-04-02 Fujitsu Ltd 半導体装置及びその製造方法
JP2004349680A (ja) * 2003-04-28 2004-12-09 Renesas Technology Corp 半導体装置およびその製造方法

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2010517306A (ja) * 2007-01-26 2010-05-20 フリースケール セミコンダクター インコーポレイテッド 高電圧トランジスタ、不揮発性メモリトランジスタ、およびロジックトランジスタを備えた半導体デバイスを製造する方法
JP2013157604A (ja) * 2012-01-31 2013-08-15 Freescale Semiconductor Inc 密度の異なるナノ結晶を有する異なる複数の不揮発性メモリを有する半導体デバイスおよびそのための方法
JP2014140069A (ja) * 2014-04-14 2014-07-31 Renesas Electronics Corp 半導体装置の製造方法
JP2017523595A (ja) * 2015-03-09 2017-08-17 サイプレス セミコンダクター コーポレーション Оｎｏスタックの形成方法
JP2018041977A (ja) * 2015-03-09 2018-03-15 サイプレス セミコンダクター コーポレーション Оｎｏスタックの形成方法

Also Published As

Publication number Publication date
WO2006007069A3 (en) 2007-04-12
WO2006007069A2 (en) 2006-01-19
US7091130B1 (en) 2006-08-15
TW200612548A (en) 2006-04-16
CN101010785A (zh) 2007-08-01
US20060194438A1 (en) 2006-08-31
EP1759405A4 (en) 2008-11-12
TWI375318B (en) 2012-10-21
CN100435286C (zh) 2008-11-19
EP1759405A2 (en) 2007-03-07

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