JP2008311593A - 電子装置 - Google Patents
電子装置 Download PDFInfo
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Abstract
【解決手段】半導体チップ101に形成された電極パッド103上にバンプ104を形成する工程と、半導体チップ101上に低弾性絶縁層120を形成すると共にこれより高い弾性率を有する高弾性絶縁層121を低弾性絶縁層120上に積層し積層絶縁層105を形成する工程と、バンプ104の一部を積層絶縁層105の上面に露出させる工程と、このバンプ104に接続した導電パターン106を形成する工程とを有する。
【選択図】図3E
Description
基板本体に形成された電極パッド上にバンプを形成する第1の工程と、
前記基板本体上に第1の絶縁層を形成すると共に、該第1の絶縁層の弾性率よりも高い弾性率を有する第2の絶縁層を該第1の絶縁層上に積層形成する第2の工程と、
前記バンプの一部を前記絶縁層の上面に露出させる第3の工程と、
前記バンプに接続した導電パターンを形成する第4の工程とを有することを特徴とする電子装置の製造方法により解決することができる。
電極パッドが形成された基板本体と、
前記電極パッド上に形成されたバンプと、
前記基板本体上に形成された第1の絶縁層と、該第1の絶縁層の弾性率よりも高い弾性率を有すると共に該第1の絶縁層上に積層形成された第2の絶縁層とよりなる積層絶縁層と、
該積層絶縁層上に形成されると共に前記バンプに接続された導電パターンとを有してなることを特徴とする電子装置により解決することができる。
101 半導体チップ
101A 基板
102 保護層
103 電極パッド
104 バンプ
104A バンプ本体
104B 突起部
105 積層絶縁層
106 導電パターン
107 第1の導電パターン
107A 導電層
108 第2の導電パターン
108A 導電層
109 ソルダーレジスト層
110 はんだバンプ
112 銅箔
120 低弾性絶縁層
121 高弾性絶縁層
130 分割絶縁層
電極パッドが形成された基板本体と、
前記電極パッド上に形成されたバンプと、
前記基板本体上に形成されており、第1の絶縁層と、該第1の絶縁層の弾性率よりも高い弾性率を有する第2の絶縁層とを有する積層絶縁層と、
該積層絶縁層上に形成されると共に前記バンプに接続された導電パターンとを有する電子装置であって、
前記積層絶縁層は、前記第2の絶縁層を前記バンプを囲繞するよう形成し、前記第1の絶縁層を前記第2の絶縁層の形成位置を除く他の部分に形成した構成であることを特徴とする電子装置により解決することができる。
また、上記発明において、前記第1の絶縁層の弾性率を20MPa以上1000MPa未満とし、前記第2の絶縁層の弾性率を1000MPa以上とすることが望ましい。
また、上記発明において、前記基板本体が半導体チップであることが望ましい。
電極パッドが形成された基板本体と、
前記電極パッド上に形成されたバンプと、
前記基板本体上に形成されており、第1の絶縁層と、該第1の絶縁層の弾性率よりも高い弾性率を有する第2の絶縁層とを有する分割絶縁層と、
該分割絶縁層上に形成されると共に前記バンプに接続された導電パターンとを有する電子装置であって、
前記分割絶縁層は、前記第2の絶縁層を前記バンプを囲繞する円筒形状に形成し、前記第1の絶縁層を前記第2の絶縁層を除く他の部分に形成した構成であることを特徴とする電子装置により解決することができる。
また、上記発明において、前記第1の絶縁層の弾性率を20MPa以上1000MPa未満とし、前記第2の絶縁層の弾性率を1000MPa以上とすることが望ましい。
また、上記発明において、前記基板本体が半導体チップであることが望ましい。
Claims (9)
- 基板本体に形成された電極パッド上にバンプを形成する第1の工程と、
前記基板本体上に第1の絶縁層を形成すると共に、該第1の絶縁層の弾性率よりも高い弾性率を有する第2の絶縁層を該第1の絶縁層上に積層形成する第2の工程と、
前記バンプの一部を前記絶縁層の上面に露出させる第3の工程と、
前記バンプに接続した導電パターンを形成する第4の工程と、
を有することを特徴とする電子装置の製造方法。 - 前記第1の絶縁層は弾性率が20MPa以上1000MPa未満であり、
前記第2の絶縁層は弾性率が1000MPa以上であることを特徴とする請求項1記載の電子装置の製造方法。 - 前記第1及び第2の絶縁層は、非導電樹脂よりなることを特徴とする請求項1又は2記載の電子装置の製造方法。
- 前記第4の工程は、
前記絶縁層の上面及び前記バンプの露出した部分に導電層を形成する工程と、
前記導電層を給電層とした電解メッキにより配線層を形成する工程と、
該配線層をパターニングして前記バンプに接続した導電パターンを形成する工程とを有することを特徴とする請求項1乃至3のいずれか一項に記載の電子装置の製造方法。 - 前記基板本体は、半導体基板であることを特徴とする請求項1乃至3のいずれか一項に記載の電子装置の製造方法。
- 前記第1の工程では、前記バンプがボンディングワイヤにより形成されることを特徴とする請求項1乃至5のいずれか一項に記載の電子装置の製造方法。
- 電極パッドが形成された基板本体と、
前記電極パッド上に形成されたバンプと、
前記基板本体上に形成された第1の絶縁層と、該第1の絶縁層の弾性率よりも高い弾性率を有すると共に該第1の絶縁層上に積層形成された第2の絶縁層とよりなる積層絶縁層と、
該積層絶縁層上に形成されると共に前記バンプに接続された導電パターンと、
を有してなることを特徴とする電子装置。 - 前記第1の絶縁層は弾性率が20MPa以上1000MPa未満であり、
前記第2の絶縁層は弾性率が1000MPa以上であることを特徴とする請求項7記載の電子装置。 - 前記基板本体が半導体チップであることを特徴とする請求項7又は8記載の電子装置。
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JP2007160614A JP4121543B1 (ja) | 2007-06-18 | 2007-06-18 | 電子装置 |
KR1020080050000A KR20080111391A (ko) | 2007-06-18 | 2008-05-29 | 전자 장치의 제조 방법 및 전자 장치 |
TW097121651A TW200908178A (en) | 2007-06-18 | 2008-06-11 | Electronic device manufacturing method and electronic device |
CNA2008101266168A CN101330027A (zh) | 2007-06-18 | 2008-06-17 | 电子器件的制造方法以及电子器件 |
US12/140,651 US8102048B2 (en) | 2007-06-18 | 2008-06-17 | Electronic device manufacturing method and electronic device |
EP08158511A EP2017883A3 (en) | 2007-06-18 | 2008-06-18 | Electronic device manufacturing method and electronic device |
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US (1) | US8102048B2 (ja) |
EP (1) | EP2017883A3 (ja) |
JP (1) | JP4121543B1 (ja) |
KR (1) | KR20080111391A (ja) |
CN (1) | CN101330027A (ja) |
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JP4121542B1 (ja) * | 2007-06-18 | 2008-07-23 | 新光電気工業株式会社 | 電子装置の製造方法 |
JP2012134270A (ja) * | 2010-12-21 | 2012-07-12 | Shinko Electric Ind Co Ltd | 半導体装置及びその製造方法 |
US8756546B2 (en) | 2012-07-25 | 2014-06-17 | International Business Machines Corporation | Elastic modulus mapping of a chip carrier in a flip chip package |
US8650512B1 (en) | 2012-11-15 | 2014-02-11 | International Business Machines Corporation | Elastic modulus mapping of an integrated circuit chip in a chip/device package |
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CN101330027A (zh) | 2008-12-24 |
TW200908178A (en) | 2009-02-16 |
JP4121543B1 (ja) | 2008-07-23 |
EP2017883A2 (en) | 2009-01-21 |
US8102048B2 (en) | 2012-01-24 |
KR20080111391A (ko) | 2008-12-23 |
US20080315413A1 (en) | 2008-12-25 |
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