JP2008227280A - リードフレーム、ならびに半導体装置およびその製造方法 - Google Patents
リードフレーム、ならびに半導体装置およびその製造方法 Download PDFInfo
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- JP2008227280A JP2008227280A JP2007065277A JP2007065277A JP2008227280A JP 2008227280 A JP2008227280 A JP 2008227280A JP 2007065277 A JP2007065277 A JP 2007065277A JP 2007065277 A JP2007065277 A JP 2007065277A JP 2008227280 A JP2008227280 A JP 2008227280A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 62
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 19
- 229920005989 resin Polymers 0.000 claims abstract description 36
- 239000011347 resin Substances 0.000 claims abstract description 36
- 238000007789 sealing Methods 0.000 claims abstract description 20
- 239000000725 suspension Substances 0.000 claims abstract description 16
- 238000000034 method Methods 0.000 description 9
- 239000012212 insulator Substances 0.000 description 3
- 230000000694 effects Effects 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- 239000000853 adhesive Substances 0.000 description 1
- 230000001070 adhesive effect Effects 0.000 description 1
- 238000005452 bending Methods 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 239000003822 epoxy resin Substances 0.000 description 1
- 230000017525 heat dissipation Effects 0.000 description 1
- 238000003754 machining Methods 0.000 description 1
- 230000007257 malfunction Effects 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 229920000647 polyepoxide Polymers 0.000 description 1
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- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
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- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
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- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
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- H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
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- Engineering & Computer Science (AREA)
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- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Geometry (AREA)
- Manufacturing & Machinery (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
- Lead Frames For Integrated Circuits (AREA)
Abstract
【解決手段】半導体装置1は、半導体チップ10と、半導体チップ10が載置された上面S1および上面S1と反対の面である下面S2を有するアイランド20と、アイランド20に連結され、当該アイランド20を保持する吊ピン30と、吊ピン30から分岐した分岐部40と、を備えている。分岐部40は、アイランド20の下面S2側に向かって傾斜している。
【選択図】図1
Description
10 半導体チップ
12 パッド
20 アイランド
30 吊ピン
40 分岐部
42 分岐部
44 分岐部
50 リード端子
60 リードフレーム
70 ワイヤ
80 金型
82 上金型
84 下金型
90 封止樹脂
Claims (8)
- 半導体チップが載置される第1面、および前記第1面と反対の面である第2面を有するアイランドと、
前記アイランドに連結され、当該アイランドを保持する吊ピンと、
前記吊ピンから分岐した分岐部と、を備え、
前記分岐部は、前記アイランドの前記第2面側に向かって傾斜していることを特徴とするリードフレーム。 - 請求項1に記載のリードフレームにおいて、
前記分岐部は、前記第2面側に向けて曲げ加工されているリードフレーム。 - 請求項1または2に記載のリードフレームにおいて、
前記分岐部は、前記吊ピンの両側に設けられた第1および第2の分岐部を含むリードフレーム。 - 請求項1乃至3いずれかに記載のリードフレームにおいて、
前記アイランドの前記第2面を下にしたとき、
前記アイランドは、前記吊ピンの先端部よりも低い位置に存在するリードフレーム。 - 半導体チップと、
前記半導体チップが載置された第1面、および前記第1面と反対の面である第2面を有するアイランドと、
前記アイランドに連結され、当該アイランドを保持する吊ピンと、
前記吊ピンから分岐した分岐部と、
を備えることを特徴とする半導体装置。 - 請求項5に記載の半導体装置において、
前記半導体チップを覆う封止樹脂を更に備え、
前記アイランドの前記第2面は、前記封止樹脂の表面に露出している半導体装置。 - 請求項1乃至4いずれかに記載のリードフレームを準備する工程と、
前記アイランドの前記第1面上に、前記半導体チップを載置する工程と、
前記半導体チップを載置する工程よりも後に、上金型および下金型を有する金型に前記リードフレームを設置する工程と、
前記リードフレームが前記金型に設置された状態で、当該金型内に封止樹脂を注入する工程と、を含み、
前記リードフレームは、前記上金型および前記下金型によって前記分岐部が挟み込まれるように、前記金型に設置されることを特徴とする半導体装置の製造方法。 - 請求項7に記載の半導体装置の製造方法において、
前記リードフレームは、前記アイランドの前記第2面が前記下金型の底面に接するように、前記金型に設置される半導体装置の製造方法。
Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2007065277A JP5180495B2 (ja) | 2007-03-14 | 2007-03-14 | 半導体装置およびその製造方法 |
US12/048,447 US7944027B2 (en) | 2007-03-14 | 2008-03-14 | Lead frame, semiconductor device, and method of manufacturing the semiconductor device |
US13/081,174 US8236620B2 (en) | 2007-03-14 | 2011-04-06 | Method of manufacturing a semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2007065277A JP5180495B2 (ja) | 2007-03-14 | 2007-03-14 | 半導体装置およびその製造方法 |
Publications (2)
Publication Number | Publication Date |
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JP2008227280A true JP2008227280A (ja) | 2008-09-25 |
JP5180495B2 JP5180495B2 (ja) | 2013-04-10 |
Family
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Application Number | Title | Priority Date | Filing Date |
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JP2007065277A Expired - Fee Related JP5180495B2 (ja) | 2007-03-14 | 2007-03-14 | 半導体装置およびその製造方法 |
Country Status (2)
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US (2) | US7944027B2 (ja) |
JP (1) | JP5180495B2 (ja) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR20190053783A (ko) | 2017-11-10 | 2019-05-20 | 에이블릭 가부시키가이샤 | 수지 봉지 금형 및 반도체 장치의 제조 방법 |
Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH04333245A (ja) * | 1990-12-28 | 1992-11-20 | Sgs Thomson Microelettronica Spa | プラスチック集積回路パッケージを製造するための金型 |
JPH08153845A (ja) * | 1994-11-29 | 1996-06-11 | Nec Corp | 樹脂封止型半導体装置及びリードフレームの製造方法 |
JPH11260985A (ja) * | 1998-03-12 | 1999-09-24 | Matsushita Electron Corp | リードフレーム,樹脂封止型半導体装置及びその製造方法 |
JP2001177035A (ja) * | 1999-12-15 | 2001-06-29 | Matsushita Electronics Industry Corp | 半導体装置及び半導体装置の製造方法 |
JP2005276890A (ja) * | 2004-03-23 | 2005-10-06 | Renesas Technology Corp | 半導体装置及びその製造方法 |
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JP3616469B2 (ja) | 1997-01-24 | 2005-02-02 | ローム株式会社 | 半導体装置およびその製造方法 |
KR100319616B1 (ko) * | 1999-04-17 | 2002-01-05 | 김영환 | 리드프레임 및 이를 이용한 버텀리드 반도체패키지 |
TW508774B (en) * | 2000-09-15 | 2002-11-01 | Samsung Techwin Co Ltd | Lead frame, semiconductor package having the same, method of manufacturing semiconductor package, molding plates and molding machine for manufacturing semiconductor package |
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2007
- 2007-03-14 JP JP2007065277A patent/JP5180495B2/ja not_active Expired - Fee Related
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2008
- 2008-03-14 US US12/048,447 patent/US7944027B2/en active Active
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- 2011-04-06 US US13/081,174 patent/US8236620B2/en not_active Expired - Fee Related
Patent Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH04333245A (ja) * | 1990-12-28 | 1992-11-20 | Sgs Thomson Microelettronica Spa | プラスチック集積回路パッケージを製造するための金型 |
JPH08153845A (ja) * | 1994-11-29 | 1996-06-11 | Nec Corp | 樹脂封止型半導体装置及びリードフレームの製造方法 |
JPH11260985A (ja) * | 1998-03-12 | 1999-09-24 | Matsushita Electron Corp | リードフレーム,樹脂封止型半導体装置及びその製造方法 |
JP2001177035A (ja) * | 1999-12-15 | 2001-06-29 | Matsushita Electronics Industry Corp | 半導体装置及び半導体装置の製造方法 |
JP2005276890A (ja) * | 2004-03-23 | 2005-10-06 | Renesas Technology Corp | 半導体装置及びその製造方法 |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR20190053783A (ko) | 2017-11-10 | 2019-05-20 | 에이블릭 가부시키가이샤 | 수지 봉지 금형 및 반도체 장치의 제조 방법 |
US10804118B2 (en) | 2017-11-10 | 2020-10-13 | Ablic Inc. | Resin encapsulating mold and method of manufacturing semiconductor device |
Also Published As
Publication number | Publication date |
---|---|
US20110183473A1 (en) | 2011-07-28 |
US8236620B2 (en) | 2012-08-07 |
US20080224280A1 (en) | 2008-09-18 |
US7944027B2 (en) | 2011-05-17 |
JP5180495B2 (ja) | 2013-04-10 |
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