JP2008205484A - 格子状レイアウトを有するトランジスタのゲート金属ルーティング - Google Patents
格子状レイアウトを有するトランジスタのゲート金属ルーティング Download PDFInfo
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- 239000002184 metal Substances 0.000 title claims description 36
- 239000004065 semiconductor Substances 0.000 claims abstract description 22
- 239000000758 substrate Substances 0.000 claims description 18
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- 239000000463 material Substances 0.000 claims description 11
- 238000000034 method Methods 0.000 abstract description 7
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- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 27
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- 235000012431 wafers Nutrition 0.000 description 12
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- 229920005591 polysilicon Polymers 0.000 description 10
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- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 230000015556 catabolic process Effects 0.000 description 2
- 239000003989 dielectric material Substances 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 238000005520 cutting process Methods 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
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- 230000005684 electric field Effects 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 239000007943 implant Substances 0.000 description 1
- 229910001092 metal group alloy Inorganic materials 0.000 description 1
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- 239000000377 silicon dioxide Substances 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 239000002210 silicon-based material Substances 0.000 description 1
- 239000002356 single layer Substances 0.000 description 1
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Abstract
【解決手段】1つの実施形態において、半導体ダイ上に作製されたトランジスタは、細長いトランジスタセグメントのセクションに配列される。当該セクションは、当該半導体ダイの実質的に全体にわたって列及び行で配列される。列内又は行で隣接するセクションは、隣接するセクションの第1のスタブライン中のトランジスタセグメントの長さが第1の方向に延び、隣接するセクションの第2のスタブライン中のトランジスタセグメントの長さが第2の方向に延びるような向きにされ、該第1の方向は第2の方向に実質的に直交する。この要約は、サーチャ又は他の閲覧者が本技術的開示事項の対象を迅速に調査できるようになる要約を必要とする規則に適合するように提供される点は強調される。
【選択図】図2A
Description
17 シリコンピラー
18a、18b ゲート部材
19a、19b フィールドプレート
21 半導体ダイ
30a 上側トランジスタセクション
30b 下側トランジスタセクション
32 ダミーシリコンピラー
Claims (24)
- 基板と、
複数のセクションに編成された複数のトランジスタセグメントと、
を備えたトランジスタであって、
前記各トランジスタセグメントが長さ及び幅を有し、前記各セクションのトランジスタセグメントが前記幅に沿って並列関係で配列され、前記セクションが列及び行の形態で配列され、前記セクション間で前記トランジスタセグメントの長さが第1の横方向と該第1の横方向と直交する第2の横方向とで交互に整列されるように前記各列のセクションが配列されており、前記各トランジスタセグメントが、
前記基板の上面又はその近傍に配置されたソース領域を有する半導体材料のピラーと、
前記ピラーの両側にそれぞれ配置された、前記ピラーによって横方向に囲まれた第1の誘電領域及び前記ピラーを横方向に囲む第2の誘電領域と、
前記第1及び第2の誘電領域内にそれぞれ配置された第1及び第2のフィールドプレートと、
ボディ領域に隣接する前記ピラーの上部又はその近傍で前記第1及び第2の誘電領域内にそれぞれ配置された第1及び第2のゲート部材と、
含み、前記トランジスタが更に、
前記各トランジスタセグメントのソース領域に結合されたソースバスと、各トランジスタセグメントの前記第1及び第2のゲート部材に結合されたゲートバスとを含む第1の金属層を備える、
ことを特徴とするトランジスタ。 - 前記ピラーが、前記第1及び第2の横方向に延びてレーストラック形リング又は楕円を形成する、
ことを特徴とする請求項1に記載のトランジスタ。 - 前記ピラーが前記基板を通って垂直に延びており、前記ピラーが更に、
拡張ドレイン領域と、
前記ソース領域と前記拡張ドレイン領域とを垂直方向に分離するボディ領域と、
を更に含む
ことを特徴とする請求項1に記載のトランジスタ。 - 前記ゲートバスが各列に関連する上部ライン及び下部ラインを備え、前記第1の横方向で整列された前記セグメントの長さを備えた前記セクションが、前記上部ラインに結合された前記セグメントの第1の半分の前記第1及び第2のゲート部材を有し、前記セグメントの第2の半分の前記第1及び第2のゲート部材が前記下部ラインに結合されている、
ことを特徴とする請求項1に記載のトランジスタ。 - 前記ゲートバスが更にスタブラインのペアを備え、前記セグメントの長さが前記第2の横方向で整列された各セクションについて、前記セグメントの第1の半分の前記第1及び第2のゲート部材が前記スタブラインのペアのうちの第1のスタブラインに結合され、前記セグメントの第2の半分の前記第1及び第2のゲート部材が前記スタブラインのペアのうちの第2のスタブラインに結合される、
ことを特徴とする請求項4に記載のトランジスタ。 - 前記スタブラインのペアの前記第1のスタブライン及び第2のスタブラインが、各列の凡そ半分にわたって前記第1の横方向に延びる、
ことを特徴とする請求項5に記載のトランジスタ。 - 前記上部及び下部ラインが、前記第2の横方向に実質的に整列し、前記スタブラインのうちの前記第1及び第2のスタブラインが、前記第1の横方向に実質的に整列する、
ことを特徴とする請求項5に記載のトランジスタ。 - 前記ソースバスが、前記上部及び下部ラインの間の各列の全体にわたって連続的に延びる、
ことを特徴とする請求項4に記載のトランジスタ。 - 前記ソースバスが、前記上部及び下部ラインの間の各列の全体にわたり且つ前記スタブラインのペアの前記第1及び第2のスタブラインの周りに連続的に延びる、
ことを特徴とする請求項5に記載のトランジスタ。 - 基板と、
複数のセクションに編成された複数のトランジスタセグメントと、
を備えたトランジスタであって、
前記各トランジスタセグメントが長さ及び幅を有し、前記各セクションのトランジスタセグメントが前記幅に沿って並列関係で配列され、前記セクションが列及び行の形態で配列され、前記セクション間で前記トランジスタセグメントの長さが第1の横方向と該第1の横方向と直交する第2の横方向とで交互に整列されるように前記各列のセクションが配列されており、前記各トランジスタセグメントが、
前記基板の上面又はその近傍に配置されたソース領域を有する半導体材料のピラーと、
前記ピラーの両側にそれぞれ配置された、前記ピラーによって横方向に囲まれた第1の誘電領域及び前記ピラーを横方向に囲む第2の誘電領域と、
前記第1及び第2の誘電領域内にそれぞれ配置された第1及び第2のフィールドプレートと、
ボディ領域に隣接する前記ピラーの上部又はその近傍で前記第1及び第2の誘電領域内にそれぞれ配置された第1及び第2のゲート部材と、
含み、前記トランジスタが更に、
前記各トランジスタセグメントのソース領域に結合されたソースバスと、各トランジスタセグメントの前記第1及び第2のゲート部材に結合されたゲートバスとを含む第1の金属層を備え、
前記ゲートバスが各列に関連する上部ライン及び下部ラインを含み、前記第1の横方向に整列された前記セグメントの長さを備えたセクションが各々、前記上部ラインに結合された前記第1及び第2のゲート部材の第1のセットと、前記下部ラインに結合された前記第1及び第2のゲート部材の第2のセットとを有する、
ことを特徴とするトランジスタ。 - 前記ピラーが、前記第1及び第2の横方向内に延びてレーストラック形のリング又は楕円を形成する、
ことを特徴とする請求項10に記載のトランジスタ。 - 前記第1のセットが、前記セグメントの前記第1及び第2のゲート部材の半分を含む、
ことを特徴とする請求項10に記載のトランジスタ。 - 前記ピラーが前記基板を通って垂直に延びており、前記ピラーが更に、
拡張ドレイン領域と、
前記ソース領域と前記拡張ドレイン領域とを垂直方向に分離するボディ領域と、
を含む、
ことを特徴とする請求項10に記載のトランジスタ。 - 前記ゲートバスが更に、スタブラインのペアを備え、前記セグメントの長さが前記第2の横方向で整列された各セクションについて、前記第1及び第2のゲート部材の第3のセットが前記スタブラインのペアのうちの第1のスタブラインに結合され、前記第1及び第2のゲート部材の第4のセットが前記スタブラインのペアのうちの第2のスタブラインに結合される、
ことを特徴とする請求項10に記載のトランジスタ。 - 前記スタブラインのペアのうちの前記第1のスタブラインが、前記上部ラインに結合され、前記スタブラインのペアのうちの前記第2のスタブラインが、前記下部ラインに結合される、
ことを特徴とする請求項14に記載のトランジスタ。 - 前記第3のセットが、前記セグメントの第1及び第2のゲート部材の半分を含む、
ことを特徴とする請求項15に記載のトランジスタ。 - 前記ソースバスが、前記上部ラインと下部ラインとの間の各列の全体にわたって連続的に延びる、
ことを特徴とする請求項10に記載のトランジスタ。 - 前記ソースバスが、前記上部及び下部ラインの間の各列の全体にわたり且つ前記スタブラインのペアの前記第1及び第2のスタブラインの周りに連続的に延びる、
ことを特徴とする請求項14に記載のトランジスタ。 - 基板と、
複数のセクションに編成された複数のトランジスタセグメントと、
を備えたトランジスタであって、
前記各トランジスタセグメントが長さ及び幅を有し、前記各セクションのトランジスタセグメントが前記幅に沿って並列関係で配列され、前記セクションが列及び行の形態で配列され、前記セクション間で前記トランジスタセグメントの長さが第1の横方向と該第1の横方向と直交する第2の横方向とで交互に整列されるように前記各列のセクションが配列されており、前記各トランジスタセグメントが、
前記基板の上面又はその近傍に配置された、半導体材料のレーストラック形ピラーと、
前記ボディ領域に隣接する前記ピラーの両側にそれぞれ配置された第1及び第2のゲート部材と、
含み、前記トランジスタが更に、
前記各トランジスタセグメントのソース領域に結合されたソースバスと、前記各トランジスタセグメントの前記第1及び第2のゲート部材に結合されたゲートバスとを含む第1の金属層を備え、
前記ゲートバスが各列に関連する上部ライン及び下部ラインを含み、前記ソースバスが、前記上部ラインと下部ラインとの間の各列の全体にわたって連続的に延びる、
ことを特徴とするトランジスタ。 - 前記第1の横方向に整列した前記セグメントの長さを有するセクションが各々、前記上部ラインに結合された前記第1及び第2のゲート部材の第1のセットと、前記下部ラインに結合された前記第1及び第2のゲート部材の第2のセットとを有する、
ことを特徴とする請求項19に記載のトランジスタ。 - 前記ゲートバスが更にスタブラインのペアを備え、前記セグメントの長さが前記第2の横方向で整列された各セクションについて、前記第1及び第2のゲート部材の第3のセットが前記スタブラインのペアのうちの第1のスタブラインに結合され、前記第1及び第2のゲート部材の第4のセットが前記スタブラインのペアのうちの第2のスタブラインに結合される、
ことを特徴とする請求項19に記載のトランジスタ。 - 前記スタブラインのペアのうちの前記第1のスタブラインが、前記上部ラインに結合され、前記スタブラインのペアのうちの前記第2のスタブラインが、前記下部ラインに結合される、
ことを特徴とする請求項21に記載のトランジスタ。 - 前記第3のセットが、前記セグメントの第1及び第2のゲート部材の半分を含む、
ことを特徴とする請求項21に記載のトランジスタ。 - 前記各セグメントが更に、
前記ピラーの両側にそれぞれ配置された、前記ピラーによって横方向に囲まれた第1の誘電領域と、前記ピラーを横方向に囲む第2の誘電領域と、
前記第1及び第2の誘電領域内にそれぞれ配置された第1及び第2のフィールドプレートと、
を備える、
ことを特徴とする請求項19に記載のトランジスタ。
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US7859037B2 (en) * | 2007-02-16 | 2010-12-28 | Power Integrations, Inc. | Checkerboarded high-voltage vertical transistor layout |
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2007
- 2007-02-16 US US11/707,403 patent/US7468536B2/en active Active
- 2007-11-28 EP EP11168216A patent/EP2365533A3/en not_active Withdrawn
- 2007-11-28 EP EP07254619A patent/EP1959500B1/en not_active Not-in-force
- 2007-11-28 EP EP20130152055 patent/EP2587545A1/en not_active Withdrawn
- 2007-11-28 AT AT07254619T patent/ATE513315T1/de not_active IP Right Cessation
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2008
- 2008-02-15 JP JP2008064895A patent/JP2008205484A/ja active Pending
- 2008-02-18 CN CN2008100807532A patent/CN101246907B/zh active Active
- 2008-02-18 CN CN201110119758.3A patent/CN102201344B/zh not_active Expired - Fee Related
- 2008-11-12 US US12/291,569 patent/US7732860B2/en active Active
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2013
- 2013-02-04 JP JP2013019567A patent/JP5637571B2/ja not_active Expired - Fee Related
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JP2012204529A (ja) * | 2011-03-24 | 2012-10-22 | Toshiba Corp | 半導体装置及びその製造方法 |
WO2022201903A1 (ja) * | 2021-03-22 | 2022-09-29 | ローム株式会社 | 半導体装置 |
Also Published As
Publication number | Publication date |
---|---|
CN102201344B (zh) | 2014-01-15 |
EP1959500A3 (en) | 2009-06-03 |
CN101246907A (zh) | 2008-08-20 |
JP5637571B2 (ja) | 2014-12-10 |
EP2365533A2 (en) | 2011-09-14 |
US7732860B2 (en) | 2010-06-08 |
US20080197396A1 (en) | 2008-08-21 |
EP1959500B1 (en) | 2011-06-15 |
US7468536B2 (en) | 2008-12-23 |
EP1959500A2 (en) | 2008-08-20 |
US20090072302A1 (en) | 2009-03-19 |
EP2587545A1 (en) | 2013-05-01 |
CN102201344A (zh) | 2011-09-28 |
EP2365533A3 (en) | 2011-09-28 |
ATE513315T1 (de) | 2011-07-15 |
CN101246907B (zh) | 2011-06-22 |
JP2013080976A (ja) | 2013-05-02 |
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