JP2008165226A - Liquid crystal display device, driving circuit for liquid crystal display device, and driving method for liquid crystal display device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To prevent an abnormal image from being displayed in a power-off state. <P>SOLUTION: A driving circuit includes: a liquid crystal panel; a timing controller for receiving control signals and data signals from an external system, for controlling a gate driver and a data driver according to the control signal, and for providing the data signals to the data driver alternately, frame by frame, in order; a discharging circuit coupled to the timing controller and the gate driver for turning on a plurality of thin film transistors for a predetermined period in a power-off state; and a power supply for supplying driving power of the gate driver, the data driver, the discharging circuit, timing controller, and liquid crystal panel. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a liquid crystal display device, and more particularly, to a liquid crystal display device, a liquid crystal display device driving circuit, and a liquid crystal display device driving method capable of preventing display of an abnormal image at power-off. .

  The general image driving principle of a liquid crystal display device uses the optical anisotropy and polarization properties of liquid crystal. Since the liquid crystal has a thin and long structure, it has an optical anisotropy having a directionality of the alignment and a polarization property in which the directionality of the molecular arrangement changes depending on the size when placed in an electric field. A liquid crystal display device has a liquid crystal panel composed of a pair of transparent substrates each having an electric field generating electrode formed on surfaces facing each other with a predetermined distance between the liquid crystal layers. The arrangement direction of the liquid crystal molecules is arbitrarily adjusted by changing the electric field, and the light transmittance is changed to express various images.

  A liquid crystal display device is configured by joining an array substrate on which a thin film transistor and a pixel electrode are formed and a color filter substrate on which a color filter and a common electrode are formed with a predetermined distance therebetween, and injecting a liquid crystal material between the substrates. And a drive circuit for electrically driving the liquid crystal panel.

  FIG. 1 is a block diagram schematically showing a basic configuration of a general liquid crystal display device, and shows a liquid crystal panel 10 for displaying an image and a plurality of drive circuits 60 for driving the liquid crystal panel 10. .

  As shown in FIG. 1, the liquid crystal panel 10 includes a plurality of gate lines (GL1 to GLn) and a plurality of data lines (DL1 to DLm) arranged on a glass substrate. Is defined as a pixel region, and in each pixel region, a thin film transistor T, a liquid crystal capacitor Clc, and a storage capacitor Cst are configured to display an image.

  The timing controller 20 includes a gate driver 30 composed of a plurality of drive integrated circuits and a data driver 40 composed of a plurality of drive integrated circuits using a plurality of control signals input from an external system (not shown). A control signal for driving is generated and supplied.

  The gate driver 30 performs on / off control of the thin film transistors T arranged on the liquid crystal panel 10 in response to a control signal input from the timing controller 20. The gate driver 30 controls the gate lines GL1 to GLn on the liquid crystal panel 10 by one horizontal. By sequentially enabling each synchronization time 1H, the thin film transistors T on the liquid crystal panel 10 are sequentially driven for each line, and an analog data signal supplied from the data driver 40 is applied to the pixels connected to the respective thin film transistors T.

  The data driver 40 selects the reference voltage of the input data in response to the control signal input from the timing controller 20 and supplies the selected reference voltage to the liquid crystal panel 10 to control the rotation angle of the liquid crystal molecules.

  The power supply unit 50 supplies operation power for the components 20, 30, and 40 and generates and supplies a common electrode voltage for the liquid crystal panel 10.

  In the liquid crystal display device having such a structure, at the time of power-off, each thin film transistor T is also turned off, and the data signals already charged in the liquid crystal capacitor Clc and the storage capacitor Cst remain without being discharged, and the liquid crystal panel is driven for a predetermined time. And an afterimage may remain on the screen or an abnormal screen may be driven.

  An object of the present invention is to provide a liquid crystal display device, a liquid crystal display device driving circuit, and a liquid crystal display device driving method for discharging a data signal remaining in a pixel when the liquid crystal display device is powered off.

  In order to achieve the above-described object, a liquid crystal display device according to the present invention includes a plurality of gate lines and data lines, and a liquid crystal panel including a plurality of thin film transistors connected to the plurality of gate lines and data lines; A timing controller that receives a control signal and a data signal from a system, controls a gate driver and a data driver in response to the control signal, and alternately supplies the data signal to the data driver in units of frames; A discharge circuit connected to the timing controller and the gate driver to turn on the plurality of thin film transistors for a predetermined period when the power is turned off; and supply power for driving the gate driver, the data driver, the discharge circuit, the timing controller, and the liquid crystal panel Power supply Characterized in that it comprises and.

  The liquid crystal display driving circuit according to the present invention includes a plurality of gate lines and data lines, and a plurality of switching elements connected to the plurality of gate lines and data lines. A data driver for applying a plurality of data signals to a plurality of data lines; a gate driver for applying a plurality of gate signals to the plurality of gate lines; and providing a plurality of control signals to the data driver and the gate driver A power supply unit for generating a driving voltage; and a discharge circuit for applying first and second signals to the gate driver according to the driving voltage.

  Further, the driving method of the liquid crystal display device according to the present invention includes driving a plurality of gate lines and data lines, a plurality of switching elements connected to the plurality of gate lines and data lines, and the plurality of gate lines. In a driving method of a liquid crystal display device including a gate driver, generating a driving voltage; detecting the driving voltage; turning on the plurality of switching elements when the driving voltage is detected lower than a reference voltage Applying a first signal to the gate driver.

  In the liquid crystal display device according to the present invention, when the liquid crystal display device is powered off, a data signal remaining in the pixel is discharged to prevent display of an abnormal image.

  In addition, a drive circuit that functions as three voltage detection ICs may be implemented by one or two voltage detection ICs, thereby reducing costs.

First Embodiment FIG. 2 is an equivalent circuit diagram of one pixel for explaining a discharge loop of a thin film transistor in a liquid crystal display device according to the present invention. As shown in FIG. 2, the liquid crystal display device according to the present invention, after power-off, applies a predetermined turn-on voltage through the gate line GL connected to the thin film transistor T to charge the liquid crystal capacitor Clc and the storage capacitor Cst. A discharging circuit for discharging the data signal that has been generated.

  FIG. 3 is a block diagram schematically showing the structure of the liquid crystal display device according to the first embodiment of the present invention. As shown in FIG. 3, the liquid crystal display device according to the first embodiment of the present invention includes a liquid crystal panel 100 that displays an image and a plurality of drive circuits 160 that drive the liquid crystal panel 100.

  In the liquid crystal panel 100, a plurality of gate lines (GL1 to GLn) and a plurality of data lines (DL1 to DLm) are arranged to intersect on a substrate using glass, and this intersection is defined as a pixel region. In the pixel region, a thin film transistor T, a liquid crystal capacitor Clc, and a storage capacitor Cst are configured to display an image.

  The drive circuit 160 includes a timing controller 120, a gate driver 130, a data driver 140, a power supply unit 150, and a discharge circuit 190.

  The timing controller 120 uses a plurality of control signals input from an external system (not shown) to drive a gate output enable signal (hereinafter referred to as GOE) for driving a gate driver 130 composed of a plurality of drive integrated circuits. Then, a gate control signal such as a gate shift clock signal (hereinafter referred to as GSC) and a gate start pulse signal (hereinafter referred to as GSP) is generated and supplied.

  The timing controller 120 also includes a source output enable signal (hereinafter referred to as SOE), a source sampling clock signal (hereinafter referred to as SSC), and a polarity inversion signal (hereinafter referred to as SSC) for driving a data driver 140 composed of a plurality of drive integrated circuits. Hereinafter, a data control signal such as POL) and a source start pulse signal (hereinafter, SSP) is generated and a data signal (Vdata) is supplied.

  The timing controller 120 generates a flicker removal signal FLK and a power supply maintenance signal DPM_VCC that are used to drive the discharge circuit 190, and supplies the flicker removal signal FLK and the gate shift clock signal GSC to the discharge circuit 190.

  The gate driver 130 performs on / off control of the thin film transistors T arranged on the liquid crystal panel 100 in response to a control signal input from the timing controller 120. The gate driver 130 controls the gate lines (GL1 to GLn) on the liquid crystal panel 100. The thin film transistors T on the liquid crystal panel 100 are sequentially driven one line at a time by sequentially enabling each horizontal synchronization time 1H, and an analog data signal supplied from the data driver 140 is applied to the pixels connected to the thin film transistors T.

  The data driver 140 selects a reference voltage of input data in response to a control signal input from the timing controller 120 and supplies the selected reference voltage to the liquid crystal panel 100 to control the rotation angle of the liquid crystal molecules.

  The power supply unit 150 supplies operation power VCC / VDD / GND for each of the components 120, 130, and 140, and generates a gate high voltage VGH and a gate low voltage VGL that are turn-on / off voltages of the thin film transistor T, in particular. The common electrode voltage Vcom of the liquid crystal panel 100 is generated and supplied.

  In addition, the discharge circuit 190 includes four circuits (see FIG. 4) that generate the discharge signal ALL_H and maintain the discharge signal ALL_H for a predetermined period. Of the input operation power supply VCC / VDD / GND, the VCC voltage When the voltage becomes 2.5 V or less, a discharge signal ALL_H having a high voltage level is generated, the gate driver 120 is controlled through the discharge signal ALL_H, and a high level signal is applied to the gate lines GL1 to GLm. Turn on all of them.

  Furthermore, the discharge circuit 190 generates a discharge maintenance signal VGH_M that maintains the discharge signal ALL_H for a predetermined period, and supplies the generated signal to the gate driver 130.

  Hereinafter, a driving circuit of the liquid crystal display device according to the first embodiment of the present invention will be described with reference to FIGS. 4 and 5A to 5C. FIG. 4 is a block diagram schematically showing the structure of the discharge circuit 190. As shown in FIG. 4, the discharge circuit 190 of the present invention includes first to fourth circuits 192, 194, 196, and 198 that are driven by receiving an input of the VCC / VDD / GND signal.

  More specifically, the first circuit 192 outputs a high level voltage signal when the input VCC voltage is 2.5 V or less. This signal is a discharge signal ALL_H and is supplied to the gate driver (130 in FIG. 3).

  As shown in FIG. 5A, the first circuit 192 is implemented with a first voltage detection IC 192a. The first voltage detection IC 192a includes a first resistor R1 and an external resistor for applying an appropriate signal. A first capacitor C1 is further provided.

  The second circuit 194 inputs the power maintenance signal DPM_VCC as the first modulation flicker signal V_FLK1 to the fourth circuit 198 when the input VCC voltage is 2.5V or less. Here, the power maintenance signal DPM_VCC is a signal that is maintained at a power management signal DPM of 1.6 V for a predetermined period. The power management signal DPM maintains a high potential when power is applied to the liquid crystal display device. When the power supply to the liquid crystal display device is cut off, it is a signal that maintains a low potential and determines the start point of the data signal Vdata.

  As shown in FIG. 5B, for example, the second circuit 194 is implemented by a second voltage detection IC 194a, and a second resistor is provided outside the second voltage detection IC 194a in order to apply an appropriate signal. The semiconductor device further includes R2, a second capacitor C2, and a PNP-type first transistor T1.

  The third circuit 196 receives the input of the flicker removal signal FLK or the gate shift clock signal GSC, and when the input VCC voltage is 2.5 V or less, the third circuit 196 receives the flicker removal signal FLK supplied to the fourth circuit 198. Restrict. Here, the flicker removal signal FLK is a signal for removing flicker generated in the liquid crystal display device, and serves to lower the voltage of the trailing side of the output gate drive signal by a constant voltage. The shift clock signal GSC is a signal applied with a relatively long high potential section and a relatively short low potential section within one week period. That is, when the VCC voltage is 2.5 V or more, the flicker removal signal FLK is input from the timing controller (120 in FIG. 3) and supplied to the fourth circuit 198 as the second modulation flicker signal V_FLK2, and the VCC voltage is 2. When the voltage is 5 V or less, no signal is supplied to the fourth circuit 198. At this time, the gate shift clock signal GSC can be supplied as the second modulation flicker signal V_FLK2 instead of the flicker removal signal FLK.

  As shown in FIG. 5C, the third circuit 196 is implemented by a third voltage detection IC 196a. The third voltage detection IC 196a has a fourth to an eighth signal for applying an appropriate signal. A resistor (R4 to R8), a third capacitor C3, and an NPN-type second transistor T2 are further provided.

  The fourth circuit 198 is a power block, corresponds to the first and second flicker modulation signals V_FLK1 and V_FLK2, generates a discharge sustain signal VGH_M, and supplies it to the gate driver (130 in FIG. 3). Therefore, the fourth circuit 198 discharges the gate drive signal by modulating the flicker removal signal FLK when the VCC voltage is 2.5 V or more, that is, when the liquid crystal display device is powered on. The sustain signal VGH_M is supplied to the gate driver (130 in FIG. 3). The fourth circuit 198 modulates the gate drive signal using the power sustain signal DPM_VCC when the VCC voltage is 2.5 V or less, that is, when the liquid crystal display device is powered off. Is supplied to the gate driver (130 in FIG. 3) to determine the sustain time of the discharge signal ALL_H.

  Next, referring to FIG. 6, FIG. 7A and FIG. 7B, the liquid crystal according to the second embodiment of the present invention in which the second and third circuits of the first embodiment are implemented by one voltage detection IC. A display device and a driving circuit thereof will be described.

Second Embodiment FIG. 6 is a block diagram showing a discharge circuit of a liquid crystal display device according to a second embodiment of the present invention. The remaining liquid crystal panel and driving circuit excluding the discharge circuit 290 are the same as those shown in FIG. 3, and FIGS. 7A and 7B show the discharge of the liquid crystal display device according to the second embodiment of the present invention. It is the circuit diagram which showed the 1st and 2nd circuit of the circuit.

  As shown in FIG. 6, the discharge circuit 290 according to the second embodiment of the present invention includes first to third circuits 292, 294, and 298 that are driven by receiving VCC / VDD / GND signals. ing.

  Here, the third circuit 298 is the same circuit as the fourth circuit (198 in FIG. 4) of the discharge circuit 190 according to the first embodiment, and is a power block that generates the discharge sustain signal VGH_M.

  More specifically, the first circuit 292 outputs a high-level voltage signal when the input VCC voltage is 2.5 V or less. This signal is a discharge signal ALL_H and is supplied to the gate driver (120 in FIG. 3).

  On the other hand, the second circuit 294 inputs the power maintenance signal DPM_VCC as the modulation flicker signal V_FLK to the third circuit 298 when the VCC voltage becomes 2.5 V or less. That is, when the VCC voltage is 2.5 V or more, the flicker removal signal FLK is input from the timing controller (120 in FIG. 3) and supplied to the third circuit 298 as the modulation flicker signal V_FLK. When the VCC voltage is less than 2.5 V, The power maintenance signal DPM_VCC is received from the timing controller (120 in FIG. 3) and supplied to the third circuit 298 as the modulation flicker signal V_FLK.

  Further, the third circuit 298 generates a discharge sustain signal VGH_M corresponding to the modulation flicker signal V_FLK and supplies it to the gate driver (130 in FIG. 3).

  As shown in FIG. 7A, the first circuit 292 is implemented by a first voltage detection IC 292a, and a first resistor R11 and a first capacitor C11 are provided outside the first voltage detection IC 292a in order to apply an appropriate signal. Is further provided.

  On the other hand, as shown in FIG. 7B, the second circuit 294 is implemented by the second voltage detection IC 294a, and the second to fourth resistors (R12) are provided outside the second voltage detection IC 294a in order to apply an appropriate signal. Or R14), a second capacitor C12, an NPN-type first transistor T11, and a PNP-type second transistor T12.

  More specifically, the first transistor T11 has a base connected to the output terminal Vout of the second voltage detection IC 294a, a collector connected to the input terminal of the flicker removal signal FLK, and an emitter connected to the output terminal of the modulation flicker signal V_FLK. The The second transistor T12 has a base connected to the output terminal Vout of the second voltage detection IC 294a, an emitter connected to the input terminal of the power maintenance signal DPM_VCC, and a collector connected to the output terminal of the modulation flicker signal V_FLK. It is.

  According to this, the VCC voltage, the on / off states of the first and second transistors T11 and T12, and the signal at the output end of the modulation flicker signal V_FLK are compared and described as shown in Table 1 below.

  Therefore, the second circuit 294 supplies the flicker signal FLK to the third circuit 298 as the modulation flicker signal V_FLK when the VCC voltage is 2.5 V or more, and the power supply maintaining signal when the VCC voltage is less than 2.5 v. DPM_VCC is supplied as a modulation flicker signal to the third circuit 298, and the third circuit 298 generates the discharge sustain signal VGH_M using the modulation flicker signal V_FLK and supplies it to the gate driver (130 in FIG. 3). Accordingly, a drive circuit that functions as three voltage detection ICs (19 in FIGS. 5A to 5C) can be implemented by the two voltage detection ICs 292a and 294a.

  Next, with reference to the drawings, a liquid crystal display device according to a third embodiment of the present invention in which the first to third circuits of the first embodiment are implemented by one voltage detection IC, and a driving circuit thereof Will be explained.

Third Embodiment FIG. 8 is a block diagram showing a discharge circuit of a liquid crystal display device according to a third embodiment of the present invention. The remaining liquid crystal panel and driving circuit excluding the discharge circuit 390 are the same as those shown in FIG. 3, and FIG. 9 shows the first discharge circuit of the liquid crystal display device according to the third embodiment of the present invention. It is the circuit diagram which showed the circuit.

  As shown in FIG. 8, the discharge circuit 390 according to the third embodiment of the present invention includes first and second circuits 392 and 398 that are driven by receiving an input of the VCC / VDD / GND signal. .

  Here, the second circuit 398 is the same circuit as the fourth circuit (198 in FIG. 4) of the discharge circuit (190 in FIG. 4) according to the first embodiment.

  More specifically, the first circuit 392 outputs a high level voltage signal when the input VCC voltage is 2.5 V or less. This signal is a discharge signal ALL_H and is supplied to the gate driver (120 in FIG. 3).

  Further, when the VCC voltage becomes 2.5 V or less, the power supply maintenance signal DPM_VCC is input to the second circuit 398 as the modulation flicker signal V_FLK. That is, when the VCC voltage is 2.5 V or more, the flicker removal signal FLK is input from the timing controller (120 in FIG. 3) and supplied to the second circuit 298 as the modulation flicker signal V_FLK, and the VCC voltage is 2.5 V or less. Then, the power supply maintenance signal DPM_VCC is supplied to the second circuit 298 as the modulation flicker signal V_FLK.

  The second circuit 398 is a power block, generates a discharge sustain signal VGH_M corresponding to the modulation flicker signal V_FLK, and supplies it to the gate driver (130 in FIG. 3).

  As shown in FIG. 9, for example, the first circuit 392 is implemented by a voltage detection IC 392a. The first to third resistors (external to the voltage detection IC 392a) are applied to an appropriate signal. R21 to R23), a first capacitor C21), an NPN-type first transistor T21, and a PNP-type second transistor T22.

  More specifically, the NPN first transistor T21 has a base connected to the output terminal Vout of the voltage detection IC 392a, a collector connected to the input terminal of the flicker removal signal FLK, and an emitter connected to the output terminal of the modulation flicker signal V_FLK. Is done. The PNP-type second transistor T22 has a base connected to the output terminal Vout of the voltage detection IC 398a, an emitter connected to the input terminal of the power maintenance signal DPM_VCC, and a collector connected to the output terminal of the modulation flicker signal. It is.

  According to this, the VCC voltage, the ON / OFF state of the first and second transistors T21 and T22, and the signal at the output end of the modulation flicker signal V_FLK are compared and described as shown in Table 2 below.

  Therefore, the first circuit 392 supplies the flicker signal FLK to the second circuit 398 as the modulation flicker signal V_FLK when the VCC voltage is 2.5 V or more, and the discharge signal ALL_H when the VCC voltage is less than 2.5 V. Is simultaneously supplied to the gate driver (130 in FIG. 3), the power supply maintenance signal DPM_VCC is supplied as a modulation flicker signal to the second circuit 398, and the second circuit 398 uses the modulation flicker signal V_FLK to maintain the discharge maintenance signal VGH_M. Is supplied to the gate driver (130 in FIG. 3). Thus, a drive circuit that functions as three voltage detection ICs can be implemented as one voltage detection IC.

Fourth Embodiment FIG. 10 is a circuit diagram showing a first circuit of a discharge circuit of a liquid crystal display device according to a fourth embodiment of the present invention. As shown in FIG. 10, the first circuit 492 is implemented with a voltage detection IC 492a, and the first to fourth resistors (R31 to R34) are connected to the outside of the voltage detection IC 492a in order to apply an appropriate signal. The semiconductor device further includes a first capacitor C31, an NPN-type first transistor T31, and a PNP-type second transistor T32.

  More specifically, the NPN-type first transistor T31 has a base connected to the output terminal Vout of the voltage detection IC 492a, a collector connected to the input terminal of the flicker removal signal FLK or the gate shift clock signal GSC, and an emitter connected to the modulation flicker signal. It is connected to the output terminal of V_FLK. The PNP-type second transistor T32 has a base connected to the output terminal Vout of the voltage detection IC 498a, an emitter connected to the input terminal of the power maintenance signal DPM_VCC, and a collector connected to the output terminal of the modulation flicker signal. It is. Here, the first and fourth resistors R31 and R34 have a relatively low resistance value, and one of the first and fourth resistors R31 and R34 is connected, and the flicker removal signal FLK and the gate shift clock signal GSC are connected. Is supplied to the first transistor T31.

  Therefore, the first circuit 492 supplies the flicker signal FLK or the gate shift clock signal GSC to the second circuit (not shown) as the modulation flicker signal V_FLK when the VCC voltage is 2.5 V or more, and the VCC voltage is When the voltage is less than 2.5 V, the discharge signal ALL_H is supplied to the gate driver (130 in FIG. 3), and at the same time, the power maintenance signal DPM_VCC is supplied to the second circuit (not shown) as a modulation flicker signal.

  FIG. 11 is a waveform diagram showing signal waveforms during operation of the liquid crystal display device according to the first to fourth embodiments of the present invention. As shown in FIG. 11, after the gate shift clock signal GSC is enabled, the gate lines GL1 to GLn are sequentially enabled after a predetermined delay period in synchronization with the gate shift clock signal GSC. When the discharge signal ALL_H is subsequently enabled, all the gate lines (GL1 to GLn) are simultaneously enabled in synchronization with the subsequent gate lines (GL1 to GLn). . It is desirable that all the gate lines (GL1 to GLn) are simultaneously enabled by the discharge signal ALL_H for a time sufficient to discharge the charges charged in all the pixels, and this time is about 3 msec or more. .

  Although the foregoing has been described with reference to the preferred embodiments of the present invention, those skilled in the relevant art will not depart from the spirit and scope of the invention as described in the claims. It will be understood that various modifications and changes can be made to the present invention within the scope.

It is the block diagram which showed schematically the basic composition of the general liquid crystal display device. FIG. 3 is an equivalent circuit diagram of one pixel for explaining a discharge loop of a thin film transistor of the liquid crystal display device according to the present invention. 1 is a block diagram schematically showing the structure of a liquid crystal display device according to a first embodiment of the present invention. FIG. 4 is a block diagram schematically showing a structure of a discharge circuit in the liquid crystal display device of FIG. 3. FIG. 5 is a block diagram showing the discharge circuit shown in FIG. 4 in more detail. FIG. 5 is a block diagram showing the discharge circuit shown in FIG. 4 in more detail. FIG. 5 is a block diagram showing the discharge circuit shown in FIG. 4 in more detail. FIG. 5 is a block diagram schematically showing a structure of a liquid crystal display device according to a second embodiment of the present invention. It is the circuit diagram which showed the 1st circuit of the discharge circuit of the liquid crystal display device by the 2nd Embodiment of this invention. It is the circuit diagram which showed the 2nd circuit of the discharge circuit of the liquid crystal display device by the 2nd Embodiment of this invention. It is the block diagram which showed the discharge circuit of the liquid crystal display device by the 3rd Embodiment of this invention. It is the circuit diagram which showed the 1st circuit of the discharge circuit of the liquid crystal display device by the 3rd Embodiment of this invention. It is the circuit diagram which showed the 1st circuit of the discharge circuit of the liquid crystal display device by the 4th Embodiment of this invention. FIG. 5 is a waveform diagram showing signal waveforms during operation of the liquid crystal display device according to the first to fourth embodiments of the present invention.

Explanation of symbols

100: Liquid crystal panel 120: Timing controller 130: Gate driver 140: Data driver 150: Power supply unit 160: Drive circuit 190: Discharge circuit

Claims (38)

A liquid crystal panel including a plurality of gate lines and data lines, and a plurality of thin film transistors connected to the plurality of gate lines and data lines;
A timing controller that receives a control signal and a data signal from an external system, controls a gate driver and a data driver in response to the control signal, and supplies the data signal to the data driver alternately in a frame unit;
A discharge circuit connected to the timing controller and the gate driver to turn on the plurality of thin film transistors for a predetermined period when the power is turned off;
A liquid crystal display device comprising: a gate driver, a data driver, a discharge circuit, a timing controller, and a power supply unit for supplying driving power to the liquid crystal panel. 2. The discharge circuit according to claim 1, wherein the discharge circuit receives a flicker removal signal FLK and a power management signal DPM from the timing controller and outputs a discharge signal ALL_H for turning on the plurality of thin film transistors to the gate driver. The liquid crystal display device described. The timing controller generates a plurality of gate control signals for controlling the gate driver, and the plurality of gate control signals include a gate output enable signal GOE, a gate shift clock signal GSC, and a gate start pulse signal GSP. The liquid crystal display device according to claim 1. The timing controller generates a plurality of data control signals for controlling the data driver, and the plurality of data control signals include a source output enable signal SOE, a source sampling clock signal SSC, a polarity inversion signal POL, and a source start pulse. The liquid crystal display device according to claim 1, comprising a signal SSP. The discharge circuit is:
A first circuit for generating a discharge signal ALL_H for turning on the plurality of thin film transistors for a predetermined period according to the magnitude of the input VCC driving voltage;
A second circuit that outputs a power maintenance signal DPM_VCC that maintains the power management signal DPM for a predetermined period according to the magnitude of the VCC drive voltage as the first modulation flicker signal V_FLK1;
The third flicker removal signal FLK and the gate shift clock signal GSC are received, and the flicker removal signal FLK or the gate shift clock signal GSC is output as the second modulation flicker signal V_FLK2 signal according to the magnitude of the VCC drive voltage. With circuit;
The discharge maintenance signal VGH_M that receives the power management signal DPM and the first and second modulation flicker signals V_FLK1 and V_FLK2 supplied from the second and third circuits and maintains the discharge signal ALL_H for a predetermined period of time. The liquid crystal display device according to claim 1, further comprising: a fourth circuit that supplies the timing controller. 6. The liquid crystal display device according to claim 5, wherein the first circuit includes a resistor and a capacitor, and one voltage detection IC that outputs the discharge signal ALL_H according to a magnitude of the VCC driving voltage. The second circuit includes a plurality of resistors, a capacitor, a switching element that controls an output of the power supply maintenance signal DPM_VCC as the first modulation flicker signal V_FLK1, and the switching element according to the magnitude of the VCC driving voltage. The liquid crystal display device according to claim 5, further comprising a voltage detection IC that determines on / off. The liquid crystal display device according to claim 7, wherein the switching element is a PNP-type bipolar transistor. The third circuit includes a plurality of resistors, a capacitor, a switching element that controls the output of the flicker removal signal FLK or the gate shift clock signal GSC as the second modulation flicker signal V_FLK2, and the magnitude of the VCC drive voltage. The liquid crystal display device according to claim 5, further comprising: a voltage detection IC that determines ON / OFF of the switching element. The liquid crystal display device according to claim 9, wherein the switching element is an NPN bipolar transistor. The liquid crystal display device according to claim 5, wherein the discharge circuit generates the discharge signal ALL_H when the magnitude of the VCC drive voltage is 2.5 V or less. The discharge circuit is:
A discharge signal ALL_H for receiving a flicker removal signal FLK and a power maintenance signal DPM_VCC from the timing controller and turning on the plurality of thin film transistors for a predetermined period according to the magnitude of the inputted VCC drive voltage, and the magnitude of the VCC drive voltage A first circuit for outputting the power maintenance signal DPM_VCC or the flicker removal signal FLK as the modulation flicker signal V_FLK for maintaining the power management signal DPM for a predetermined period;
2. A second circuit that receives a modulation flicker signal V_FLK supplied from the first circuit and outputs a discharge maintenance signal VGH_M that maintains the discharge signal ALL_H for a predetermined period to the timing controller. 2. A liquid crystal display device according to 1. The first circuit includes a plurality of resistors, a capacitor, a first switching element that controls the output of the flicker removal signal FLK as the modulation flicker signal V_FLK, and the modulation flicker signal V_FLK of the power maintenance signal DPM_VCC. A second switching element that controls output; and a voltage detection IC that outputs the discharge signal ALL_H and determines on / off of the first and second switching elements according to the magnitude of the VCC drive voltage. The liquid crystal display device according to claim 12. The liquid crystal display device according to claim 13, wherein the first switching element is an NPN bipolar transistor, and the second switching element is a PNP bipolar transistor. In a driving circuit for a liquid crystal display device comprising a plurality of gate lines and data lines, and a plurality of switching elements connected to the plurality of gate lines and data lines,
A data driver for applying a plurality of data signals to the plurality of data lines;
A gate driver for applying a plurality of gate signals to the plurality of gate lines;
A timing controller for providing a plurality of control signals to the data driver and the gate driver;
A power supply for generating a drive voltage;
And a discharge circuit for applying first and second signals to the gate driver according to the drive voltage.   The first signal for turning on all of the plurality of switching elements is applied to the gate driver when the discharge circuit detects that the driving voltage is lower than a reference voltage. Drive circuit for liquid crystal display devices. When the discharge circuit detects that the driving voltage is lower than a reference voltage, the second signal corresponds to the power maintenance signal DPM_VCC,
When the discharge circuit detects that the drive voltage is higher than a reference voltage, the second signal corresponds to at least one of a flicker removal signal FLK and a gate shift clock signal GSC. Item 16. A drive circuit for a liquid crystal display device according to Item 15. The liquid crystal display device drive circuit according to claim 17, wherein the power supply maintenance signal DPM_VCC is a signal for maintaining a power management signal DPM for controlling a plurality of operation power supplies for a predetermined period. The driving circuit for a liquid crystal display device according to claim 18, wherein the power maintenance signal DPM_VCC determines a start point of the plurality of data signals. The discharge circuit is:
A first circuit that compares the drive voltage with a reference voltage and outputs the first signal when the drive voltage is lower than the reference voltage;
A second circuit that compares the drive voltage with the reference voltage and supplies a power maintenance signal DPM_VCC in response to the timing controller when the drive voltage is lower than the reference voltage;
A third circuit for comparing the drive voltage with the reference voltage and supplying a control signal in response to the timing controller when the drive voltage is higher than the reference voltage;
The drive circuit for a liquid crystal display device according to claim 15, further comprising: a power supply maintaining signal DPM_VCC and a fourth circuit that receives one of the control signals. The first circuit includes a first capacitor and a first voltage detection IC,
The second circuit includes a second capacitor, a first transistor, and a second voltage detection IC,
The drive circuit for a liquid crystal display device according to claim 20, wherein the third circuit includes a third capacitor, a second transistor, and a third voltage detection IC. 21. The driving circuit for a liquid crystal display device according to claim 20, wherein the control signal is one of a gate shift clock signal GSC and a flicker removal signal FLK that are input from the timing controller. The discharge circuit is:
A first circuit that compares the drive voltage with a reference voltage and outputs the first signal when the drive voltage is lower than the reference voltage;
When the driving voltage is lower than the reference voltage by comparing the driving voltage and the reference voltage, the power supply maintaining signal DPM_VCC is supplied in response to the timing controller, and when the driving voltage is higher than the reference voltage, A second circuit for providing a control signal in response to the timing controller;
The drive circuit for a liquid crystal display device according to claim 15, further comprising: a third circuit that receives the power maintenance signal DPM_VCC and the control signal. The first circuit includes a first capacitor and a first voltage detection IC,
The drive circuit for a liquid crystal display device according to claim 23, wherein the second circuit includes a second capacitor, a first transistor, a second transistor, and a second voltage detection IC. The drive circuit for a liquid crystal display device according to claim 23, wherein the control signal is one of a gate shift clock signal GSC and a flicker removal signal FLK that are input from the timing controller. The discharge circuit is:
When the driving voltage is lower than the reference voltage by comparing the driving voltage and the reference voltage, the first signal is output to supply the power maintenance signal DPM_VCC in response to the timing controller, and the driving voltage is A first circuit for providing a control signal in response to the timing controller if higher than a reference voltage;
The drive circuit for a liquid crystal display device according to claim 15, further comprising: a second circuit that receives either the power maintenance signal DPM_VCC and the control signal. The first circuit includes a capacitor, a first transistor that outputs the power maintenance signal DPM_VCC, a second transistor that outputs the control signal, and a first voltage detection IC that controls the first and second transistors. 27. The driving circuit for a liquid crystal display device according to claim 26. The first transistor is a PNP-type bipolar transistor,
The drive circuit for a liquid crystal display device according to claim 27, wherein the second transistor is an NPN bipolar transistor. 27. The driving circuit for a liquid crystal display device according to claim 26, wherein the control signal is one of a gate shift clock signal GSC and a flicker removal signal FLK received from the timing controller. In a driving method of a liquid crystal display device comprising a plurality of gate lines and data lines, a plurality of switching elements connected to the plurality of gate lines and data lines, and a gate driver for driving the plurality of gate lines,
Generating a drive voltage;
Detecting the drive voltage;
Applying the first signal for turning on the plurality of switching elements to the gate driver when the driving voltage is detected to be lower than a reference voltage. When the driving voltage is detected to be lower than the reference voltage, it corresponds to the power maintenance signal DPM_VCC, and when the driving voltage is detected to be higher than the reference voltage, the second signal corresponding to the control signal is supplied to the gate driver. The method for driving a liquid crystal display device according to claim 30, further comprising a step of applying to the liquid crystal display. The liquid crystal display device according to claim 31, wherein the step of applying the power maintenance signal DPM_VCC includes a step of applying a signal for maintaining a power management signal DPM for controlling a plurality of operation power sources for a predetermined period. Driving method. 32. The method of driving a liquid crystal display device according to claim 31, wherein the step of applying the first and second signals is performed by a single voltage detection IC. The step of applying the first signal is performed by a first voltage detection IC,
The method of driving a liquid crystal display device according to claim 31, wherein the step of applying the second signal is performed by a second voltage detection IC. The step of applying the first signal is performed by a first voltage detection IC,
32. The method of driving a liquid crystal display device according to claim 31, wherein the step of applying the second signal is performed by second and third voltage detection ICs. 32. The method of driving a liquid crystal display device according to claim 31, wherein the control signal is one of a gate shift clock signal GSC and a flicker removal signal FLK that are input from the timing controller. In a driving method of a liquid crystal display device comprising a plurality of gate lines and data lines, a plurality of switching elements connected to the plurality of gate lines and data lines, and a gate driver for driving the plurality of gate lines,
Generating a driving voltage during a normal operation mode and sequentially enabling the plurality of switching elements by row using the driving voltage;
And a step of simultaneously enabling the plurality of switching elements during a discharge period when the driving voltage is lower than a reference voltage after the normal operation mode. Applying one of a gate shift clock signal GSC and a flicker removal signal FLK to the gate driver during the normal operation mode;
38. The method of claim 37, further comprising: applying a power maintenance signal DPM_VCC to the gate driver during the discharge period.

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