TW200828252A - Liquid crystal display device and method of driving the same - Google Patents

Abstract

A driving circuit for driving a liquid crystal display device having a plurality of gate lines, data lines and switch elements connected to the gate and data lines includes a data driver for applying a plurality of data signals to the date lines, a gate driver for applying a plurality of gate signals to the gate lines, a timing controller for providing a plurality of control signals to the data and gate drivers, a power supply for generating a power voltage, and a discharging circuit for applying a first signal and a second signal to the gate driver in accordance with the power voltage.

Description

200828252 IX. Description of the Invention: [Technical Field] The present invention relates to a liquid crystal display device, and more particularly to a liquid crystal display device and a method of driving the same. Although the embodiments of the present invention are applicable to a wider range of applications, they are particularly directed to a liquid crystal display comprising a discharge circuit and a method of driving the same. [Prior Art] A liquid crystal display (LCD) device utilizes optical anisotropy and polarization characteristics of liquid crystal molecules to produce an image. The liquid crystal molecules have a long (four) shape and have an optical anisotropy, so that the liquid crystal molecules can be aligned along a straight line. The liquid crystal molecules also have a bias and a characteristic, and thus the alignment direction can be changed according to the intensity of an applied electric field. In particular, the alignment of the liquid crystal molecules can be changed by changing the intensity of the electric field. Thereby, the light age of the liquid crystal molecules is controlled by the field, and the liquid crystal display device displays an image based on the change in the light. In general, a liquid crystal display device includes a liquid crystal panel and a driving circuit. The liquid crystal panel comprises a first substrate and a second substrate spaced apart from each other, and a liquid crystal layer between the first substrate and the second substrate. The first substrate has a thin film transistor

A pixel electrode is generally considered to be an array substrate; the second substrate has a color=wave layer and a common electrode, which are generally considered to be color filter substrates. Drive circuit drive, crystal panel. Since the liquid crystal display device is a non-emissive device, the = crystal display device includes a light source, for example, a backlight unit, located under the liquid crystal panel. One is a schematic view of a prior art liquid crystal display device. In Fig. 1, a liquid crystal garment includes a liquid crystal panel 1G and a drive circuit 6G. The liquid crystal panel 1 〇 = a plurality of gates, lines GL1 to GLn, and a plurality of data, lines DL1 to DLm.稷, the hard line GL1 to GLn and the Wei Shi capital as the DLm cross definition ^ domain 'and each pixel area contains __ _ transistor (tft) '-liquid Ba capacitor||(Cle) and - storage capacitor Post the image. 5 200828252 = Produce 'information / (ICs) by signal. Further, the interpole driver 3A includes a plurality of gate integrated circuits 4A. , the timing controller 20 outputs the data signal to the data drive

r, ^ !°5 2〇 , ^flJ ^ A plurality of thin film transistors (TFTs) reciprocal operation. Turn on, using a single horizontal sync (1H) to be applied to the two cars in turn to make the gates, lines GL1 to GLn and thin film transistors (TFTs)

Body (TFT; iip; S 10 'the poor material signal is applied to the pixels in the pixel area of the liquid crystal panel 1 1 _ through the data lines 1 ^ 1 to DL m. The secondary ancestor 4G ' is based on the data control signal of the timing controller 2G Selecting Π, 考考电压' to apply the selected reference voltage to the liquid crystal panel 10, and to control the angle of rotation of one of the two molecules. The power supply 50 generates a voltage source for the controller 2 〇, gate driver 3〇 and data driver 4〇. In addition, the source source 5G generates a common voltage and supplies it to the liquid crystal panel 1〇. When the power of the crystal display device is turned off, the film is electro-crystal Following the shutdown, the data signal is stored in the liquid crystal capacitor (Clc) and the storage capacitor 2, /if, and is retained without being released. Because the aforementioned poor material b tiger does not normally drive the liquid crystal panel in a short time. The invention causes the liquid crystal panel to display an undesired image or an abnormal image. [Summary of the Invention] The present invention is directed to solving the prior art liquid crystal display device and driving Party The resulting one or more side problems, thereby avoiding the limitations of the prior art 200828252 and the disadvantages. The purpose is to provide a liquid crystal display device and a driving method thereof, i include a -discharge circuit for retaining a data signal. This application, t another purpose, is to provide a liquid crystal display device and a method for driving the same, including a voltage detecting integrated circuit (1C).

The additional advantages and features of the alum method will be apparent from the description in the following description, or may be through the implementation of the present invention, and the purpose and other advantages of the invention will be specifically written. The structure with Shen Shina 11 and __ was discovered and obtained. "Technical means for solving the problem" Root, for the purpose of the embodiments of the present invention, in order to achieve other advantages related to the truth: the general description of the '-drive circuit' for driving a plurality of gate lines, 2 lean lines, And a display device connected to the plurality of lobes to the off-line pole-off component, comprising: a data driver, applying a plurality of data signals to the squadron, driving the gate, driving the plurality of gate signals to the gate a line; a timing control: for a plurality of control nicknames to the data and gate driver; a power supply, using a power supply voltage; and a discharge circuit, according to the power supply will be a first signal and a A second signal is applied to the gate driver. In another aspect, a method of driving a liquid crystal display device, the liquid crystal display device having a plurality of gate lines, a plurality of data lines, a plurality of switching elements connected to the gate lines and the data lines, and a gate driver for Driving the gate line, comprising: generating a power voltage; detecting the power voltage; and applying a first signal to the gate driver when the power voltage is detected to be lower than a reference voltage, the first signal Turn all the switching elements on. In other aspects, a method of driving a liquid crystal display device, the liquid crystal display device having a plurality of gate lines, a plurality of data lines, a plurality of switching elements connected to the gate lines and the data lines, and a gate driver, Driving the gate line includes: generating a power supply voltage during an operation mode, and sequentially arranging the switching elements in a row and a row based on the power supply; after the operation mode, when the power supply voltage 7 200828252 Under the reference voltage 'make all of the switching elements operate synchronously during a discharge period. BRIEF DESCRIPTION OF THE DRAWINGS The invention will be described with reference to the following detailed description of the invention. The embodiments, in conjunction with the drawings and the component symbols, and which are described in more detail, can be implemented by those skilled in the art after studying this specification.

In accordance with an embodiment of the present invention, a liquid crystal display (LCD) device includes: a discharge circuit for solving a problem of a residual image or an abnormal image. Fig. 2 shows a circuit diagram of a discharge circuit of a residual data signal in a liquid crystal display device according to the present invention. In FIG. 2, after the power of the liquid crystal display device is turned off, a drain, a circuit (not shown) applies an open gate voltage to a gate line GL for a predetermined period of time, and then A thin film transistor (TFT) τ is turned on. The data signal remaining in a liquid crystal electric valley (Qc) and a storage capacitor (. lean) is discharged. 3 is a schematic view of a liquid crystal display device according to an embodiment of the present invention. 3, the liquid crystal display device comprises: a liquid crystal panel 1 for displaying an image and a driving circuit 16 for the liquid crystal display panel 100. The liquid crystal panel 1A includes a plurality of gate lines GL1 to GLn and a plurality of data lines Du to DLm. The plurality of gate lines GL1 to GLn and the plurality of data lines DL1 to DLm intersect to define a plurality of pixel regions, and each of the pixel regions includes: a thin film transistor (tft) t, a liquid crystal capacitor (Clc) And a storage capacitor (Cst) for displaying an image. The driving circuit 160 includes a timing controller 12A, a gate driver 130, two data drivers 140, a power supply 150 and a discharge circuit 19A. The timing controller 120 generates a gate drive control signal for the gate driver 130 by using a plurality of external signals of the external system, the gate driver 13A includes a plurality of gate integrated circuits (ICs), and is a data driver. 14〇 generates a data control signal, the resource 8 200828252 material driver 140 includes: a plurality of data integrated circuits (ICs). The gate control signal may include: a gate output enable signal (G0E), a gate shift clock signal and a gate, a pulse signal (GSP), and the data control signal may include: a source An output enable signal (SOE), a source sample clock signal (ssc), a polarity inversion signal (POL), and a source start pulse signal (ssp). Moreover, the timing controller outputs a material signal (Vdata) to the data driver 14A. In addition, the g-charger 120 generates a flicker signal (FLK) and a DPM hold signal (DPM_VCQ ,, the discharge circuit 190, and provides the flicker signal (FLK), the DpM hold signal (DPM-VCC) And the gate displacement clock signal (GSC) to the discharge circuit 19〇. 闸, according to the gate control signal of the If time controller 120, the gate driver 13〇 controls a plurality of thin film transistors in the liquid crystal display panel 100 ( The on/off operation of the TFTs) is not so long as the single horizontal sync_(m) is sequentially applied to the closed lines GL1 to GLn, and the thin film transistor TFTs are connected to the gate lines gli to GLn. When the crystal TFTs correspond to the opening of a single gate line, the data line is seen as 1 to the pixel applied to the pixel area of the liquid crystal panel 100. - The data control signal of the timing controller 120 is tested and provided. The reference voltage of the turn is to the liquid crystal panel 100 t to turn off the rotation angle of the liquid crystal molecules. The power supply 150 generates and supplies the secret voltage to the object controller 120, the data driver 14 and the discharge circuit 19A. ,

150 generates 7 gate high voltage VGH, - gate low voltage VGL sub and 'will be extremely high voltage (VGH) and gate low voltage ^ 3G, used to turn on and _ a plurality of thin film transistors (τρ, and will be common The voltage Vcom# is supplied to the liquid crystal panel. The discharge circuit 19G is included in a predetermined time_local circuit. For example, when the first electric discharge circuit 19G generates the discharge signal (ALL Η), the domain is secreted to _ The enchantment 13G can be mv. 200828252 The gate driver 130 is applied to all of the inter-pole lines GU to GLn according to the discharge signal (ALL_H) for turning on all of the predetermined time periods. The internal sustain discharge signal (ALLJi and ^2) is supplied to the gate driver 130: ^, for example, may exceed 3 megaseconds. Between the embodiments of the present invention, FIG. 4 is a liquid crystal display device. The block diagram of the first to third partial circuits of the discharge circuit for liquid crystal display according to an embodiment of the present invention includes: first, third, and third The fourth partial electric two = receiving the first, second and third hybrids VCCD I GND. Dragon VCC ^ The reference light scale, the local circuit 192 outputs a discharge signal (ALL-H) to the gate drive; = the test voltage can be approximately 2.5 V. "τ" The cutoff is shown in Figure 5, for example, the first A partial circuit 192 can include: a ♦ 2 test, circuit (IC) 192a. The first voltage can have a J ^ „outout and a ground terminal Vgd. The first partial IC (4) of the first capacitor C1 and When the voltage is equal to the cut-off reference voltage, the local η generates a power modulation signal dpm hold signal (dpm vcc) 1 _ signal (v-FLKl), And providing the fourth partial circuit original (four) signal DPM hold signal (DPM VCC) at the predetermined time DPM 5 Dm = the power supply modulation signal DPM of the start time of the ^5 贫 poor material signal is large, 'when the power supply modulation When the signal DPM has a high voltage, the voltage 'and' may be unknown when the power supply modulation dpm has a -_ voltage. As shown in FIG. 2, the second partial circuit 194 may include: Two voltage debt test 200828252 IC194a, a second capacitor C2, a second resistor R2, a third resistor And the second voltage detecting ici94a may have an output terminal ^, a power input terminal Vps and a ground terminal vg (j, and the first transistor D1 may be positive-negative-positive ( PNP) bipolar type. Since the output terminal 乂(10) of the second power detecting Icl94a is connected to the base of the first transistor τι, the second voltage detecting lci94a controls a transistor T1 and passes through the first transistor. T1 determines that DPM is guaranteed (DPM-VCC) as the first change flicker signal (V-FLK1). For example, when the second source voltage VCC is lower than the cut-off reference voltage, the DPM hold signal (DPM_vcc) is output from the two partial circuits 194 as the first change flicker signal (VjpLK1). Referring back to FIG. 4, when the first source voltage vcc is higher than the cutoff reference voltage, the third partial circuit 196 generates a flicker signal (FLK) as a second cancel signal (V_FLK2)' and provides it to the fourth. Local circuit 198. Therefore, the second circuit 196 receives the flicker signal (FLK) and a gate shift clock signal and controls the flicker signal (FLK) as the second change flicker signal (VJ?LK^. The flicker signal (FLK) is For the flicker phenomenon in the liquid crystal display panel'' According to the flicker signal (FLK), the rear of a gate pulse may be cut, so that the pulse corresponds to the gate displacement clock signal (GSC) for a single period long before = The region has a high voltage and has a low voltage in the short back region of the single period. When the source voltage VCC is higher than the cutoff reference voltage, the third partial circuit is provided from the timing controller 120 (in FIG. 3). a flicker signal (FLK) as a second change flicker signal (y-FLK2) to the fourth partial circuit 198, and when the source voltage vcc is lower than the cut reference voltage, the flicker signal (FLK) is not supplied to the fourth The partial circuit 198. Alternatively, the gate displacement clock signal (GSC) may be provided as the second change flicker signal (V_FLK2) instead of the flicker signal 2. ~ The second partial circuit 196 may be included as shown in FIG. 5C : A third voltage detection, 11〇96&, one The third capacitor (^, the fourth to eighth resistors are to the ruler ^, ^ and 1 ^ two transistors T2. The third voltage detection IC 196a can have an output terminal % hunger, a power input terminal Vps and a ground terminal Vgd And, the second transistor T2 can be a negative•positive-negative (ΝΡΝ) bipolar type. Because the third voltage detection 1〇9 known output terminal 11 200828252 is connected to the base of the second transistor T2, then The third ray detects the busy control of the second transistor T2, and determines that the flash signal (FLK) is the second change flicker signal (V-FLK2). For example, when the first source ν (refer to the _ signal ( FLK) is used as the first change from the third partial circuit 196. When the first-hybrid vcc is lower than the cut-off reference voltage (yLK2) output, the second partial power is used as the first Changing the flash signal (v-FLK1). ', π η - Figure 4, according to the first and second change flicker signal (v-flki) and holding the '^νΓ' τ ΛΖ local circuit 198, that is, the power module, Used to generate discharge protection!·"" Tiger (Η-Μ) and provide it to the gate driver 13. (Figure 3). Therefore, :ΐϊίΐ VCC is higher than the cut-off reference voltage 'LCD display Turn on, ^^ VGH-M, then the discharge hold signal (VGH-M) is supplied f ΪΞΪΪ 13G (in Figure 3)' to operate the liquid crystal display without flickering. When the 筮^带坚 VCC is lower than the cut reference When the voltage is applied, the liquid crystal display device is turned off, and the two-two-two-circuit circuit 198 and the DPM hold signal DPM~VCC are used to change the gate of the gate. The VGH-M is replaced by the VGH-M cat. 130 (in FIG. 3) is used to determine the interval between discharge signals (ALL-H). Although not shown in the drawing, at least two of the _th to third voltage detecting ICs 92a, 194a, and 196a may form a single ic. Fig. 6 is a circuit diagram showing a discharge circuit of a liquid crystal display device and Fig. 7β, respectively, showing a first embodiment and a second partial circuit of a liquid crystal display device according to another embodiment of the present invention. In Fig. 6, the discharge circuit t includes second, second and third partial circuits 292, 294 and 298 and a receiving first, third and third source voltages vcc, YQD and GND. When the first source is 1 乂〇: low _ when the reference voltage is cut off, the first partial circuit 292 outputs a discharge signal (^^L - H) to the gate driver (not shown). The cut-off reference voltage can be large, , , scoop:, ,, 2.5V. In addition, when the source voltage vcc is higher than the cut-off reference voltage, the 12th 200828252 two-part circuit 294 is a blinking signal from a timing controller (not shown) (the hole acts as a change flashing jg number (V- FLK) is supplied to the third partial circuit 298, and, ♦ when the source voltage vcc is lower than the cutoff reference voltage, a DPM: (DPM: VCC) is provided as a change flicker signal (V-FLK) To the third partial circuit 298. Similarly, for the fourth partial circuit 198 (in FIG. 4), the third circuit 298, that is, a power module, generates a discharge hold signal (VGH_M), which blinks according to the change. The signal (VJFLK) is supplied to the gate driver 13A (in FIG. 3). As shown in FIG. 7A, for example, the first partial circuit 292 may include a one-to-one detection integrated circuit (IC) 292a. A voltage detection 1 (:: 292 & can have a lightning source input terminal Vps, an output terminal v 〇 ut and a ground terminal vd. The second = can further include: a first capacitor C11 to the first detection of the voltage detection IC 292a Resistor R11. 丨, 罘罨 as shown in FIG. 7B, for example, the second partial circuit 2 Road (IC) 292a, a first - thunder pet crying I & detected to R14 盥 basket a δ 笙 brother an electrical state C12, brother one to fourth resistance Rl2 t ΐ transistor T11 to T12. The voltage fine (10) has The power supply f input terminal Vps and a ground terminal Vgd. In addition, the younger battery body T11 may be negative_positive_negative (turning T12 may be just like (10)) bipolar type. A ring resistance R13 connected to the Lai and Di (4) by the second resistor R13 is connected to the second transistor T12. 'm DPM-vcc is input to the body T12, and the emission of the six-body-one transistor T11 is performed. The body and the second transistor and DPM maintain the letter _M = 3), and the emitter of the Hi can be connected to the timing controller 12 〇 (the set of electrodes can be connected to the erbium and the second transistor T12 Electric = set Wang Le a partial circuit 298 (in Figure 6). One of the commercial voltage and - low voltage can refer to the first - source voltage batch output from the output of 13 200828252 voltage detection IC292a. According to the first secret The voltage vcc 3 circuit 292 changes the number of flash signals (V_FLK); the states of the crystals τη and T12 are displayed in the table! [Table 1]

-----------:_| With 丄丄V n in Table 1, when the first source voltage vcc is higher than the cut-off voltage, when it is on, it is lower than the domain Reference voltage. When the second source voltage VCC is in an on state, the first transistor T11 is turned on and the second transistor, T12 is turned off. When the first source voltage vcc is in the off state, the first body τι is turned off and the second transistor T12 is turned on. As a result, the first local power 292 outputs a flash signal in a state where the first source is turned on, and the DpM keeps the signal DPM-VCC as a state in which the first source voltage vcc is turned off. Change the blinking signal (v-FLK). Therefore, the first partial circuit 292 having a single voltage detecting IC 292a and the first, second and third partial circuits having the first, second and second detecting ICs 92a, 194a and 196a in FIG. The functions of 192, 194 and 196 are the same. Figure 8 is a block diagram of a discharge circuit of a liquid crystal display device according to another embodiment of the present invention. Although not shown in Fig. 8, the liquid crystal display device includes a liquid crystal panel and a driver, circuit components such as a meter, a driver, a data driver, and a power supply. In Fig. 8, a discharge circuit 390 includes first and second local circuits 392 and 398 and receives first, second and third voltage sources vcc, y^D and GND. When the first source voltage is lower than the cut reference voltage, the second partial circuit 392 outputs a discharge signal (ALL_H2) to the gate driver (not shown). The cut-off reference voltage is approximately 2.5V. In addition, when the source voltage VCC is higher than the cutoff reference voltage, the first partial circuit 392 is supplied as a change flicker signal (vjFLK) from a blinking signal (FLK) of a timing controller (not shown). 14 200828252 to the second partial circuit 398, and when the source voltage VCC is lower than the cutoff reference voltage, a DPM hold signal (DPM_VCC) is supplied to the second partial circuit 398 as a change flicker signal (VJFLK). Similarly, for the fourth partial circuit (in FIG. 4), the second partial circuit 398, that is, a power supply module, generates a discharge hold signal VGH_Μ and provides it to the gate according to the change flicker signal (VjpLK). Pole driver (in Figure 3).

According to the discharge circuit of the liquid crystal display device of the above-described embodiment of the present invention, Fig. 9 is a circuit diagram of a partial circuit of the second embodiment. As shown in FIG. 9, the first partial circuit 392 includes: a voltage detection integrated circuit (IC) 392a, a first capacitor C21, first to second resistors R21 to R23, and first and second electrodes. Crystals T21 and T22. The voltage extraction IC 292a has an output terminal Vout, a power input terminal Vps and a ground terminal Vgd. In addition, the first transistor T21 can be a negative (^n) bipolar type, and the second power The crystal T22 may be a positive-negative-positive (pNp) bipolar type. The base of the first transistor 41 is connected to the output Vout of the electric (IC) IC 392a through the second resistor leg, and the flicker signal (flk) is input to the collector of the first transistor T21 through the first resistor. Moreover, the base of the second transistor T22 is connected to the voltage detection 1 (the output end of the application) through the g-th body, and the DpM remains (DPM-VCC) is input to the emitter of the second transistor 32. The first transistor T21 body and the collector of the second transistor T22 are alternately output as FLK)' and the change (four) signal (V_FLKH乍 is DpM is held H, so the collector of the first transistor τ21 and the second The scoring body of the electro-crystal ^ T22 can be connected to the timing controller 12 () (in FIG. 3), and the emitter of the transistor T21 and the second transistor μ 22 a partial circuit 398 (in FIG. 8). The wood electrode of the crucible 22 can be connected to the second according to the first-source voltage vcc, the high voltage and the low voltage end = output voltage gamma IC 392a. The flicker signal v FL according to the change of the first partial circuit 392 = the young crystal T2 The status of the T22 and T22 can be displayed in Table 2 - ^ and the younger brother - the second brother [Table 2] 15 200828252

VCC T21 T22 V-FLK Turn on and turn off FLK Turn off and turn on DPM VCC, Tian 叩 paper team heart WT green music a source voltage VCC is higher than cut off Mai Khao Jian Jian, and when off state, it is lower than cut off Reference one

The voltage vCC is in an on state, and the first transistor T22 is turned off. When the first source voltage vcc is in the off state, the first transistor = 21 is turned off and the second transistor T22 is turned on. As a result, the first partial circuit 392 loses money (FLK) in the state of the source-source key vcc, and inputs $ DPM in the first source, the voltage VCC is off, and keeps en(DPM_VCC) 4, Flashing Tiger VJPLK. Therefore, in FIG. 8, there is a single voltage debt measurement IC 392a, the local circuit t 392 and the first, second, and third voltage detections K:sl92a, ma and the first, second, and third portions of FIG. Circuits 192, 194 and 196 have the same function. According to another embodiment of the present invention, Fig. 10 is a circuit diagram of two partial circuits of a discharge circuit of a liquid crystal display device. As shown in Figure i. As shown, the first partial circuit 492 is similar to the elements of the first partial circuit 392 in the figure. Therefore, the first partial circuit includes a voltage detecting integrated circuit (IC) 492a, a first snowing, and a first to second transistor voltage detecting IC 492a having an output terminal VGUt. - the power input terminal, and a ground terminal Vgd ^ additionally 'the first transistor T31 can be a negative-positive-negative (NpN) bipolar type, and the second transistor T32 can be positive-negative_positive ( pNp) bipolar type. In the first partial circuit 492, a timing signal (FLK) and a gate displacement clock signal (GSC) of the timing controller 12 (in FIG. 3) are input to the first and fourth resistors R34, respectively. First transistor T31_electrode. Therefore, when the = voltage source vcc lacks the cutoff reference voltage, the first transistor = at least one flicker signal (FLK) and the gate shift clock signal (4) c), as a modulated flicker signal (V- FLK). As a result, the first transistor T31 alternates with the first transistor 16200828252 crystal T32 to output the flicker signal FLK and the DPM hold signal DPM vcc as the change flicker signal V-FLK to the second partial circuit (not shown). In accordance with another embodiment of the present invention, Figure n is a time chart of a plurality of signals for chicken fluid. In FIG. η, a predetermined delay time is enabled after the gate displacement clock mark, and when a gate signal has a gate height ^^vgh, the plurality of gate lines GL1 to GLn and the gate are displaced. The clock signal (GSC) is synchronized in sequence. A gate output enable signal (G〇E) is a plurality of gate lines Gu to GLn dividing the gate signal. When the liquid crystal display device is turned off, the first source voltage (in FIG. 8) is lower than the cut-off reference voltage, and the discharge circuit 39A (in FIG. 8) outputs a low voltage during a predetermined time period of more than about 3 megaseconds. Discharge signal tiger (ALL-H). The cut reference voltage can be approximately 2.5 ν. As a result, all of the complex gate lines GL1 to GLn are enabled in synchronization with the low voltage of the discharge signal (ALL-H). Therefore, all of the transistor TFTs in the liquid crystal panel are turned on to effectively discharge the pixels. When the first source voltage VCC is higher than the cut-off reference voltage (on state), at least the flashing k number (FLK) and the gate displacement clock signal (gsc) are synchronized with each other for generating a Γ discharge holding signal ( VGH-M). Further, when the first source voltage vcc is lower than the cut-off reference voltage (off state), the DPM hold signal 1PM-VCC for determining the predetermined time period for discharging is used to generate the discharge hold signal (vgh_m). Therefore, the liquid crystal display device according to the embodiment of the present invention prevents the abnormal image from being displayed because the liquid crystal display device is turned off because the discharge circuit releases the pixel. Further, since the electric circuit includes the single-voltage system 1C, the driving circuit of the liquid crystal display device is simplified and the production cost of the liquid crystal display device is lowered. & Within the spirit and scope of the present invention, those skilled in the art will understand that the present embodiment can be modified or altered in different forms on the LCD screen. Therefore, all kinds of changes and refinements made within the scope and boundaries of the patent application should still be included in the scope of the patent application appended hereto. 17 is a schematic diagram of a liquid crystal display device of the prior art; FIG. 2 is a circuit diagram of a circuit for retaining data in a liquid crystal display device according to an embodiment of the present invention; BRIEF DESCRIPTION OF THE DRAWINGS FIG. 4 is a schematic diagram of a discharge circuit of a liquid crystal display device according to an embodiment of the present invention, which is respectively a circuit of a liquid crystal display device according to an embodiment of the present invention.

FIG. 6 is a circuit diagram of first to second partial circuits of a liquid crystal display of a liquid crystal display device according to another embodiment of the present invention, FIG. 7A to FIG. 7B, respectively. Figure 8 is a block diagram of a discharge circuit of a liquid crystal display device according to another embodiment of the present invention; Figure 9 is a circuit diagram of a first partial circuit of a discharge circuit of a liquid crystal display device according to another embodiment of the present invention; A circuit diagram of a partial circuit of a discharge circuit of a liquid crystal display device according to another embodiment of the present invention; and FIG. 11 shows a schedule of a plurality of signals for driving a liquid crystal display device according to another embodiment of the present invention. 】 10 LCD panel 20 timing controller 30 gate driver 40 data driver 50 power supply 60 drive circuit 100 liquid crystal panel 120 timing controller 130 gate driver 18 200828252 140 150 160 190 192 192a 194 194a 196 196a 198 290 292 292a 294 298 390 392 392a 398 492 492a Cl Cll C12 C2 C21 C3 C31 Poor material drive for power supply drive Circuit discharge circuit first partial circuit first voltage detection integrated circuit (1C) second partial circuit

Second voltage detection 1C third partial circuit

Third voltage detection 1C fourth partial circuit discharge circuit first partial circuit first detection integrated circuit (1C) second partial circuit third partial circuit discharge circuit first partial circuit voltage detection integrated circuit second partial circuit First partial circuit voltage detecting integrated circuit first capacitor first capacitor second capacitor second capacitor first capacitor third capacitor first capacitor 19 200828252 R1 R11 R12 to R14 R2 R21 to R23 R3 R31 to R34 R4 to R8 T1 T11 to T12 T2 T21 to T22 T31 to T32 first resistance first resistance second to fourth resistance second resistance first to third resistance third resistance first to fourth resistance fourth to eighth resistance first transistor First and second transistor second transistor first and second transistor first and second transistor 20

Claims (1)

200828252 X. Patent application scope · · 1β has a road for driving-liquid crystal display device, the liquid crystal display device has a data line, a plurality of connecting the interpolar line and the capital 2, and applying a plurality of data signals to the data a plurality of gate signals are applied to the gate lines; the drive U' provides a plurality of control signals to the data driver and the idler power supply for generating a power supply voltage; The first signal is applied to the gate driver by using the power supply voltage generated by the power supply of the month ij. 2 that she refers to the first item, the crane circuit, the towel, when the discharge circuit is debt: electricity, the voltage is lower than the - reference voltage, the first signal is applied to the interpole drive, and the first signal is All switching elements are turned on. 3. The driving circuit according to claim 1, wherein when the voltage is lower than the reference voltage, the second signal corresponds to the hold signal; and the port and the field discharge circuit detect that the power supply voltage is higher than the reference voltage. The number corresponds to at least one blinking signal and the gate pole displacement clock signal. A < 4 · as claimed in the patent specification 3, the chicken circuit, wherein ^ power modulation signal, used to control a plurality of sources _ in - pre- & 5 · as described in claim 4 The drive circuit, which, 誃. To determine the start time of a plurality of data signals.乂',, 1a with 6 · The drive circuit described in item 1 of the scope of the patent application, i r-side discharge circuit pack 21 200828252 contains: • a second partial circuit for comparing the power supply voltage with the external supply voltage When the voltage is lower than the reference voltage, the output of the first letter - "I and 'in the comparison power supply and the reference", and when the electric house is lower than the reference voltage, provide a simple signal response timing ^ u,, 'for comparison Supply voltage and voltage = a reference voltage, providing a control signal in response to a chronograph number in a fourth partial circuit for receiving the hold signal and control signal 7. tt, please call the drive circuit described in claim 6 "Hai second partial circuit comprises: a second capacitor, a voltage detecting integrated electrical first transistor and a second partial partial circuit comprising: - the first capacitor and the -1 - _ voltage detection The integrated circuit; and the second partial circuit includes a second lightning voltage flip circuit. 2H crystal and - third 8. The driving circuit according to the sixth aspect of the patent application is based on the driving circuit of the timing control _ pole displacement clock signal and the number 9. The discharge circuit packs electricity == and, when the power supply voltage is higher than the reference voltage 22 200828252, and a third partial circuit for receiving one of the hold signal and the control signal from the second partial circuit. The driving circuit of claim 9, wherein the first partial circuit comprises: a first capacitor and a first detecting integrated circuit; and the second partial circuit comprises: a second capacitor a first transistor and a second quadrature circuit. The driving circuit of claim 9, wherein the control signal is based on one of a gate displacement clock signal and a blinking signal from the timing controller. I2. ^Application of the driving circuit described in item i of the patent scope, wherein the discharge circuit includes a U-first-partial circuit 'for comparing the power supply voltage with the reference voltage, and the combination, when the low-point test voltage is used' The output of the first signal, when the power supply H is provided - the signal is maintained in response to the timing controller, and -, when 'provided - (four) signal response timing one; = two solids used to connect from the first partial circuit TM ^ i3. ^ Shen ^ According to the 12th item of the patent scope, the drive road includes: - capacitor, turn-off hold signal - the first, - (four) Hi control signal - the second transistor, and the control body, the wheel discharge detection integrated circuit . A worker / brother, a battery of electricity, contains a body - positive _ _ _ 23 23200828252 negative bipolar transistor 15 · 16. ϋ driving liquid shut-off method, Wei Jingxian thin has: a plurality of lean lines after the line Du, a plurality of gate drivers connected to the cut-off and driving gate lines generate a power supply voltage; 3 · detecting the aforementioned power supply voltage; and when the power supply voltage is When the voltage is lower than a reference voltage, a first gate drive 11 is applied, and the first signal is turned on and off. J to 17. The method according to claim 16 is applied to apply a second signal. To the gate driver, 3·where, when the detected power supply voltage is lower than the reference one hold signal, and when the power supply voltage is 2 唬 corresponds to the second signal corresponding to the control signal. The method of claim 17 is the method of claim 17, wherein the method of applying a power modulation signal is applied to the second beta plus the hold signal for a predetermined period of time. The system has a plurality of source voltages in a pre-19. As stated in the method of claim 17, the second signal is based on a single voltage_integration ^" plus the brother one and the twenty-first patent The method according to the method of item 17 is based on the -first dust detecting integrated circuit, the force applying = port =: the signal field - 1s is the system 24 200828252 according to a second voltage detecting integrated circuit. 21·If the method described in the πth item of the patent application is based on the first voltage detection, the first step is to detect the integrated circuit based on the second and third voltages. According to the method of the above-mentioned, the control signal is one of the clock signal and the scintillation signal of the gate displacement from the timing controller. 23·3 zone method 'The liquid crystal display device has a plurality of closed=pieces, and a gate driver for driving the gate line; comprising: 'Field 1', generating a power supply voltage, and based on the power supply voltage=off 7G parts : New-row-row arrangement; and after Jit' when the power is lower than the reference tilt, the switch will operate synchronously during the discharge period. 24' The method described in the 23rd patent, further The step includes: in the 2 mode, a control signal is applied to the gate driver, the = gate shifts one of the clock signal and the blinking signal; and during the 3 electrical period, a hold signal is applied to the gate driver.