CN103123770B - Power management circuit and gate electrode pulse modulation circuit thereof - Google Patents
Power management circuit and gate electrode pulse modulation circuit thereof Download PDFInfo
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- CN103123770B CN103123770B CN201110367500.5A CN201110367500A CN103123770B CN 103123770 B CN103123770 B CN 103123770B CN 201110367500 A CN201110367500 A CN 201110367500A CN 103123770 B CN103123770 B CN 103123770B
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Abstract
The invention discloses a power management circuit. The power management circuit is used in a liquid crystal display device and comprises one or more power generating circuits, a gate electrode pulse modulation circuit and a discharging controller, wherein the one or more power generating circuits respectively receive one or more input voltage and produce one or more output voltage, the gate electrode pulse modulation circuit is coupled between a gate electrode high-level voltage source and a discharging control end and used for generating a gate electrode control signal, the discharging controller is coupled to the discharging control end and used for providing a discharging route for the gate electrode pulse modulation circuit. One of the gate electrode pulse modulation circuit and the discharging controller is further coupled to a power supply to enable the gate electrode pulse modulation circuit to discharge electricity to the power supply during gate electrode discharging, and the power supply is one of the one or more input voltage and the one or more output voltage.
Description
Technical field
The present invention relates to a kind of electric power management circuit and its gate electrode pulse modulation circuit, more particularly to one kind can lift power supply
The electric power management circuit and its gate electrode pulse modulation circuit of conversion efficiency.
Background technology
In general, in liquid crystal display (liquid crystal display, LCD) device, arbitrary sub- picture element includes one
Thin film transistor (TFT) (Thin film transistor, TFT) and a liquid crystal capacitance, and due to the gate and source electrode of thin film transistor (TFT)
Between there are a parasitic capacitance, therefore the electric charge stored by liquid crystal capacitance can receive parasitic capacitance coupling influence during discharging, and
Affect the be intended to image data for showing.
For example, Fig. 1 is refer to, Fig. 1 is the schematic diagram of a sub- picture element 10 in a known liquid crystal indicator.Such as Fig. 1
Shown, sub- picture element 10 includes a thin film transistor (TFT) 100 and a liquid crystal capacitance 102, between the gate and source electrode of thin film transistor (TFT) 100
There are parasitic capacitance CGD.The time schedule controller of liquid crystal indicator carries out sequencing contro so that the one of scan line GL
Gate drive voltage in a gate high levle voltage VGH can conducting membrane transistor 100, therefore a data wire SL can be by liquid crystal
Electric capacity 102 charges to the be intended to level for showing with image data displaying.However, scan line GL gate drive voltage switching extremely
One gate low level voltage VGL to close during thin film transistor (TFT) 100, due to thin film transistor (TFT) 100 gate and source electrode between exist
There is parasitic capacitance CGD, therefore the voltage switching of the gate of thin film transistor (TFT) 100 is (i.e. by gate high levle voltage VGH to gate
Low level voltage VGL), parasitic capacitance C can be passed throughGDLiquid crystal capacitance 102 is affected to be stored up coupled to the source electrode of thin film transistor (TFT) 100
The current potential deposited, and then affect the be intended to image data for showing.
In the case, Fig. 2A is refer to, Fig. 2A reduces parasitic capacitance C as shown in Figure 1 for knownGDThe signal of coupling effect
Figure.As shown in Figure 2 A, compared to scan line GL is switched to gate low level voltage VGL by gate high levle voltage VGH directly
(as shown in left side), in order to reduce parasitic capacitance CGDCoupling effect, conventional scan line GL are switched by gate high levle voltage VGH
To gate low level voltage VGL to close thin film transistor (TFT) 100 during, first can be put with one by gate high levle voltage VGH
Electric slope is down to gate low level voltage VGL again after being down to 0V (as shown in right-hand part).Consequently, it is possible to parasitic capacitance CGDTwo ends wink
Span bucklingization is reduced, therefore can effectively reduce the coupling effect of the gate of thin film transistor (TFT) 100 to the source electrode of thin film transistor (TFT) 100
Should.
It is carefully sayed, Fig. 2 B are refer to, Fig. 2 B are the gate electrode pulse modulation (Gate for realizing Fig. 2A right-hand part functions
Pulse Modulation) circuit 20 block schematic diagram.As shown in Figure 2 B, gate electrode pulse modulation circuit 20 includes foot position
200～206, foot position 200 is used for receiving a switch controlling signal VFLK (can be provided by time schedule controller), and foot position 202 is used for connecing
Gate high levle voltage VGH is received, foot position 204 couples a discharge resistance RE to ground (0V), and foot position 206 is used for exporting gate control
Signal VGHM gives the gate of the thin film transistor (TFT) of all sub- picture elements in liquid crystal indicator, wherein, an equivalent sum total parasitic capacitance
C_VGHM can be equivalent to the sum total of parasitic capacitance between the gate and source electrode of the thin film transistor (TFT) of all sub- picture elements, therefore gate control
Signal VGHM can simultaneously to the parasitic capacitance C_VGHM discharge and recharge of equivalent sum total.
With regard to the concrete operations of gate electrode pulse modulation circuit 20, during a gate charges, switch controlling signal VFLK is
High levle, causes gate control signal VGHM to be gate high levle voltage VGH, while equivalent sum total parasitic capacitance C_VGHM is filled
Electricity is to gate high levle voltage VGH.In addition, during a gate discharges, switch controlling signal VFLK is low level, causes gate
Control signal VGHM is equal to the voltage of equivalent sum total parasitic capacitance C_VGHM at the beginning, and this voltage can be via discharge resistance RE
It is discharged to 0V.
It is well known, however, that way gate electrode pulse modulation circuit 20 sums up parasitic capacitance C_VGHM by equivalent during gate electric discharge
Stored charge discharge is to ground, it is impossible to effectively utilizes.In view of this, known technology has improved necessary in fact, to increase power supply
Efficiency.
The content of the invention
Therefore, the one of the purpose of the present invention is to provide one kind will to be stored up in parasitic capacitance during a gate discharges
The spurious charge deposited is transferred to arbitrary input voltage of power management chip or output voltage is recycled, to lift turning for power supply
Change the electric power management circuit and its gate electrode pulse modulation circuit of efficiency.
In one embodiment, a kind of electric power management circuit is disclosed, in a liquid crystal indicator.The electric power management circuit
One or more power generation circuit is included, one or more input voltage is received respectively, and is produced one or more output voltage；
One gate electrode pulse modulation circuit, is coupled between a gate high levle voltage source and a discharge control terminal, to produce a gate
Control signal；And a discharge controller, the discharge control terminal is coupled to, is put to provide the gate electrode pulse modulation circuit one
Power path, wherein the gate electrode pulse modulation circuit and the discharge controller one of are worked as and to be more coupled to a supply power supply, so that
The gate electrode pulse modulation circuit is discharged to the supply power supply during gate electric discharge, and the supply power supply be this one or more
Input voltage and one or more output voltage one of are worked as.
In another embodiment, a kind of electric power management circuit is disclosed, in a liquid crystal indicator.The power management electricity
Road includes one or more power generation circuit, a gate electrode pulse modulation circuit and a discharge controller.One or more electricity
Source generating circuit receives one or more input voltage respectively, and produces one or more output voltage；The gate electrode pulse modulation electricity
Road includes a charge switch, between one gate high levle voltage source of coupling and a gate control end；And a discharge switch, coupling
It is connected between the gate control end and a discharge control terminal.The discharge controller, is coupled to the discharge control terminal with a supply electricity
Between source, to the discharge path for providing the gate electrode pulse modulation circuit, the wherein supply power supply is one or more input
Voltage and one or more output voltage one of are worked as.
In more another embodiment, a kind of gate electrode pulse modulation circuit is disclosed, for producing the lock of a liquid crystal indicator
Pole control signal.The gate electrode pulse modulation circuit includes a charge switch, is coupled to a gate high levle voltage source and a lock
Between the control signal output of pole；One current mirror, is coupled between the gate control signal output and the discharge control terminal；
And a discharge switch, it is coupled between current mirror and a supply power supply.
In more another embodiment, a kind of electric power management circuit is disclosed, the electric power management circuit includes above-mentioned gate
PM circuit power manages circuit；And one or more power generation circuit, one or more input voltage is received respectively, with
And produce one or more output voltage.
Here coordinates following schemes, the detailed description of embodiment and claims, and other mesh of the present invention are addressed by
Be specified in advantage after.
Description of the drawings
Fig. 1 is the schematic diagram of a sub- picture element in a known liquid crystal indicator.
Fig. 2A is the known schematic diagram for reducing parasitic capacitance coupling effect as shown in Figure 1.
Fig. 2 B are the block schematic diagram for realizing a gate electrode pulse modulation circuit of Fig. 2A right-hand part functions.
The schematic diagram of an electric power management circuits of the Fig. 3 to be used for a liquid crystal indicator in the embodiment of the present invention.
Fig. 4 A are the block schematic diagram according to a gate electrode pulse modulation circuit in embodiment Fig. 3.
Fig. 4 B are the circuit diagram according to embodiment gate electrode pulse modulation circuit as shown in Figure 4 A.
Fig. 4 C are the operation chart according to embodiment gate electrode pulse modulation circuit as shown in Figure 4 A.
The schematic diagram of an electric power management circuits of Fig. 5 A to be used for a liquid crystal indicator in another embodiment of the present invention.
Fig. 5 B are the block schematic diagram according to an embodiment gate electrode pulse modulation circuit as shown in Figure 5A.
Fig. 5 C are the circuit diagram according to embodiment gate electrode pulse modulation circuit as shown in Figure 5A.
Fig. 5 D are the operation chart according to embodiment gate electrode pulse modulation circuit as shown in Figure 5A.
Schematic diagrams of the Fig. 6 for one electric charge circulation process of the embodiment of the present invention.
Wherein, description of reference numerals is as follows：
10 sub- picture elements
100 thin film transistor (TFT)s
102 liquid crystal capacitances
20th, 308,508 gate electrode pulse modulation circuit
200～206,400～406,500,502 foot positions
208th, 408 charge switch
210th, 410 discharge switch
30th, 50 electric power management circuit
300 DC-DC converters
302 low dropout voltage regulators
304 voltage buffers
306 other power generation circuits
310 discharge controllers
506 current mirrors
60 electric charge circulation process
600～608 steps
CGDParasitic capacitance
GL scan lines
SL data lines
VGH, VGH ＇, VIN5 gate high levle voltage
VGL gate low level voltages
VFLK, VFLK ＇ switch controlling signals
RE, RE ＇ discharge resistances
VGHM, VGHM ＇ gate control signals
The equivalent sum total parasitic capacitances of C_VGHM, C_VGHM ＇
VFLK_INV ＇ inversion signals
VIN1～VIN4 input voltages
VOUT1～VOUT4 output voltages
VSUP supplies voltage
C_SUP electric capacity
M1, M2 transistor
Specific embodiment
Refer to Fig. 3, Fig. 3 is showing for the electric power management circuit 30 in the embodiment of the present invention for a liquid crystal indicator
It is intended to.As shown in figure 3, electric power management circuit 30 can be embodied as a chip, and including a gate electrode pulse modulation (Gate Pulse
Modulation) circuit 308, which receives and one gate high levle voltage source VIN5 of modulation.One discharge controller 310 (for example with
One discharge resistance RE ' is implemented) can be coupled between a discharge control terminal and a supply power supply (there is supply voltage VSUP), it is used for
There is provided gate electrode pulse modulation circuit 308 1 discharge path.In addition, electric power management circuit 30 further includes one or more power supply produces electricity
Road, be for example in the middle of lower column circuits one of at least：One DC-DC converter (DC/DC converter), 300, one low pressure
Drop manostat (Low drop out regulator, LDO regulator) 302, one voltage buffer 304, and one other
Power generation circuit 306, its difference receives input voltage VIN1～VIN4, and it is defeated to provide according to the input voltage for being received
Go out voltage VOUT1～VOUT4.
The one of this embodiment is characterized mainly in that the supply power supply of gate electrode pulse modulation circuit 308 elects input voltage VIN 1 as
One in the middle of～VIN4 and output voltage VO UT1～VOUT4.Under this arrangement, gate electrode pulse modulation circuit 308 can be in a gate
During electric discharge, via discharge resistance RE ＇ by a gate control signal VGHM ＇ (electricity of i.e. one equivalent sum total parasitic capacitance C_VGHM ＇
Pressure) it is discharged to the supply power supply.It should be noted that this embodiment illustrates discharge controller 310 is arranged on electric power management circuit
30 outside, but other embodiments may be provided inside.
Compared to gate electrode pulse modulation circuit 20 in Fig. 2 during gate electric discharge, be discharged to 0V and cannot effectively utilizes
Electric charge stored by equivalent sum total parasitic capacitance C_VGHM, the discharge resistance RE ＇ of the present embodiment are coupled to supply power supply, and supply
Power supply directly takes one in the middle of 1～VIN4 of input voltage VIN and output voltage VO UT1～VOUT4, thus the present embodiment except
Can reduce all sub- picture elements in liquid crystal indicator thin film transistor (TFT) gate the coupling effect between source electrode outside, can also by etc.
Spurious charge stored by effect sum total parasitic capacitance C_VGHM ＇ is recycled, so as to needn't additionally arrange other voltage sources
The conversion efficiency of power supply can be just lifted in the case of to provide supply power supply.
It is carefully sayed, Fig. 4 A are refer to, Fig. 4 A are the square of gate electrode pulse modulation circuit 308 in Fig. 3 according to an embodiment
Schematic diagram.As shown in Figure 4 A, gate electrode pulse modulation circuit 308 includes foot position 400～406, and foot position 400 is used for receiving a switch
Control signal VFLK ＇ (can be provided by time schedule controller), and foot position 402 is used for receiving a gate high levle voltage VGH ＇, foot position 404
Coupling discharge resistance RE ＇ to the supply voltage VSUP for supplying power supply, liquid is given for exporting gate control signal VGHM ＇ in foot position 406
The gate of the thin film transistor (TFT) of (being for example whole) multiple in crystal device picture element.Equivalent sum total parasitic capacitance C_VGHM ＇
The sum total of parasitic capacitance between the gate and source electrode of the thin film transistor (TFT) of multiple (for example all) sub- picture elements, therefore gate can be equivalent to
Control signal VGHM ＇ can simultaneously to the parasitic capacitance C_VGHM ＇ discharge and recharges of equivalent sum total.In addition, gate high levle voltage VGH ＇ can
The gate high levle voltage source VIN5 being considered as in Fig. 3.Under this arrangement, gate control signal VGHM ＇ is to discharge into power management
One of input of circuit 30 or output voltage.In other words, gate control signal VGHM ' in storage stage, (on-off control is believed
Number VFLK='HI') stored by electric charge, can reclaim to one of input or the output voltage of electric power management circuit 30, therefore
The conversion efficiency of electric power management circuit 30 can be lifted.
Specifically, Fig. 4 B and Fig. 4 C are refer to, Fig. 4 B are according to embodiment gate electrode pulse modulation as shown in Figure 4 A
The circuit diagram of circuit 308, Fig. 4 C are to show according to the operation of embodiment gate electrode pulse modulation circuit 308 as shown in Figure 4 B
It is intended to.As shown in Figure 4 B, a charge switch 408 and a discharge switch 410 are included in gate electrode pulse modulation circuit 308.Separately
Outward, discharge switch 410 can be coupled to supply power supply by discharge controller 310 (being for example discharge resistance RE ').Charge switch
The 408 equivalent sum totals for being coupled to a gate high levle voltage source (provide gate high levle voltage VGH ＇) and liquid crystal indicator are posted
Life electric capacity appearance C_VGHM ＇ (i.e. gate control signal output VGHM ') between.It is parasitic that discharge switch 410 is coupled to equivalent sum total
Between electric capacity C_VGHM ＇ and the discharge control terminal.Discharge controller 310 is coupled between the discharge control terminal and supply power supply,
It is one in the middle of 1～VIN4 of input voltage VIN and output voltage VO UT1～VOUT4 wherein to supply power supply.In addition, charge switch
408 with discharge switch 410 respectively by an inversion signal VFLK-_ of switch controlling signal VFLK ＇ and switch controlling signal VFLK ＇
INV ＇ are controlled.
In the case, as shown in Figure 4 C, during gate charging, VFLK ＇ are anti-for high levle for switch controlling signal
Phase signals VFLK---_INV ＇ is low level, and charge switch 408 is turned on and discharge switch 410 is closed, therefore gate control signal
VGHM ＇ are gate high levle voltage VGH ＇, while equivalent sum total parasitic capacitance C_VGHM ＇ is charged to gate high levle voltage
VGH ＇.Next, during a gate discharges, switch controlling signal VFLK ＇ switch to low level and inversion signal VFLK---_
INV ＇ switch to high levle, and charge switch 408 is closed and discharge switch 410 is turned on, therefore gate control signal VGHM ＇ at the beginning can
The voltage previously stored equal to equivalent sum total parasitic capacitance C_VGHM ＇, that is, gate high levle voltage VGH ＇, it is then equivalent total
Close parasitic capacitance C_VGHM ＇ and supply voltage VSUP can be discharged to by gate high levle voltage VGH ＇ via discharge controller 310.Change
Yan Zhi, this stage are the electric capacity that the spurious charge stored by equivalent sum total parasitic capacitance C_VGHM ＇ is transferred to supply power supply
C_SUP is stored.
Wherein, gate electric discharge during gate control signal VGHM ＇ (voltage of equivalent sum total parasitic capacitance C_VGHM ＇) by
Gate high levle voltage VGH ＇ are discharged to an electric discharge slope of supply voltage VSUP can be by equivalent sum total parasitic capacitance C_VGHM ＇'s
The resistance value of capacitance and discharge resistance RE ＇ is determined.Therefore, by the resistance value of adjustment discharge resistance RE ＇, can adjust and put
Electric slope and reach be intended to display effect.Consequently, it is possible to as gate control signal VGHM ＇ is entered by adjustable electric discharge slope
Row switch discharges slope, therefore cross-pressure change can be less, and then effectively reduce the gate pair of the thin film transistor (TFT) of all sub- picture elements
Coupling effect between source electrode.Further, since supply voltage is 1～VIN4 of input voltage VIN and output voltage VO UT1～VOUT4
Central one, therefore the spurious charge stored by equivalent sum total parasitic capacitance C_VGHM ＇ can be recycled, to lift power supply
Conversion efficiency.
It should be noted that the main spirits of the present embodiment are by gate control signal VGHM ＇ during gate discharges
(voltage of i.e. equivalent sum total parasitic capacitance C_VGHM ＇) is discharged to supply power supply, and this supply power supply is electric power management circuit 30
1～VIN4 of input voltage VIN and output voltage VO UT1～VOUT4 in the middle of one, therefore can by it is equivalent sum total parasitic capacitance C_
Spurious charge stored by VGHM ＇ is recycled, to lift the conversion efficiency of power supply.Those of ordinary skill in the art work as can be according to this
Modification changes, and not limited to this.For example, above-described embodiment illustrates supply power supply by being connected on gate arteries and veins outside foot position 404
Rush the chip exterior of modulation circuit 308, but actually supply the inside that power supply also can directly be connected on electric power management circuit 30 and enter
Row is utilized.Additionally, supply power supply is also not necessarily limited to the 1～VIN4 of input voltage VIN and output voltage VO UT1 of electric power management circuit 30
One in the middle of～VOUT4, can be other input voltages of electric power management circuit 30 or output voltage, and an alternatively system application is electric
One in the middle of an at least input voltage and an at least output voltage on road, so that system application circuit is recycled.Furthermore, electric discharge
The implementation of controller 310 is also not necessarily limited to above-mentioned to be coupled between equivalent sum total parasitic capacitance C_VGHM ＇ and supply power supply
Discharge resistance RE ＇ implement, and can with embodied in other, as long as can gate discharge during control grid control signal
The electric discharge slope of VGHM ＇ (voltage of i.e. equivalent sum total parasitic capacitance C_VGHM ＇).
For example, Fig. 5 A to Fig. 5 D be refer to, Fig. 5 A are to be used for a liquid crystal indicator in another embodiment of the present invention
Another electric power management circuit 50 schematic diagram.Fig. 5 B are that the square of a gate electrode pulse modulation circuit 508 as shown in Figure 5A shows
It is intended to, Fig. 5 C are the circuit diagram of gate electrode pulse modulation circuit 508 as shown in Figure 5A, and Fig. 5 D are gate as shown in Figure 5A
The operation chart of PM circuit 508.Electric power management circuit 50 is former with the framework of gate pulse modulation circuit 508 and running
Reason is similar to 308 part of gate pulse modulation circuit to electric power management circuit 30, therefore purposes identical component and signal are continued to use
Same-sign, in the hope of succinct.As shown in Fig. 5 A and Fig. 5 B, gate electrode pulse modulation circuit 508 and gate electrode pulse modulation circuit 308
Main difference is that, discharge resistance RE ＇ are coupled to supply power supply by foot position 404 compared to gate electrode pulse modulation circuit 308
Supply voltage VSUP (is coupled to supply power supply by discharge controller 310), and gate electrode pulse modulation circuit 508 is with a foot position 502
A discharge resistance RE ' is coupled to ground (0V), then the supply voltage VSUP of the newly-increased coupling of a foot position 500 supply power supply.In other words, i.e.,
It is additionally coupled in itself supply power supply by gate electrode pulse modulation circuit 508.It should be noted that this embodiment illustrates control of discharge
Device 310 or discharge resistance RE ' are arranged on the outside of electric power management circuit 50, but other embodiments may be provided inside.
In the case, as shown in Figure 5 C, which is the gate electrode pulse modulation circuit as shown in Figure 5 B according to an embodiment
508 circuit implementation.The framework of gate electrode pulse modulation circuit 508 is mainly similar with gate electrode pulse modulation circuit 308, but also
Equivalent sum total parasitic capacitance C_VGHM ＇ (i.e. gate control signal output) and the electric discharge are coupled to including a current mirror 506
Between control end.In other words, gate electrode pulse modulation circuit 508 includes a charge switch 408, and which is coupled to gate high levle electricity
Potential source VGH ' and a gate control signal output (output gate control signal VGHM ') between, and a current mirror 506, coupling
It is connected between gate control signal output and a discharge control terminal (for being coupled to the end points of discharge controller 310), with
And a discharge switch 410, it is coupled between current mirror 506 and supply power supply.In addition, gate electrode pulse modulation circuit 508 can pass through
Equally it is coupled to the discharge controller 310 (for example implementing with a discharge resistance RE ') of the discharge control terminal and is coupled to ground electricity
Position, while being coupled to supply power supply by discharge switch 410.
In one embodiment, current mirror 506 becomes another road from the discharge current of parasitic capacitance C_VGHM ＇ for mirror
Electric current, flows to ground by discharge controller 310 again by discharge control terminal.For example, current mirror 506 may include crystalline substance
Body pipe M1, M2, control end and the control end of transistor M2 of transistor M1 are coupled against each other.In addition, transistor M1 be coupled to it is equivalent
Between sum total parasitic capacitance C_VGHM ＇ and discharge switch 410, and transistor M2 be coupled to a voltage and the discharge control terminal it
Between.Therefore, transistor M1 is coupled to supply voltage by discharge switch 410, and transistor M2 by discharge resistance RE ' coupling
It is connected to ground.Using a resistance value size of adjustment discharge resistance RE ', the size of current of transistor M2 is can adjust, and transistor M1
Size of current also can with change, therefore also can reach gate discharge during control grid control signal VGHM ＇ it is (i.e. equivalent
Sum total parasitic capacitance C_VGHM ＇ voltage) electric discharge slope effect.Gate electrode pulse modulation circuit 508 other operation, can be by lock
The operation of pole PM circuit 308 is analogized and is obtained, and here is not also repeated.
Gate electrode pulse modulation circuit 308 can be summarized as an electric charge circulation process with the operation of gate pulse modulation circuit 508
60, as shown in fig. 6, which comprises the following steps：
Step 600：Start.
Step 602：According to switch controlling signal VFLK ＇, by the equivalent sum total of liquid crystal indicator during gate charges
Parasitic capacitance C_VGHM ＇ charges to gate high levle voltage VGH ＇.
Step 604：According to an inversion signal VFLK---_INV ＇ of switch controlling signal VFLK ＇, during gate discharges
Equivalent sum total parasitic capacitance C_VGHM ＇ is discharged to into the supply voltage VSUP of supply power supply.
Step 606：Equivalent sum total parasitic capacitance C_VGHM of control is during gate electric discharge by gate high levle voltage VGH ＇
It is discharged to the electric discharge slope of supply voltage；Wherein, supply at least input voltage and at least that power supply is electric power management circuit 30
One in the middle of one output voltage.
Step 608：Terminate.
The details of wherein each step can be by corresponding with gate pulse modulation circuit 508 group of gate electrode pulse modulation circuit 308
The operation of part is analogized and is obtained, and here is not also repeated.
In known technology, gate electrode pulse modulation circuit 20 is during gate electric discharge by equivalent sum total parasitic capacitance C_VGHM
Stored charge discharge is to ground, it is impossible to effectively utilizes.In comparison, above-described embodiment during gate electric discharge by gate control
Signal VGHM ＇ (voltage of i.e. equivalent sum total parasitic capacitance C_VGHM ＇) are discharged to supply power supply, and supply power supply for power management
One in the middle of the 1～VIN4 of input voltage VIN of circuit 30 and output voltage VO UT1～VOUT4, therefore can equivalent sum total parasitism
Spurious charge stored by electric capacity C_VGHM ＇ is recycled, to lift the conversion efficiency of power supply.
The foregoing is only the preferred embodiments of the present invention, all impartial changes done according to the claims in the present invention with repair
Decorations, should all belong to the covering scope of the present invention.
Claims (12)
1. a kind of electric power management circuit, for a liquid crystal indicator in, it is characterised in that include：
One or more power generation circuit, receives one or more input voltage respectively, and produces one or more output voltage；
One gate electrode pulse modulation circuit, is coupled between a gate high levle voltage source and a discharge control terminal, to produce one
Gate control signal；And
One discharge controller, is coupled between the discharge control terminal and a ground potential, to provide the gate electrode pulse modulation circuit
A discharge path, wherein
The gate electrode pulse modulation circuit is coupled to a supply power supply, so that the gate electrode pulse modulation circuit is during gate electric discharge
The supply power supply is discharged to, and
The supply power supply be one or more input voltage Yu Productivity lifes that this one or more power generation circuit is received this one to
Multiple output voltages one of are worked as；
Wherein, the gate electrode pulse modulation circuit is included：
One charge switch, is coupled between the gate high levle voltage source and a gate control signal output；
One current mirror, is coupled between the gate control signal output and the discharge control terminal, for mirror from the lock
One electric current of pole control signal output becomes another road electric current to be circulated through the discharge controller；And
One discharge switch, is coupled between the current mirror and the supply power supply.
2. electric power management circuit as claimed in claim 1, it is characterised in that one or more power generation circuit is included always
Stream in the middle of direct current transducer, a low dropout voltage regulator and a voltage buffer one of at least.
3. electric power management circuit as claimed in claim 1, it is characterised in that the discharge controller includes a discharge resistance,
Which is coupled between the discharge control terminal and a ground potential.
4. electric power management circuit as claimed in claim 1, it is characterised in that during a gate charges, in response to a switch
First level of control signal and the charge switch is turned on and the discharge switch is closed, gate control signal output is filled
Electricity, and during the gate discharges, in response to the switch controlling signal the second level and the charge switch is closed and should
Discharge switch is turned on, by the tension discharge of the gate control signal output to the supply power supply.
5. a kind of electric power management circuit, for a liquid crystal indicator in, it is characterised in that include：
One or more power generation circuit, receives one or more input voltage respectively, and produces one or more output voltage；
One gate electrode pulse modulation circuit, is coupled between a gate high levle voltage source and a discharge control terminal, to produce one
Gate control signal, the gate electrode pulse modulation circuit include：
One charge switch, is coupled between the gate high levle voltage source and a gate control signal output；And
One discharge switch, is coupled between the gate control signal output and the discharge control terminal；
And
One discharge controller, is coupled between the discharge control terminal and a supply power supply, to provide the gate electrode pulse modulation electricity
One discharge path on road, makes the gate electrode pulse modulation circuit be discharged to the supply power supply during gate electric discharge, wherein
The supply power supply be one or more input voltage Yu Productivity lifes that this one or more power generation circuit is received this one to
Multiple output voltages one of are worked as；
Wherein, one or more power generation circuit is separately used for storing the electric charge that the discharge path is provided.
6. electric power management circuit as claimed in claim 5, it is characterised in that one or more power generation circuit is included always
Stream in the middle of direct current transducer, a low dropout voltage regulator and a voltage buffer one of at least.
7. electric power management circuit as claimed in claim 5, it is characterised in that the discharge controller includes a discharge resistance,
Which is coupled between the discharge control terminal and the supply power supply.
8. electric power management circuit as claimed in claim 5, it is characterised in that during a gate charges, in response to a switch
First level of control signal and the charge switch is turned on and the discharge switch is closed, gate control signal output is filled
Electricity, and during the gate discharges, in response to the switch controlling signal the second level and the charge switch is closed and should
Discharge switch is turned on, by the tension discharge of the gate control signal output to the supply power supply.
9. a kind of gate electrode pulse modulation circuit, it is characterised in that produce a liquid crystal to receive one or more input voltage
The gate control signal of showing device, the gate electrode pulse modulation circuit are included：
One charge switch, is coupled between a gate high levle voltage source and a gate control signal output；
One current mirror, is coupled between the gate control signal output and a discharge control terminal, for mirror from the lock
One electric current of pole control signal output becomes another road electric current to be circulated through a discharge controller；And
One discharge switch, is coupled between current mirror and a supply power supply；
Wherein, the gate electrode pulse modulation circuit is also coupled to one or more power generation circuit, one or more power generation circuit
Receive one or more input voltage respectively, and produce one or more output voltage, and the supply power supply be this one or more
Input voltage and one or more output voltage one of are worked as.
10. a kind of electric power management circuit, it is characterised in that include：
One or more power generation circuit, receives one or more input voltage respectively, and produces one or more output voltage；With
And
One gate electrode pulse modulation circuit, includes：
One charge switch, is coupled between a gate high levle voltage source and a gate control signal output；
One current mirror, is coupled between the gate control signal output and a discharge control terminal, for mirror from the lock
One electric current of pole control signal output becomes another road electric current to be circulated through a discharge controller；And
One discharge switch, is coupled between current mirror and a supply power supply；
Wherein, the supply power supply is one or more input voltage and one or more output voltage one of is worked as.
11. electric power management circuits as claimed in claim 10, it is characterised in that one or more power generation circuit includes one
In the middle of DC-DC converter, a low dropout voltage regulator and a voltage buffer one of at least.
12. electric power management circuits as claimed in claim 10, it is characterised in that the current mirror includes：
The first transistor, which is coupled between the gate control signal output and the discharge switch；And
Transistor seconds, there is a control end to be coupled to a control end of the first transistor for which, and its be coupled to a power supply with
Between the discharge control terminal.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201110367500.5A CN103123770B (en) | 2011-11-18 | 2011-11-18 | Power management circuit and gate electrode pulse modulation circuit thereof |
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| Application Number | Priority Date | Filing Date | Title |
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| CN201110367500.5A CN103123770B (en) | 2011-11-18 | 2011-11-18 | Power management circuit and gate electrode pulse modulation circuit thereof |
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| CN103123770B true CN103123770B (en) | 2017-04-12 |
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| JP3326829B2 (en) * | 1992-10-28 | 2002-09-24 | ソニー株式会社 | Drive signal processing circuit for liquid crystal display |
| JP5027464B2 (en) * | 2006-09-08 | 2012-09-19 | ローム株式会社 | Power supply device, liquid crystal drive device, display device |
| KR101480313B1 (en) * | 2006-12-29 | 2015-01-08 | 엘지디스플레이 주식회사 | Liquid crystal display |
| TWI415098B (en) * | 2009-09-10 | 2013-11-11 | Raydium Semiconductor Corp | Gate driver and operating method thereof |
| KR101324428B1 (en) * | 2009-12-24 | 2013-10-31 | 엘지디스플레이 주식회사 | Display device |
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| CN103123770A (en) | 2013-05-29 |
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