CN103123770A - Power management circuit and gate electrode pulse modulation circuit thereof - Google Patents
Power management circuit and gate electrode pulse modulation circuit thereof Download PDFInfo
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- CN103123770A CN103123770A CN2011103675005A CN201110367500A CN103123770A CN 103123770 A CN103123770 A CN 103123770A CN 2011103675005 A CN2011103675005 A CN 2011103675005A CN 201110367500 A CN201110367500 A CN 201110367500A CN 103123770 A CN103123770 A CN 103123770A
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Abstract
The invention discloses a power management circuit. The power management circuit is used in a liquid crystal display device and comprises one or more power generating circuits, a gate electrode pulse modulation circuit and a discharging controller, wherein the one or more power generating circuits respectively receive one or more input voltage and produce one or more output voltage, the gate electrode pulse modulation circuit is coupled between a gate electrode high-level voltage source and a discharging control end and used for generating a gate electrode control signal, the discharging controller is coupled to the discharging control end and used for providing a discharging route for the gate electrode pulse modulation circuit. One of the gate electrode pulse modulation circuit and the discharging controller is further coupled to a power supply to enable the gate electrode pulse modulation circuit to discharge electricity to the power supply during gate electrode discharging, and the power supply is one of the one or more input voltage and the one or more output voltage.
Description
Technical field
The present invention relates to a kind of electric power management circuit and gate PM circuit thereof, relate in particular to a kind of electric power management circuit and gate PM circuit thereof that promotes power supply conversion efficiency.
Background technology
In general, liquid crystal display (liquid crystal display, LCD) in the device, arbitrary sub-picture element includes a thin film transistor (TFT) (Thin film transistor, TFT) and a liquid crystal capacitance, and owing to having a stray capacitance between the gate of thin film transistor (TFT) and source electrode, therefore the stored electric charge of liquid crystal capacitance can be subjected to the stray capacitance coupling influence at interdischarge interval, and affects the image data that institute's wish shows.
For instance, please refer to Fig. 1, Fig. 1 is the schematic diagram of a sub-picture element 10 in a known liquid crystal indicator.As shown in Figure 1, sub-picture element 10 includes a thin film transistor (TFT) 1 00 and a liquid crystal capacitance 102, has a stray capacitance C between the gate of thin film transistor (TFT) 100 and source electrode
GDThe time schedule controller of liquid crystal indicator carries out sequential control, but make gate drive voltage conducting membrane transistor 100 when a gate high levle voltage VGH of one scan line GL, therefore a data line SL can charge to liquid crystal capacitance 102 level of institute's wish demonstration with image data displaying.Yet, switch to a gate low level voltage VGL when closing thin film transistor (TFT) 100 at the gate drive voltage of sweep trace GL, owing to having a stray capacitance C between the gate of thin film transistor (TFT) 100 and source electrode
GD, so the voltage of the gate of thin film transistor (TFT) 100 switches (namely by gate high levle voltage VGH to gate low level voltage VGL), can pass through stray capacitance C
GDBe coupled to the source electrode of thin film transistor (TFT) 100 and affect the stored current potential of liquid crystal capacitance 102, and then affect the image data that institute's wish shows.
In the case, please refer to Fig. 2 A, Fig. 2 A is known reduction stray capacitance C as shown in Figure 1
GDThe schematic diagram of coupling effect.As shown in Fig. 2 A, compared to directly sweep trace GL being switched to gate low level voltage VGL (as shown in the left side) by gate high levle voltage VGH, in order to reduce stray capacitance C
GDCoupling effect, known sweep trace GL switches to gate low level voltage VGL with in the process of closing thin film transistor (TFT) 100 by gate high levle voltage VGH, can first be discharged with one by gate high levle voltage VGH and be down to gate low level voltage VGL (as shown in right-hand part) after slope is down to 0V again.Thus, stray capacitance C
GDTwo ends moment cross-pressure changes and reduces, and therefore can effectively reduce the gate of thin film transistor (TFT) 100 to the coupling effect of the source electrode of thin film transistor (TFT) 100.
Thin speech, please refer to Fig. 2 B, Fig. 2 B is the block schematic diagram of a gate PM (the Gate Pulse Modulation) circuit 20 of realizing Fig. 2 A right-hand part function.as shown in Fig. 2 B, gate PM circuit 20 includes pin position 200～206, pin position 200 is used for receiving a switch controlling signal VFLK (can be provided by time schedule controller), pin position 202 is used for receiving gate high levle voltage VGH, pin position 204 couples a discharge resistance RE to ground (0V), pin position 206 is used for exporting the gate that a gate control signal VGHM gives the thin film transistor (TFT) of all sub-picture elements in liquid crystal indicator, wherein, one equivalence sum total stray capacitance C_VGHM can equivalence be the sum total of stray capacitance between the gate of thin film transistor (TFT) of all sub-picture elements and source electrode, therefore gate control signal VGHM can discharge and recharge by while equity effect sum total stray capacitance C_VGHM.
Concrete operations about gate PM circuit 20, between a gate charge period, switch controlling signal VFLK is high levle, and causing gate control signal VGHM is gate high levle voltage VGH, simultaneously equivalence is summed up stray capacitance C_VGHM and charges to gate high levle voltage VGH.In addition, at a gate interdischarge interval, switch controlling signal VFLK is low level, cause gate control signal VGHM to equal at the beginning the voltage that stray capacitance C_VGHM is summed up in equivalence, and this voltage can be discharged to 0V via discharge resistance RE.
Yet well known practice gate PM circuit 20 is summed up the stored charge discharge of stray capacitance C_VGHM to ground at the gate interdischarge interval with equivalence, can't effectively utilize.In view of this, known technology has improved necessary in fact, to increase power-efficient.
Summary of the invention
Therefore, one of purpose of the present invention namely be to provide a kind of can a gate interdischarge interval with stray capacitance on the stored spurious charge arbitrary input voltage or the output voltage that are transferred to power management chip recycle, with electric power management circuit and the gate PM circuit thereof of the conversion efficiency that promotes power supply.
In one embodiment, disclose a kind of electric power management circuit, be used for a liquid crystal indicator.This electric power management circuit includes one or more power generation circuit, receives respectively one or more input voltage, and produces one or more output voltage; One gate PM circuit is coupled between a gate high levle voltage source and a control of discharge end, in order to produce a gate control signal; An and discharge controller, be coupled to this control of discharge end, in order to a discharge path of this gate PM circuit to be provided, wherein the one in the middle of this gate PM circuit and this discharge controller more is coupled to a supply power supply, so that this gate PM circuit is discharged to this supply power supply at a gate interdischarge interval, and this supply power supply is the one in the middle of this one or more input voltage and this one or more output voltage.
In another embodiment, disclose a kind of electric power management circuit, be used for a liquid crystal indicator.This electric power management circuit includes one or more power generation circuit, a gate PM circuit and a discharge controller.This one or more power generation circuit receives respectively one or more input voltage, and produces one or more output voltage; This gate PM circuit includes a charge switch, couples between a gate high levle voltage source and a gate control end; And a discharge switch, be coupled between this gate control end and a control of discharge end.This discharge controller is coupled between this control of discharge end and a supply power supply, and in order to a discharge path of this gate PM circuit to be provided, wherein this supply power supply is the one in the middle of this one or more input voltage and this one or more output voltage.
In another embodiment more, a kind of gate PM circuit is disclosed, for generation of the gate control signal of a liquid crystal indicator.This gate PM circuit includes a charge switch, is coupled between a gate high levle voltage source and a gate control signal output terminal; One current mirror is coupled between this gate control signal output terminal and this control of discharge end; And a discharge switch, be coupled between current mirror and a supply power supply.
In another embodiment more, a kind of electric power management circuit is disclosed, this electric power management circuit includes above-mentioned gate PM circuit power management circuit; And one or more power generation circuit, receive respectively one or more input voltage, and produce one or more output voltage.
Coordinate detailed description and claims of following diagram, embodiment at this, with on address other purpose of the present invention and advantage and be specified in after.
Description of drawings
Fig. 1 is the schematic diagram of a sub-picture element in a known liquid crystal indicator.
Fig. 2 A is the known reduction schematic diagram of a stray capacitance coupling effect as shown in Figure 1.
Fig. 2 B is the block schematic diagram of realizing a gate PM circuit of Fig. 2 A right-hand part function.
Fig. 3 is used for the schematic diagram of an electric power management circuit of a liquid crystal indicator in the embodiment of the present invention.
Fig. 4 A is the block schematic diagram according to a gate PM circuit in an embodiment Fig. 3.
Fig. 4 B is the circuit diagram according to the gate PM circuit of an embodiment as shown in Fig. 4 A.
Fig. 4 C is the operation chart according to the gate PM circuit of an embodiment as shown in Fig. 4 A.
Fig. 5 A is used for the schematic diagram of an electric power management circuit of a liquid crystal indicator in another embodiment of the present invention.
Fig. 5 B is the block schematic diagram according to the gate PM circuit of an embodiment as shown in Fig. 5 A.
Fig. 5 C is the circuit diagram according to the gate PM circuit of an embodiment as shown in Fig. 5 A.
Fig. 5 D is the operation chart according to the gate PM circuit of an embodiment as shown in Fig. 5 A.
Fig. 6 is the schematic diagram of the embodiment of the present invention one electric charge circulation process.
Wherein, description of reference numerals is as follows:
10 sub-picture elements
100 thin film transistor (TFT)s
102 liquid crystal capacitances
20,308,508 gate PM circuit
200～206,400～406,500,502 pin positions
208,408 charge switchs
210,410 discharge switches
30,50 electric power management circuits
300 DC-DC converters
302 low dropout voltage regulators
304 voltage buffers
306 other power generation circuits
310 discharge controllers
506 current mirrors
60 electric charge circulation process
600～608 steps
C
GDStray capacitance
The GL sweep trace
The SL data line
VGH, VGH ', VIN5 gate high levle voltage
VGL gate low level voltage
VFLK, VFLK ' switch controlling signal
RE, RE ' discharge resistance
VGHM, VGHM ' gate control signal
C_VGHM, C_VGHM ' equivalence sum total stray capacitance
VFLK_INV ' inversion signal
VIN1～VIN4 input voltage
VOUT1～VOUT4 output voltage
VSUP supplies voltage
C_SUP electric capacity
M1, M2 transistor
Embodiment
Please refer to Fig. 3, Fig. 3 is used for the schematic diagram of an electric power management circuit 30 of a liquid crystal indicator in the embodiment of the present invention.As shown in Figure 3, electric power management circuit 30 can be embodied as a chip, and comprises a gate PM (Gate Pulse Modulation) circuit 308, and it receives and modulation one gate high levle voltage source V IN5.One discharge controller 310 (for example implementing with a discharge resistance RE ') can be coupled between a control of discharge end and a supply power supply (having supply voltage VSUP), is used for providing gate PM circuit 308 1 discharge paths.In addition, electric power management circuit 30 more comprises one or more power generation circuit, for example at least one in the middle of lower column circuits: a DC-DC converter (DC/DC converter) 300, one low dropout voltage regulator (Low drop out regulator, LDO regulator) 302, one voltage buffer 304 and other power generation circuit 306, it receives respectively input voltage VIN 1～VIN4, and provides output voltage VO UT1～VOUT4 according to the input voltage that receives.
The principal character of this embodiment is that the supply power supply of gate PM circuit 308 elects one in the middle of input voltage VIN 1～VIN4 and output voltage VO UT1～VOUT4 as.Under this configuration, gate PM circuit 308 can at a gate interdischarge interval, be discharged to this supply power supply via discharge resistance RE ' with a gate control signal VGHM ' (i.e. the voltage of an equivalence sum total stray capacitance C_VGHM ').It should be noted that this embodiment illustrates the outside that discharge controller 310 is arranged on electric power management circuit 30, but other embodiment can be arranged on inside.
Thin speech, please refer to Fig. 4 A, Fig. 4 A is the block schematic diagram according to gate PM circuit 308 in Fig. 3 of an embodiment.As shown in Fig. 4 A, gate PM circuit 308 includes pin position 400～406, pin position 400 is used for receiving a switch controlling signal VFLK ' (can be provided by time schedule controller), pin position 402 is used for receiving a gate high levle voltage VGH ', pin position 404 couples discharge resistance RE ' to the supply voltage VSUP that supplies power supply, and pin position 406 is used for exporting the gate that gate control signal VGHM ' gives the thin film transistor (TFT) of a plurality of in liquid crystal indicator (for example for all) sub-picture element.Equivalence sum total stray capacitance C_VGHM ' can equivalence be the sum total of stray capacitance between the gate of thin film transistor (TFT) of a plurality of (for example whole) sub-picture element and source electrode, so gate control signal VGHM ' can sum up stray capacitance C_VGHM ' to equivalence simultaneously and discharge and recharge.In addition, gate high levle voltage VGH ' can be considered the gate high levle voltage source V IN5 in Fig. 3.Under this configuration, gate control signal VGHM ' is that one of them that discharge into electric power management circuit 30 inputs or outputs voltage.In other words, gate control signal VGHM ' is at the stored electric charge of storage stage (switch controlling signal VFLK=' HI '), one of them that can reclaim to electric power management circuit 30 inputs or outputs voltage, therefore can promote the conversion efficiency of electric power management circuit 30.
Particularly, please refer to Fig. 4 B and Fig. 4 C, Fig. 4 B is the circuit diagram according to the gate PM circuit 308 of an embodiment as shown in Fig. 4 A, and Fig. 4 C is the operation chart according to embodiment gate PM circuit 308 as shown in Figure 4 B.As shown in Figure 4 B, include a charge switch 408 and a discharge switch 410 in gate PM circuit 308.In addition, discharge switch 410 can be coupled to the supply power supply by discharge controller 310 (for example being discharge resistance RE ').Charge switch 408 is coupled to the equivalence sum total stray capacitance of a gate high levle voltage source (gate high levle voltage VGH ' is provided) and liquid crystal indicator to be held between C_VGHM ' (being gate control signal output terminal VGHM ').Discharge switch 410 is coupled between equivalence sum total stray capacitance C_VGHM ' and this control of discharge end.Discharge controller 310 is coupled between this control of discharge end and supply power supply, and wherein supplying power supply is one in the middle of input voltage VIN 1～VIN4 and output voltage VO UT1～VOUT4.In addition, charge switch 408 is controlled by the inversion signal VFLK-_INV ' of switch controlling signal VFLK ' and switch controlling signal VFLK ' respectively with discharge switch 410.
In the case, as shown in Fig. 4 C, between a gate charge period, switch controlling signal VFLK ' is low level for high levle inversion signal VFLK---_INV ', charge switch 408 conductings and discharge switch 410 is closed, therefore gate control signal VGHM ' is gate high levle voltage VGH ', simultaneously equivalence is summed up stray capacitance C_VGHM ' and charges to gate high levle voltage VGH '.Next, at a gate interdischarge interval, switch controlling signal VFLK ' transfers low level to and inversion signal VFLK---_INV ' transfers high levle to, charge switch 408 is closed and discharge switch 410 conductings, therefore gate control signal VGHM ' can equal the previous stored voltage of equivalence sum total stray capacitance C_VGHM ' at the beginning, that is gate high levle voltage VGH ', the stray capacitance of equivalence sum total then C_VGHM ' meeting is discharged to supply voltage VSUP via discharge controller 310 by gate high levle voltage VGH '.In other words, this stage is one capacitor C _ SUP that the stored spurious charge of stray capacitance C_VGHM ' is transferred to the supply power supply to be summed up in equivalence store.
Wherein, can sum up the capacitance of stray capacitance C_VGHM ' and the resistance value of discharge resistance RE ' is determined at gate interdischarge interval gate control signal VGHM ' (voltage of equivalence sum total stray capacitance C_VGHM ') by equivalence by the discharge slope that gate high levle voltage VGH ' is discharged to supply voltage VSUP.Therefore, by the resistance value of adjusting discharge resistance RE ', can adjust the discharge slope and reach want display effect.Thus, because gate control signal VGHM ' carries out the switch discharges slope by adjustable discharge slope, so cross-pressure change can be less, and then the gate of thin film transistor (TFT) that effectively reduces all sub-picture elements is to the coupling effect between source electrode.In addition, because supply voltage is one in the middle of input voltage VIN 1～VIN4 and output voltage VO UT1～VOUT4, therefore equivalence can be summed up the stored spurious charge of stray capacitance C_VGHM ' and recycle, to promote the conversion efficiency of power supply.
It should be noted that, the main spirits of the present embodiment is at the gate interdischarge interval, gate control signal VGHM ' (i.e. the voltage of equivalence sum total stray capacitance C_VGHM ') to be discharged to the supply power supply, and one in the middle of input voltage VIN 1～VIN4 that this supply power supply is electric power management circuit 30 and output voltage VO UT1～VOUT4, therefore equivalence can be summed up the stored spurious charge of stray capacitance C_VGHM ' and recycle, to promote the conversion efficiency of power supply.Those of ordinary skills work as and can modify according to this or change, and are not limited to this.For instance, above-described embodiment illustrates the supply power supply by the outer chip exterior that are connected on gate PM circuit 308 in pin position 404, utilizes yet in fact supply the inside that power supply also can directly be connected on electric power management circuit 30.In addition, the supply power supply also is not limited to input voltage VIN 1～VIN4 and the central one of output voltage VO UT1～VOUT4 of electric power management circuit 30, can be electric power management circuit 30 other input voltage or output voltages, and also can be at least one input voltage and the central one of at least one output voltage of a system applies circuit, use for the system applies circuit cycles.Moreover, the implementation of discharge controller 310 also is not limited to above-mentioned to be coupled to the discharge resistance RE ' enforcement between equivalence sum total stray capacitance C_VGHM ' and supply power supply, and can embodied in other, as long as can be at the discharge slope of gate interdischarge interval control grid control signal VGHM ' (i.e. the voltage of equivalence sum total stray capacitance C_VGHM ').
For instance, please refer to Fig. 5 A to Fig. 5 D, Fig. 5 A is used for the schematic diagram of another electric power management circuit 50 of a liquid crystal indicator in another embodiment of the present invention.Fig. 5 B is the block schematic diagram of the gate PM circuit 508 as shown in Fig. 5 A, and Fig. 5 C is the circuit diagram of the gate PM circuit 508 as shown in Fig. 5 A, and Fig. 5 D is the operation chart of the gate PM circuit 508 as shown in Fig. 5 A.Electric power management circuit 50 is similar to gate pulse modulation circuit 308 parts to electric power management circuit 30 to operation principles to the framework of gate pulse modulation circuit 508, so identical assembly and the signal of purposes continue to use same-sign, in the hope of succinctly.As shown in Fig. 5 A and Fig. 5 B, gate PM circuit 508 is with the main difference of gate PM circuit 308, couple discharge resistance RE ' to the supply voltage VSUP that supplies power supply (namely being coupled to the supply power supply by discharge controller 310) compared to gate PM circuit 308 by pin position 404, gate PM circuit 508 couples a discharge resistance RE ' to ground (0V) with a pin position 502, a more newly-increased pin position 500 couples the supply voltage VSUP of supply power supply.In other words, namely itself additionally be coupled to the supply power supply by gate PM circuit 508.It should be noted that this embodiment illustrates the outside that discharge controller 310 or discharge resistance RE ' are arranged on electric power management circuit 50, but other embodiment can be arranged on inside.
In the case, as shown in Fig. 5 C, it is the circuit embodiment according to the gate PM circuit 508 as shown in Fig. 5 B of an embodiment.The framework of gate PM circuit 508 is main and gate PM circuit 308 is similar, but comprises that also a current mirror 506 is coupled between equivalence sum total stray capacitance C_VGHM ' (being gate control signal output terminal) and this control of discharge end.In other words, gate PM circuit 508 comprises a charge switch 408, it is coupled between a gate high levle voltage source V GH ' and a gate control signal output terminal (output gate control signal VGHM '), an and current mirror 506, be coupled between gate control signal output terminal and a control of discharge end (being used for being coupled to the end points of discharge controller 310), and a discharge switch 410, be coupled between current mirror 506 and supply power supply.In addition, gate PM circuit 508 can be coupled to an earth potential by the discharge controller 310 (for example implementing with a discharge resistance RE ') that is coupled to equally this control of discharge end, is coupled to the supply power supply by discharge switch 410 simultaneously.
In one embodiment, current mirror 506 is used for mirror becomes another road circuit from the discharge current of stray capacitance C_VGHM ' and flows to ground by the control of discharge end.For example, current mirror 506 can include transistor M1, M2, and the control end of the control end of transistor M1 and transistor M2 couples mutually.In addition, transistor M1 is coupled between equivalence sum total stray capacitance C_VGHM ' and discharge switch 410, and transistor M2 is coupled between a voltage and this control of discharge end.Therefore, transistor M1 is coupled to supply voltage by discharge switch 410, and transistor M2 is coupled to ground by discharge resistance RE '.Utilize a resistance value size of adjusting discharge resistance RE ', the size of current of capable of regulating transistor M2, and the size of current of transistor M1 also can with change, therefore also can reach the effect at the discharge slope of gate interdischarge interval control grid control signal VGHM ' (i.e. the voltage of stray capacitance C_VGHM ' is summed up in equivalence).508 other operations of gate PM circuit can be analogized and be got by the operation of gate PM circuit 308, also do not give unnecessary details at this.
Step 600: beginning.
Step 602: according to switch controlling signal VFLK ', the equivalence sum total stray capacitance C_VGHM ' with liquid crystal indicator between the gate charge period charges to gate high levle voltage VGH '.
Step 604: according to the inversion signal VFLK---_INV ' of switch controlling signal VFLK ', at the gate interdischarge interval, the supply voltage VSUP that stray capacitance C_VGHM ' is discharged to the supply power supply is summed up in equivalence.
Step 606: control equivalence sum total stray capacitance C_VGHM and be discharged to the discharge slope of supply voltage at the gate interdischarge interval by gate high levle voltage VGH '; Wherein, the supply power supply is at least one input voltage and the central one of at least one output voltage of electric power management circuit 30.
Step 608: finish.
Wherein the details of each step can be analogized and get with the operation of the corresponding assembly of gate pulse modulation circuit 508 by gate PM circuit 308, does not also give unnecessary details at this.
In known technology, gate PM circuit 20 is summed up the stored charge discharge of stray capacitance C VGHM to ground at the gate interdischarge interval with equivalence, can't effectively utilize.In comparison, above-described embodiment is discharged to the supply power supply at the gate interdischarge interval with gate control signal VGHM ' (i.e. the voltage of equivalence sum total stray capacitance C_VGHM '), and the supply power supply is input voltage VIN 1～VIN4 and the central one of output voltage VO UT1～VOUT4 of electric power management circuit 30, therefore equivalence can be summed up the stored spurious charge of stray capacitance C_VGHM ' and recycle, to promote the conversion efficiency of power supply.
The above is only the preferred embodiments of the present invention, and all equalizations of doing according to claim of the present invention change and modify, and all should belong to covering scope of the present invention.
Claims (19)
1. an electric power management circuit, be used for a liquid crystal indicator, it is characterized in that, includes:
One or more power generation circuit receives respectively one or more input voltage, and produces one or more output voltage;
One gate PM circuit is coupled between a gate high levle voltage source and a control of discharge end, in order to produce a gate control signal; And
One discharge controller is coupled to this control of discharge end, in order to a discharge path of this gate PM circuit to be provided, wherein
One in the middle of this gate PM circuit and this discharge controller more is coupled to a supply power supply, so that this gate PM circuit is discharged to this supply power supply at a gate interdischarge interval, and
This supply power supply is the one in the middle of this one or more input voltage and this one or more output voltage.
2. electric power management circuit as claimed in claim 1, is characterized in that, this gate PM circuit includes:
One charge switch is coupled between this gate high levle voltage source and a gate control signal output terminal;
One discharge switch is coupled between this gate control signal output terminal and this control of discharge end.
3. electric power management circuit as claimed in claim 2, is characterized in that, this discharge controller is coupled between this control of discharge end and this supply power supply.
4. electric power management circuit as claimed in claim 1, is characterized in that, this gate PM circuit includes:
One charge switch is coupled between this gate high levle voltage source and a gate control signal output terminal;
One current mirror is coupled between this gate control signal output terminal and this control of discharge end; And
One discharge switch is coupled between this current mirror and this supply power supply.
5. electric power management circuit as claimed in claim 4, is characterized in that, this discharge controller is coupled between this control of discharge end and an earth potential.
6. electric power management circuit as claimed in claim 1, is characterized in that, this one or more power generation circuit comprises in the middle of a DC-DC converter, a low dropout voltage regulator and a voltage buffer one at least.
7. electric power management circuit as claimed in claim 1, is characterized in that, this discharge controller includes a discharge resistance, and it is coupled between this control of discharge end and this supply power supply.
8. electric power management circuit as claimed in claim 1, is characterized in that, this discharge controller includes a discharge resistance, and it is coupled between this control of discharge end and an earth potential.
9. electric power management circuit as claimed in claim 4, it is characterized in that, between a gate charge period, this charge switch conducting and this discharge switch are closed in response to first standard of a switch controlling signal, so that gate control signal output terminal is charged, and at this gate interdischarge interval, this charge switch is closed and this discharge switch conducting in response to the second of this switch controlling signal is accurate, is discharged to this supply voltage with the voltage with this gate control signal output terminal.
10. an electric power management circuit, be used for a liquid crystal indicator, it is characterized in that, includes:
One or more power generation circuit receives respectively one or more input voltage, and produces one or more output voltage;
One gate PM circuit includes:
One charge switch is coupled between a gate high levle voltage source and a gate control end;
One discharge switch is coupled between this gate control end and a control of discharge end; And
One discharge controller is coupled between this control of discharge end and a supply power supply, and in order to a discharge path of this gate PM circuit to be provided, wherein this supply power supply is the one in the middle of this one or more input voltage and this one or more output voltage.
11. electric power management circuit as claimed in claim 9 is characterized in that, this discharge controller includes
One discharge resistance, it is coupled between this control of discharge end and this supply power supply.
12. electric power management circuit as claimed in claim 9 is characterized in that, this one or more power generation circuit comprises in the middle of a DC-DC converter, a low dropout voltage regulator and a voltage buffer one at least.
13. a gate PM circuit in order to produce the gate control signal of a liquid crystal indicator, is characterized in that, includes:
One charge switch is coupled between a gate high levle voltage source and a gate control signal output terminal;
One current mirror is coupled between this gate control signal output terminal and a control of discharge end; And
One discharge switch is coupled between current mirror and a supply power supply.
14. an electric power management circuit is characterized in that, includes:
Gate PM circuit as claimed in claim 13; And
One or more power generation circuit receives respectively one or more input voltage, and produces one or more output voltage, and wherein this supply power supply is the one in the middle of this one or more input voltage and this one or more output voltage.
15. electric power management circuit as claimed in claim 14 is characterized in that, more comprises:
One discharge controller is coupled to this control of discharge end, in order to a discharge path of this gate PM circuit to be provided.
16. electric power management circuit as claimed in claim 15 is characterized in that, this discharge controller is coupled between this control of discharge end and an earth potential.
17. electric power management circuit as claimed in claim 15 is characterized in that, this discharge controller includes
One discharge resistance, it is coupled between this control of discharge end and an earth potential.
18. electric power management circuit as claimed in claim 14 is characterized in that, this one or more power generation circuit comprises in the middle of a DC-DC converter, a low dropout voltage regulator and a voltage buffer one at least.
19. electric power management circuit as claimed in claim 14 is characterized in that, this current mirror comprises:
The first transistor, it is coupled between this gate control signal output terminal and this discharge switch; And
Transistor seconds, it has the control end that a control end is coupled to this first transistor, and it is coupled between a power supply and this control of discharge end.
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Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH06138845A (en) * | 1992-10-28 | 1994-05-20 | Sony Corp | Drive signal processing circuit of liquid crystal display device |
| WO2008029782A1 (en) * | 2006-09-08 | 2008-03-13 | Rohm Co., Ltd. | Power supply apparatus, liquid crystal driving apparatus and display apparatus |
| CN101211543A (en) * | 2006-12-29 | 2008-07-02 | Lg.菲利浦Lcd株式会社 | Liquid crystal device driving circuit and method |
| TW201110098A (en) * | 2009-09-10 | 2011-03-16 | Raydium Semiconductor Corp | Gate driver and operating method thereof |
| TW201123135A (en) * | 2009-12-24 | 2011-07-01 | Lg Display Co Ltd | Display device and method for controlling gate pulse modulation thereof |
-
2011
- 2011-11-18 CN CN201110367500.5A patent/CN103123770B/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH06138845A (en) * | 1992-10-28 | 1994-05-20 | Sony Corp | Drive signal processing circuit of liquid crystal display device |
| WO2008029782A1 (en) * | 2006-09-08 | 2008-03-13 | Rohm Co., Ltd. | Power supply apparatus, liquid crystal driving apparatus and display apparatus |
| CN101211543A (en) * | 2006-12-29 | 2008-07-02 | Lg.菲利浦Lcd株式会社 | Liquid crystal device driving circuit and method |
| TW201110098A (en) * | 2009-09-10 | 2011-03-16 | Raydium Semiconductor Corp | Gate driver and operating method thereof |
| TW201123135A (en) * | 2009-12-24 | 2011-07-01 | Lg Display Co Ltd | Display device and method for controlling gate pulse modulation thereof |
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