JP4621235B2 - Driving voltage control device, driving voltage switching method, and driving voltage switching device - Google Patents

Description

The present invention relates to a driving voltage control device , a driving voltage switching method, and a driving voltage switching device that control a load driving voltage for driving a load circuit such as a liquid crystal panel, and more specifically, more than a time constant due to load capacitance and load resistance. The present invention relates to a technique for raising a load drive voltage at a high speed at a speed corresponding to a short time.

  2. Description of the Related Art Conventionally, there is known a drive voltage control device that increases the speed while reducing power consumption by controlling the bias current of an operational amplifier (see, for example, Patent Document 1). An operational amplifier that has a boost function in an operational amplifier and realizes further speedup is known (see, for example, Patent Document 2).

  On the other hand, with higher resolution and larger screens of liquid crystal panels, higher precision and higher speed drive devices are required. Furthermore, in order to narrow the display panel in addition to supporting a large screen, it is desired not to increase the device size and to minimize the increase in current consumption.

  FIG. 31 shows a general active matrix type liquid crystal panel driving apparatus. 11 is a liquid crystal panel in which (X × Y) liquid crystal cells LC are arranged in a two-dimensional matrix, 12 is a control unit, 13 is a source driver, 14 is a gate driver, and 15 is a drive voltage control device. D1 to DX are X data lines connected from the source driver 13 to the source electrode of the liquid crystal cell LC, G1 to GY are Y gate lines connected from the gate driver 14 to the gate electrode of the liquid crystal cell LC, and COM is The counter electrode is commonly connected to each liquid crystal cell LC. The liquid crystal cell LC includes a switching element such as a TFT (Thin Film Transistor) and a liquid crystal element.

  Upon receiving the state instruction signal STATE indicating panel driving, the control unit 12 outputs display data DATA to the source driver 13 and outputs a scanning control signal LINE to the gate driver 14. The liquid crystal element included in the liquid crystal cell LC receives the higher target drive voltage VH or the lower target drive voltage VL supplied from the drive voltage control device 15 to the counter electrode COM. The source driver 13 supplies a data signal having a voltage value corresponding to the display data DATA indicating the gradation level output from the control unit 12 to the data lines D1 to DX. The gate driver 14 supplies a gate signal corresponding to the scanning control signal LINE output from the control unit 12 to the gate lines G1 to GY. The liquid crystal element included in the liquid crystal cell LC has a difference between the voltage value of the data signal applied to the data line and the voltage value of the higher target drive voltage VH or lower target drive voltage VL applied to the counter electrode. The corresponding transmittance is shown.

  The reason why the drive voltage control device 15 alternately repeats the high-order target drive voltage VH and the low-order target drive voltage VL in a certain cycle is to prevent burn-in of the liquid crystal element. This is referred to as an alternating drive method (line opposing inversion drive method).

FIG. 32 shows a general circuit configuration of a conventional drive voltage control apparatus. A1 is an operational amplifier, and 2 is a load circuit that equivalently represents a liquid crystal panel having a load capacitance _COUT and a load resistance _ROUT . When a signal having a waveform as shown in FIG. 34 (a) is input to the operational amplifier A1, the output waveform is as shown in FIG. 34 (b). The load drive voltage V _OUT output from the operational amplifier A1 converges to the higher target drive voltage VH. In this case, the lower one of the slew rate (internal slew rate) of the operational amplifier A1 and the external slew rate at the time constant due to the load capacitance C _OUT and the load resistance R _OUT of the load circuit 2 determines the overall delay time. If the internal slew rate of the operational amplifier A1 is sufficiently increased by the method of Patent Document 2, the system of the drive voltage control device is determined by the external slew rate, and the speed is saturated.

FIG. 33 shows a configuration example of a drive voltage control device that generates a drive voltage to a counter electrode for a liquid crystal screen in a mobile phone. The high-order target drive voltage VH (for example, 3V) and the low-order target drive voltage VL (for example, -3V) supplied to the liquid crystal screen are impedance-converted by the positive-side operational amplifier A1 and the negative-side operational amplifier A3, respectively. By switching the output changeover switch Sx at the timing, a voltage having an amplitude between −3 V and +3 V is supplied to the liquid crystal screen. Resistors R1 and R2 and capacitors C1 and C2 are for smoothing (for preventing oscillation). The resistor R _OUT and the capacitor C _OUT are equivalent models of a liquid crystal panel. The input / output waveforms are shown in FIG. The output changeover switch Sx is operated by the selection signal SEL from the timing control unit 3, and the positive-side operational amplifier A1 and the negative-side operational amplifier A3 are alternately selected. The voltage VH and the lower target drive voltage VL are alternately output.
JP 2003-216256 A (page 4-8, FIG. 1) Japanese Unexamined Patent Publication No. 2003-188852 (page 3-4, FIG. 1-3) Trikeps, “CMOS Analog Circuit Design Technology” 1998, P.A. 76-P. 77

In the drive voltage control apparatus of FIG. 33, a delay occurs in the output when the output changeover switch Sx is operated. Operational amplifier A1 and the capacitor C1 or operational amplifier A3 and internal slew rate and the load circuit 2 of the load capacitance C _OUT and the load resistor R external slew rate lower overall delay time-out of a time constant due to the _OUT of capacitor C2 To decide. Large-screen liquid crystal panels are subject to heavy loads and high speed for high resolution. If the gain boost type described in Patent Document 2 is applied to the operational amplifier A1 and the operational amplifier A3, the slew rate of the operational amplifier can be increased. However, since the external slew rate of the load circuit 2 is determined by the liquid crystal panel and is limited by that, it is difficult to remove the restriction on the speed limit (see Non-Patent Document 1).

  The present invention has been created in view of such circumstances, and provides a drive voltage control device capable of quickly starting up a load drive voltage at a speed corresponding to a time shorter than the time constant of the load circuit. It is an object.

  In the following, the “buffer” corresponds to the general concept of the operational amplifier described above. The buffer includes an operational amplifier and a source follower as long as it has a function of converting the input signal to impedance and supplying a load drive voltage to the load circuit.

(1) The drive voltage control device according to the present invention is:
A buffer that supplies a load drive voltage obtained by impedance conversion of the input signal to the load circuit, and a boost voltage that is higher than the target drive voltage at the initial stage of voltage change as a voltage input to the buffer for a certain period, And an input level control unit for switching.

  The load capacity in the load circuit reduces the rate of increase of the applied voltage to the load circuit. This is a delay in the rise characteristic of the load drive voltage. Therefore, the input level control unit performs control so that a boost voltage higher than the target drive voltage is input to the buffer at the initial stage of voltage change. This suppresses a decrease in the voltage increase speed that has occurred due to the load capacity, and speeds up the rise of the load drive voltage. When the boost voltage is applied for a predetermined period and the load drive voltage approaches the target drive voltage, the input level control unit switches the input voltage to the buffer from the boost voltage to the normal input signal voltage. Therefore, when the load driving voltage is converged to the target driving voltage, it is possible to converge at a high speed at a speed corresponding to a time shorter than a time constant determined by the capacity and resistance of the load circuit.

  (2) In the configuration of (1), there is an aspect in which the boost voltage at the initial stage of voltage change is a voltage whose absolute value is equal to or higher than the power supply voltage (VDD) of the buffer. In this case, since the boost voltage is sufficiently high, it is possible to significantly shorten the convergence time of the load drive voltage to the target drive voltage.

  (3) In the configuration of (1), there is an aspect in which the boost voltage at the initial stage of voltage change is a voltage whose absolute value is smaller than the power supply voltage (VDD) of the buffer. In this case, the convergence time of the load drive voltage to the target drive voltage is slightly longer than that in (2), but it is still improved as compared with the prior art and low power consumption is achieved.

  (4) In the configurations of (1) to (3), the comparator further compares the voltage of the output terminal with the load driving voltage, and operates according to the comparison result of the comparator, and the load driving voltage is The boost voltage is stepped down when higher than the target drive voltage, the boost voltage is not changed if the load drive voltage is equal to the target drive voltage, and the boost voltage is lowered when the load drive voltage is lower than the target drive voltage. There is a mode in which a boost voltage control unit that boosts the voltage is provided. With this configuration, even if the load varies or fluctuates for some reason, the boost voltage is automatically adjusted through measurement of the load drive voltage by the boost voltage control unit, so the speed is equivalent to a time shorter than the time constant. Thus, it is possible to stabilize the convergence to the high-speed target drive voltage.

  (5) In the configuration of (4), there is an aspect in which the comparator repeats the comparison operation a plurality of times with a set reference time as a period. If comprised in this way, it will become possible to make load drive voltage close to a target drive voltage reliably.

  (6) In the configurations of (4) and (5), when the convergence time is not updated or when the load circuit is not changed, the boost voltage is stored and the comparator is turned off. There are aspects. With this configuration, it is not necessary to operate the automatic adjustment function unnecessarily, and unnecessary power consumption can be avoided.

(7) Further, the drive voltage control apparatus according to the present invention includes:
A buffer for supplying a load drive voltage obtained by impedance conversion of the input signal to the load circuit;
A step-up control switch interposed between the output terminal of the buffer and a power source of a boost voltage higher than the target drive voltage;
And a timing control unit that switches the boost control switch to an OFF state after the switch is turned ON for a certain period at the beginning of voltage change.

  In this configuration, the timing control unit turns on the boost control switch at the initial stage of voltage change, and applies a boost voltage higher than the target drive voltage to the output terminal of the buffer. As a result, the decrease in the voltage increase rate that has occurred due to the load capacity is suppressed, and the rise of the load drive voltage is increased. When the load drive voltage approaches the target drive voltage, the timing control unit turns off the boost control switch. Therefore, when the load driving voltage is converged to the target driving voltage, it is possible to converge at a high speed at a speed corresponding to a time shorter than a time constant determined by the capacity and resistance of the load circuit.

(8) Further, the drive voltage control apparatus according to the present invention includes:
A buffer for supplying a load drive voltage obtained by impedance conversion of the input signal to the load circuit;
As an input to the buffer, an input selection switch for selecting either the voltage of the input signal and a boost voltage higher than the target drive voltage;
A smoothing capacitor inserted between the output terminal of the buffer and the ground;
An output control switch interposed between the smoothing capacitor and the load circuit;
Timing control is performed on the input selection switch and the output control switch, and in the initial stage of voltage change, the boost voltage is selected by the input selection switch when the output control switch is in an OFF state. And a timing control unit that controls the input switch to select the voltage of the input signal after the control switch is turned on.

  In this configuration, the timing control unit turns off the output control switch at the initial stage of voltage change, and causes the input selection switch to select a boost voltage having a higher potential than the target drive voltage. As a result, the smoothing capacitor is charged with the boost voltage. In accordance with the display timing, the timing control unit switches the output control switch to the on state, and applies a boost voltage having a higher potential than the target drive voltage from the smoothing capacitor to the load circuit. As a result, the decrease in the voltage increase rate that has occurred due to the load capacity is suppressed, and the rise of the load drive voltage is increased. When the load drive voltage approaches the target drive voltage, the timing control unit causes the input selection switch to select the voltage of the input signal. Therefore, when the load driving voltage is converged to the target driving voltage, it is possible to converge at a high speed at a speed corresponding to a time shorter than a time constant determined by the capacity and resistance of the load circuit.

(9) Further, the drive voltage control apparatus according to the present invention includes:
A first buffer that impedance-converts the input signal and supplies a load drive voltage to the load circuit;
A second buffer for supplying a boost voltage higher than a target drive voltage to the load circuit;
An output selection switch for selecting one of the output of the first buffer and the output of the second buffer;
A smoothing capacitor inserted between the output terminal of the output selection switch and the ground;
An output control switch interposed between the smoothing capacitor and the load circuit;
Timing control is performed on the output selection switch and the output control switch. In the initial stage of voltage change, the output selection switch selects the output of the second buffer when the output control switch is off, and then the display timing is reached. In response, the output control switch is switched to an on state, and thereafter, the output selection switch includes a timing control unit that selects the output of the first buffer.

  In this configuration, the timing control unit turns off the output control switch at the initial stage of voltage change, and selects a boost voltage higher than the target drive voltage that is the output of the second buffer by using the output selection switch. Let As a result, the smoothing capacitor is charged with the boost voltage. In accordance with the display timing, the timing control unit switches the output control switch to the on state, and applies a boost voltage having a higher potential than the target drive voltage from the smoothing capacitor to the load circuit. As a result, the decrease in the voltage increase rate that has occurred due to the load capacity is suppressed, and the rise of the load drive voltage is increased. When the load drive voltage approaches the target drive voltage, the timing control unit causes the output selection switch to select the voltage of the input signal that is the output of the first buffer. Therefore, when the load driving voltage is converged to the target driving voltage, it is possible to converge at a high speed at a speed corresponding to a time shorter than a time constant determined by the capacity and resistance of the load circuit.

  (10) In the drive voltage control apparatus mentioned in the first and second buffers, the timing control unit stops the operation of the second buffer when selecting the output of the first buffer, There is a mode in which the operation of the first buffer is stopped when the output of the second buffer is selected. If configured in this way, the buffer whose output is not selected stops its operation, so that it is possible to reduce power consumption.

(11) Further, the drive voltage control apparatus according to the present invention includes:
A first buffer that impedance-converts the input signal and supplies a load drive voltage to the load circuit;
A second buffer for supplying a boost voltage higher than a target drive voltage to the load circuit;
A smoothing capacitor inserted between a connection point between the output terminal of the first buffer and the output terminal of the second buffer and the ground;
An output control switch interposed between the smoothing capacitor and the load circuit;
Timing control is performed on the operation of the output selection switch and the first buffer and the operation of the second buffer. In the initial stage of voltage change, the operation of the first buffer is stopped when the output control switch is off. And a timing control unit that operates the second buffer, then switches on the output control switch according to display timing, and then operates the first buffer and stops the operation of the second buffer. It is equipped with.

  In this configuration, the timing control unit turns off the output control switch at the initial stage of voltage change, operates the second buffer, and stops the first buffer. As a result, the smoothing capacitor is charged with the boost voltage. In accordance with the display timing, the timing control unit switches the output control switch to the on state, and applies a boost voltage having a higher potential than the target drive voltage from the smoothing capacitor to the load circuit. As a result, the decrease in the voltage increase rate that has occurred due to the load capacity is suppressed, and the rise of the load drive voltage is increased. When the load drive voltage approaches the target drive voltage, the timing control unit operates the first buffer and stops the second buffer. Therefore, when the load driving voltage is converged to the target driving voltage, it is possible to converge at a high speed at a speed corresponding to a time shorter than a time constant determined by the capacity and resistance of the load circuit. In addition, since the operation of the non-selected buffer is stopped, it is possible to reduce power consumption.

(12) Further, the drive voltage control apparatus according to the present invention includes:
A buffer for supplying a load drive voltage obtained by impedance conversion of the input signal to the load circuit;
A timing control switch and an output control switch inserted between the output terminal of the buffer and a load circuit;
A step-up control switch interposed between a connection point between the timing control switch and the output control switch and a power source of a boost voltage higher than a target drive voltage;
A smoothing capacitor inserted between a connection point between the timing control switch and the output control switch and a ground;
Controls the boost control switch, the output control switch, and the timing control switch. At the initial stage of voltage change, the output control switch is turned on while the timing control switch is turned off, and the boost control switch is turned on for a certain period. And a timing control unit for controlling to switch the timing control switch to the on state.

  In this configuration, in the initial stage of voltage change, the timing control unit turns on the output control switch with the timing control switch turned off, turns on the boost control switch, and smoothes the smoothing capacitor with a boost voltage higher than the target drive voltage. Is charged and the boost voltage of the smoothing capacitor is applied to the load circuit. As a result, the decrease in the voltage increase rate that has occurred due to the load capacity is suppressed, and the rise of the load drive voltage is increased. When the load drive voltage approaches the target drive voltage, the timing control unit turns off the boost control switch and turns on the timing control switch to select the output of the buffer. Therefore, when the load driving voltage is converged to the target driving voltage, it is possible to converge at a high speed at a speed corresponding to a time shorter than a time constant determined by the capacity and resistance of the load circuit.

(13) Further, the drive voltage control apparatus according to the present invention includes:
A buffer for supplying a load drive voltage obtained by impedance conversion of the input signal to the load circuit;
A smoothing capacitor inserted between the output terminal of the buffer and the ground;
A step-up control switch interposed between the output terminal of the buffer and a power source of a boost voltage higher than the target drive voltage;
An output control switch interposed between the smoothing capacitor and the load circuit;
Timing control of the operation of the output selection switch, the boost control switch, and the buffer. In the initial stage of voltage change, the boost control switch is turned on when the output control switch is turned off, and the output of the buffer is set high. And a timing control unit that switches the output control switch to an on state, switches the boost control switch to an off state, and operates the buffer.

  In contrast to the above (12), the timing control switch at the output terminal of the buffer is omitted, and the operation of the buffer is stopped instead. In this configuration, at the initial stage of voltage change, the timing control unit turns off the output control switch and turns on the boost control switch with the buffer output in the high impedance state, and the boost control voltage is higher than the target drive voltage. Charge the smoothing capacitor. When the charging voltage approaches the target drive voltage, the timing control unit switches the boost control switch to the off state, switches the output control switch to the on state, and applies the boost voltage of the smoothing capacitor to the load circuit. As a result, the decrease in the voltage increase rate that has occurred due to the load capacity is suppressed, and the rise of the load drive voltage is increased. Then, the timing control unit operates the buffer. Therefore, when the load driving voltage is converged to the target driving voltage, it is possible to converge at a high speed at a speed corresponding to a time shorter than a time constant determined by the capacity and resistance of the load circuit.

(14) Further, the drive voltage control apparatus according to the present invention includes:
A buffer for supplying a load drive voltage obtained by impedance conversion of the input signal to the load circuit;
A smoothing capacitor inserted between the output terminal of the buffer and the ground;
A feedback control switch that controls feedback of the buffer and switches between a state where the inverting input terminal of the buffer is short-circuited to the ground and a state where the buffer is short-circuited to the output terminal;
An output control switch interposed between the smoothing capacitor and the load circuit;
The timing control of the output control switch and the feedback control switch, and inversion of the buffer to output the power supply voltage level by operating the buffer as a comparator for a predetermined period in the off state of the output control switch The feedback control switch is controlled to short-circuit the input terminal to the ground, and the output control switch is turned on according to the display timing, and then the inverting input terminal of the buffer to operate the buffer as a voltage follower And a timing control unit that controls the feedback control switch so as to short-circuit the output terminal.

  In this configuration, the timing control unit controls the feedback control switch with the output control switch turned off at the initial stage of voltage change, and connects the inverting input terminal of the buffer to the ground. As a result, the buffer operates as a comparator, outputs the power supply voltage level, and charges the smoothing capacitor at high speed. Then, the output control switch is turned on according to the display timing, and the charging voltage of the smoothing capacitor is applied to the load circuit. As a result, the decrease in the voltage increase rate that has occurred due to the load capacity is suppressed, and the rise of the load drive voltage is increased. When the load drive voltage approaches the target drive voltage, the timing control unit controls the feedback control switch to short-circuit the inverting input terminal of the buffer to the output terminal, and operates the buffer as a voltage follower. Therefore, when the load driving voltage is converged to the target driving voltage, it is possible to converge at a high speed at a speed corresponding to a time shorter than a time constant determined by the capacity and resistance of the load circuit.

(15) Further, the drive voltage control apparatus according to the present invention provides:
A buffer for supplying a load drive voltage obtained by impedance conversion of the input signal to the load circuit;
A smoothing capacitor inserted between the output terminal of the buffer and the ground;
An output control switch interposed between the smoothing capacitor and the load circuit;
A step-up control switch interposed between a connection point between the output control switch and the load circuit and a power source having a boost voltage higher than a target drive voltage;
The potential of a connection point between the output control switch and the load circuit is monitored, and when the voltage is less than a predetermined reference voltage, the boost control switch is controlled to be in an ON state, and when the voltage is higher than the reference voltage, the boost control switch A comparator for controlling the
A timing control unit for controlling the timing of the output control switch.

  In this configuration, the point is to use a comparator to perform on / off control of a boost control switch that applies a high boost voltage to the load circuit. Since the timing control unit turns on the output control switch and the monitoring potential is low, the smoothing capacitor is charged with a boost voltage higher than the target drive voltage when the boost control switch is on. Along with this charging, the charging voltage increases. The charge potential is monitored by the comparator, and the boost control switch is turned off when the voltage becomes equal to or higher than the reference voltage. The turn-off timing is more accurate than when the boost control switch is turned off by the timing control unit. In this case as well, the smoothing capacitor is charged with a boost voltage that is higher than the target drive voltage, so the time required to converge the load drive voltage to the target drive voltage is shorter than the time constant determined by the capacity and resistance of the load circuit. It is possible to converge at a high speed at a speed to perform. Since the control timing of the boost control switch is performed based on the actual measurement of the voltage applied to the load circuit, the timing control becomes highly accurate.

(16) Further, the drive voltage control apparatus according to the present invention provides:
A positive-side buffer that impedance-converts a positive-side input signal and supplies a positive-side load drive voltage to the load circuit;
As an input voltage to the positive-side buffer, a positive-side input selection switch that selects either the positive-side input signal voltage or the positive-side boost voltage higher than the positive-side load drive voltage;
A positive-side smoothing capacitor inserted between the output terminal of the positive-side buffer and the ground;
A negative-side buffer for impedance-converting a negative-side input signal and supplying a negative-side load driving voltage to the load circuit;
As an input voltage to the negative side buffer, a negative side input selection switch that selects either the negative side input signal voltage or the negative side boost voltage lower than the negative side load drive voltage;
A negative-side smoothing capacitor inserted between the output terminal of the negative-side buffer and the ground;
An output changeover switch for alternately switching the output of the positive side buffer and the output of the negative side buffer at a predetermined timing;
Timing control of the positive side input selection switch, the negative side input selection switch and the output changeover switch, and when the output changeover switch selects the output of the positive side buffer, the positive side input selection When the switch selects the voltage of the positive-side input signal and the negative-side input selection switch selects the negative-side boost voltage while the output changeover switch selects the output of the negative-side buffer And a timing control unit that controls the negative side input selection switch to select the voltage of the negative side input signal and the positive side input selection switch to select the positive side boost voltage. Is.

  This configuration has the following effects.

  (I) In a period in which the output selector switch selects the output of the negative-side buffer under the control of the timing control unit, the positive-side input selection switch selects the higher positive-side boost voltage, which is the positive-side buffer. The smoothing capacitor on the positive electrode side is charged in advance via At this time, the negative side input selection switch selects a normal level input voltage and inputs it to the load circuit via the negative side buffer.

  (Ii) In a period in which the output changeover switch selects the output of the positive-side buffer under the control of the timing control unit, the negative-side input selection switch selects the lower negative-side boost voltage, which is the negative-side buffer. The smoothing capacitor on the negative electrode side is charged in advance via At this time, the positive side input selection switch selects a normal level input voltage and inputs it to the load circuit via the positive side buffer.

  And a timing control part switches said (i) state and (ii) state alternately by an output switch.

  When switching from (i) to (ii), the positive-side smoothing capacitor has already been charged with the positive-side boost voltage, so the load drive voltage for the load circuit converges rapidly to the convergence target voltage. . Similarly, when switching from (ii) to (i), the negative-side smoothing capacitor has already been charged with the negative-side boost voltage, so the load drive voltage for the load circuit converges quickly to the target voltage. Converge to. The above operation is cyclically repeated to obtain a voltage waveform for driving the load in an alternating manner. Also in this case, it is possible to drive the load at a high speed at a speed corresponding to a time shorter than the time constant determined by the load of the liquid crystal panel.

(17) Further, the drive voltage control apparatus according to the present invention includes:
A positive-side buffer that impedance-converts a positive-side input signal and supplies a positive-side load drive voltage to the load circuit;
A positive-side smoothing capacitor inserted between the output terminal of the positive-side buffer and the ground;
A positive-side boost control switch interposed between the positive-side buffer output terminal and a positive-side boost voltage power supply higher than the positive-side load drive voltage;
A negative-side buffer for impedance-converting a negative-side input signal and supplying a negative-side load driving voltage to the load circuit;
A negative-side smoothing capacitor inserted between the output terminal of the negative-side buffer and the ground;
A negative-side boost control switch interposed between an output terminal of the negative-side buffer and a negative-side boost voltage power source lower than the negative-side load drive voltage;
An output changeover switch for alternately switching the output of the positive side buffer and the output of the negative side buffer at a predetermined timing;
Timing control of the positive side boost control switch, the negative side boost control switch and the output changeover switch, and when the output changeover switch selects the output of the positive side buffer, the negative side boost control And a timing control unit that controls the positive-side boost control switch to be turned on when the output changeover switch selects the output of the negative-side buffer when the switch is turned on.

  This configuration has the following effects.

  (I) In the period when the output selector switch selects the output of the negative-side buffer under the control of the timing control unit, at this time, the negative-side smoothing capacitor is already charged with the negative-side boost voltage on the negative-side. The negative-side buffer inputs the negative-side input signal to the load circuit in a stable voltage state. Then, when the boost control switch on the positive electrode side is turned on, charging of the smoothing capacitor on the positive electrode side is started with a boost voltage on the higher positive electrode side.

  (Ii) In the period when the output changeover switch selects the output of the positive-side buffer under the control of the timing control unit, at this time, the positive-side smoothing capacitor is already charged with the positive-side boost voltage on the positive-side. The positive-side buffer inputs the positive-side input signal to the load circuit in a stable voltage state. Then, when the boost control switch on the negative electrode side is turned on, charging of the smoothing capacitor on the negative electrode side is started with the boost voltage on the lower negative electrode side.

  And a timing control part switches said (i) state and (ii) state alternately by an output switch.

  When switching from (i) to (ii), the positive-side smoothing capacitor has already been charged with the positive-side boost voltage, so the load drive voltage for the load circuit converges rapidly to the convergence target voltage. . Similarly, when switching from (ii) to (i), the negative-side smoothing capacitor has already been charged with the negative-side boost voltage, so the load drive voltage for the load circuit converges quickly to the target voltage. Converge to. The above operation is cyclically repeated to obtain a voltage waveform for driving the load in an alternating manner. Also in this case, it is possible to drive the load at a high speed at a speed corresponding to a time shorter than the time constant determined by the load of the liquid crystal panel.

(18) Further, the drive voltage control apparatus according to the present invention provides:
A positive-side buffer that impedance-converts a positive-side input signal and supplies a positive-side load drive voltage to the load circuit;
A positive-side smoothing capacitor inserted between the output terminal of the positive-side buffer and the ground;
A negative-side buffer for impedance-converting a negative-side input signal and supplying a negative-side load driving voltage to the load circuit;
A negative-side smoothing capacitor inserted between the output terminal of the negative-side buffer and the ground;
An output changeover switch that alternately switches the output of the positive side buffer and the output of the negative side buffer at a predetermined timing and outputs the output to the load circuit;
A timing control unit for timing control of the output changeover switch;
A positive-side boost control switch interposed between an output terminal of the output changeover switch and a positive-side boost voltage power supply higher than the positive-side load drive voltage;
The potential of the smoothing capacitor on the positive electrode side is monitored, and when the voltage is lower than a predetermined reference voltage, the boost control switch on the positive electrode side is controlled to be in an ON state, and when the voltage becomes equal to or higher than the reference voltage, the boost control switch on the positive electrode side A comparator on the positive electrode side that controls the
A negative-side boost control switch interposed between an output terminal of the output changeover switch and a negative-side boost voltage power supply lower than the negative-side load drive voltage;
The potential of the negative-side smoothing capacitor is monitored, and when the reference voltage exceeds a predetermined reference voltage, the negative-side boost control switch is controlled to be in an ON state, and when the reference voltage is lower than the reference voltage, the negative-side boost control switch is controlled. And a comparator on the negative electrode side that controls the OFF state.

  In this configuration, similarly to the above (17), in obtaining a voltage waveform for driving the load in an alternating current manner, at a speed corresponding to a time shorter than the time constant determined by the load of the liquid crystal panel on the positive electrode side or the negative electrode side. It is possible to drive the load at high speed, and furthermore, the boost control switch is controlled by monitoring the voltage applied to the load circuit with the positive side comparator and the negative side comparator, so that timing control is possible. High accuracy.

(19) Further, the drive voltage control apparatus according to the present invention provides:
A positive-side buffer that impedance-converts a positive-side input signal and supplies a positive-side load drive voltage to the load circuit;
A positive-side smoothing capacitor inserted between the output terminal of the positive-side buffer and the ground;
A negative-side buffer for impedance-converting a negative-side input signal and supplying a negative-side load driving voltage to the load circuit;
A negative-side smoothing capacitor inserted between the output terminal of the negative-side buffer and the ground;
An output changeover switch that alternately switches the output of the positive side buffer and the output of the negative side buffer at a predetermined timing and outputs the output to the load circuit;
A positive-side boost control switch interposed between an output terminal of the output changeover switch and a positive-side boost voltage power supply higher than the positive-side load drive voltage;
A negative-side boost control switch interposed between an output terminal of the output changeover switch and a negative-side boost voltage power supply lower than the negative-side load drive voltage;
The inverting input terminal is connected to the reference potential on the positive side and the reference potential on the negative side via a reference potential changeover switch that operates in a mutually contradictory manner, and the non-inverting input terminal is connected to the output terminal of the output changeover switch. And monitoring the potential of the smoothing capacitor on the positive electrode side and the potential of the smoothing capacitor on the negative electrode side, and when the applied voltage is less than a predetermined reference voltage with the reference potential on the positive electrode side being selected. The positive side boost control switch is controlled to be in an ON state, and when the reference voltage is equal to or higher, the positive side boost control switch is controlled to be in an OFF state and the negative side reference potential is selected. When the applied voltage exceeds a predetermined reference voltage, the negative side boost control switch is controlled to be in an ON state, and when the applied voltage is equal to or lower than the reference voltage, the negative side boost control switch is controlled. A comparator combined type for controlling the switch in the off state,
And a timing control unit for controlling the timing of the output changeover switch and the two reference potential changeover switches operating in contradiction.

  In this configuration, in the same manner as in the above (18), in obtaining a voltage waveform for driving the load in an alternating current manner, at a speed corresponding to a time shorter than a time constant determined by the load of the liquid crystal panel on the positive electrode side or the negative electrode side. It is possible to drive the load at high speed, and in order to make the timing control highly accurate, the positive side as a comparator that monitors the voltage applied to the load circuit as the cause of on / off control of the boost control switch Therefore, the circuit configuration can be simplified.

  (20) In the drive voltage control device referred to the above boost control switch, the boost control switch is configured by a low breakdown voltage transistor, and a clamp element that performs a voltage drop between the low breakdown voltage transistor and the power supply of the boost voltage is provided. There is an aspect of being inserted. With this configuration, the transistor as the boost control switch can be configured with a breakdown voltage equal to or lower than the power supply voltage of the buffer. A transistor having a low withstand voltage has a low on-resistance of the switch, and the switching speed is improved.

  (21) Further, a plurality of clamp elements connected in series as the clamp elements are provided, and a short-circuit switch element is connected in parallel to each of the plurality of clamp elements, and the plurality of short-circuit switch elements are arbitrarily turned on / off There is an aspect in which a switch control unit for controlling is provided. With this configuration, the rising of the applied voltage to the load circuit can be achieved at an optimum voltage level by adjusting the number of clamp elements to be operated among a plurality of clamp elements for various load circuits with different loads. It is possible to increase the speed.

  (22) The clamp element may be a diode-connected transistor, a transistor biased in a saturation region, a diode, or a resistor.

  (23) In the configurations of (1) to (22) above, there is an aspect in which the buffer is configured by an operational amplifier.

  (24) In the configurations of (1) to (22) above, there is an aspect in which the buffer is configured by a source follower.

  In the case of an operational amplifier, the voltage accuracy is originally high, so it can be said that it is more suitable for convergence to the target drive voltage.

  According to the present invention, the load can be driven at a high speed at a speed corresponding to a time shorter than the time constant determined by the load of the liquid crystal panel. It does not complicate the buffer.

  Further, by optimizing the drive capability of the buffer that accumulates charges in the smoothing capacitor, the mounting area of the liquid crystal driver on which the drive voltage control device is mounted can be reduced, and low power consumption can be realized.

  Embodiments of a drive voltage control apparatus according to the present invention will be described below in detail with reference to the drawings.

(Embodiment 1)
FIG. 1 is a circuit diagram showing a configuration of a drive voltage control device for a liquid crystal panel according to Embodiment 1 of the present invention. In FIG. 1, A1 is an operational amplifier as a preferred example of a buffer, 1 is an input level control unit, and 2 is a load circuit. The output terminal of the operational amplifier A1 is feedback-connected to the inverting input terminal (−). A load circuit 2 of a liquid crystal panel including a load resistor R _OUT and a load capacitor C _OUT is connected to the output terminal of the operational amplifier A1. The load circuit 2 is expressed as an equivalent circuit. The input level control unit 1 is interposed between the non-inverting input terminal (+) of the operational amplifier A1 and the ground, and controls the voltage level applied to the non-inverting input terminal (+) of the operational amplifier A1. Further, the output terminal OUT outputs a high-side target drive voltage VH having a high voltage level and a low-side target drive voltage VL having a low voltage level at a constant cycle.

  Here, the convergence time τs will be described. The convergence time is the time required to reach 97% of the voltage difference between the high-order target drive voltage VH and the low-order target drive voltage VL. Here, for convenience of explanation, it is assumed to be 97%, but the convergence time τs may be changed depending on the liquid crystal panel and the driving method.

  First, the rising convergence time τs will be described.

  When both the input voltage and the output voltage are the target drive voltage VL on the lower side and are switched at a constant cycle (1 line of liquid crystal = 30 microseconds, 1 frame = 16 milliseconds, etc.), first the input voltage is higher The load drive voltage V1 output from the operational amplifier A1 gradually approaches the higher target drive voltage VH from the lower target drive voltage VL. At this time, the time until the output voltage V1 reaches VL + 0.97 × (VH−VL) is the rising convergence time τs.

  Similarly, in the case of the falling, both the input voltage and the output voltage are the target drive voltage VH on the higher side, and have a constant cycle (1 line of liquid crystal = 30 microseconds, 1 frame = 16 milliseconds, etc.) First, the input voltage becomes the lower target drive voltage VL, and the load drive voltage V1 output from the operational amplifier A1 gradually changes from the higher target drive voltage VH to the lower target drive voltage VL. Get closer. At this time, the time until the output voltage V1 reaches VH−0.97 × (VH−VL) is the falling convergence time τs.

  The above is an explanation in the case of ± 97% convergence. However, in the case of 95% or 99%, if 0.95 or 0.99 is substituted in place of 0.97 in the above formula, the same can be handled. it can.

  2A is a waveform of an input voltage to the operational amplifier A1, FIG. 2B is a waveform of an input voltage subjected to input level control for the operational amplifier A1, and FIG. 2C is an input of FIG. 2A. FIG. 2D shows the waveform of the load drive voltage output to the input of FIG. 2B.

  As shown in FIG. 2A, the input voltage rises from the lower target drive voltage VL to the higher target drive voltage VH at the beginning of the voltage change. The rise time of the input voltage is sufficiently shorter than the switching cycle (in this case, ΔT = T2−T1).

  Next, as shown in FIG. 2B, the input level control unit 1 boosts the voltage higher by the voltage ΔV than the high-level target drive voltage VH at the initial stage of the voltage change to be boosted from the low-level target drive voltage VL. The voltage (VH + ΔV) is applied for a certain period, and then level control is performed in which the higher-side target drive voltage VH is continuously applied. ΔV is an increase in boost voltage. The higher target drive voltage VH is a DC voltage determined according to the pixel data of the liquid crystal display.

  Here, the fixed period is equal to or higher than the unity gain frequency of the operational amplifier A1, and specifically, (VH + ΔV−VL) / (slew rate of the operational amplifier A1) is selected.

  Now, if VH = 5.0V, ΔV = 1.0V, VL = 0V, and the slew rate of the operational amplifier A1 is 1 V / μs, the fixed time may be 6 μs.

  The operation at this time is an initial stage of the voltage change by the control of the drive voltage control device, and the voltage by the input level control unit 1 is not the target drive voltage VH on the higher side but the boost voltage (VH + ΔV) higher than that. The operation starts to converge, and then is returned to the higher target drive voltage VH. The load drive voltage output from the operational amplifier A1 rises rapidly at a speed corresponding to a time shorter than the time constant of the load circuit 2 of the liquid crystal panel, and obtains a waveform as shown in FIG. FIG. 2C shows a conventional waveform in which the input level is not controlled. According to the present embodiment, the convergence time τs is greatly shortened.

  It is assumed that the internal slew rate of the operational amplifier A1 (charge time to the phase compensation capacitor of the operational amplifier) is sufficiently higher than the external slew rate (charge time from the output of the operational amplifier to the load resistor and the capacitor). Therefore, the operational amplifier A1 is designed so that the convergence time τs is determined by the external slew rate.

  The output waveforms in FIGS. 2C and 2D will be described in more detail.

Consider the case of FIG. 2C corresponding to the load driving voltage of the prior art. A time constant determined by the load (C _OUT × R _OUT ) of the load circuit 2 is τ (= C _OUT × R _OUT ). Assuming that R _OUT = 100Ω and C _OUT = 100 nF, the time constant τ = R _OUT × C _OUT = 10 microseconds (μs). It is assumed that the necessary convergence time τs is a times the time constant τ (τs = a · τ). Considering the equation for charging and discharging,
1-exp (−τs / τ) = 1−exp (−a) = 0.97 (1)
Than,
a = −LN (1−0.97) (2)
It becomes. Here, LN is a natural logarithm.

  In the case of FIG. 2C, a is a≈3.5. Therefore, the convergence time τs is approximately 35 μs.

The case of FIG. 2D showing the load driving voltage of the present embodiment will be described. in this case,
a = −LN (1−0.97 × (VH−VL) / (VH + ΔV−VL)) (3)
It can be obtained more. As numerical examples, it is assumed that VH = 5.0V, ΔV = 1.0V, and VL = 0V.

In the case of FIG. 2D, from the equation (3),
a = −LN (1−0.97 · 5/6)
= -LN (1-0.808) = 1.65 (4)
Thus, the convergence time τs is 16.5 μs. This is about 47% of 35 μs in the case of the prior art, and the convergence time τs is greatly shortened.

  From the above, the convergence time τs that required 3.5τ in the conventional signal processing can be set to 1.65τ in the present embodiment, which exceeds the speed constraint of the time constant when driving with the conventional voltage setting. Shorter convergence time τs can be obtained.

  If the convergence time τs is other than 97%, a desired value may be substituted for 0.97 in the above equations.

Furthermore, if the LCD panel becomes larger, the load resistance R _OUT and the load capacitance C _OUT become larger, and if the fixed period itself becomes double speed or higher due to double speed drive, it is difficult to realize with the conventional drive method. Become. In this embodiment, even if the time constant elements of R _OUT and C _OUT become large, as shown in the equation (3), the boost voltage increase ΔV is adjusted and the constant a is set small, so that the liquid crystal panel It is possible to achieve faster convergence in a shorter time exceeding the time constant constraint.

  In short, the drive voltage control apparatus of the present embodiment has an operational amplifier (buffer) A1 that supplies a load drive voltage obtained by impedance conversion of an input signal to the load circuit 2, and an input voltage to the operational amplifier A1 at the initial stage of voltage change. This is provided with an input level control unit 2 that performs control to switch to the higher target drive voltage VH after giving a boost voltage (VH + ΔV) higher than the higher target drive voltage VH for a certain period. In the impedance conversion, the output impedance is changed with respect to the input impedance to reduce the output impedance, thereby reducing the power consumption.

According to the present embodiment, in the drive voltage control device for driving the liquid crystal panel, the load is driven at a high speed at a speed corresponding to a time shorter than the time constant τ determined by the load (C _OUT × R _OUT ) of the liquid crystal panel. be able to.

  As shown in FIG. 3, impedance conversion may be performed by a source follower circuit A1 ′ or the like instead of the operational amplifier A1. In this case, a voltage that is always higher than the input voltage by VT (threshold voltage) is applied to the input in advance.

(Embodiment 2)
FIG. 4 is a circuit diagram showing a configuration of a drive voltage control device for a liquid crystal panel according to Embodiment 2 of the present invention. An input signal is applied to the non-inverting input terminal (+) of the operational amplifier A1. A load circuit 2 of a liquid crystal panel comprising a load resistor R _OUT and a load capacitor C _OUT is connected to the output terminal of the operational amplifier A1. VGG is a boost voltage having a potential higher than the power supply voltage VDD of the operational amplifier A1. The output terminal of the operational amplifier A1 is connected to the power supply of the boost voltage VGG via the boost control switch Su. The timing control unit 3 performs on / off control of the boost control switch Su by a control signal TP.

  This is shown in FIGS. 5 (b) and 5 (c). FIG. 5A shows the load driving voltage in the case of the conventional technique.

At the initial stage of the voltage change due to the operation of the drive voltage control device, the timing control unit 3 controls the boost control switch Su to be turned on by the control signal TP and applies the boost voltage VGG to the output terminal OUT for a predetermined period. The load drive voltage V _OUT starts to converge with the boost voltage VGG as a convergence target. When the load drive voltage V _OUT reaches a level equal to the higher target drive voltage VH, the timing control unit 3 inverts the control signal TP and sets the boost control switch Su. Turn off. As a result, the load drive voltage V _OUT converges to the higher target drive voltage VH. This convergence is performed at high speed at a speed corresponding to a time shorter than the time constant determined by the load (C _OUT × R _OUT ) of the liquid crystal panel, and the liquid crystal panel can be driven at high speed.

  In the present embodiment, the boost voltage VGG is substituted for (VH + ΔV) in the expression (3) of the first embodiment, and the ON time of the boost control switch Su is 1 / (unity gain frequency of the operational amplifier A1. ), But shorter than the convergence time τs.

When the load resistance R _OUT and the load capacitance C _{OUT of} the liquid crystal panel can be accurately estimated in advance and the convergence time τs can be defined, the constants are determined so that the expression (3) is satisfied. It is possible to freely adjust the speed at which the load drive voltage is raised without depending on the load and without the restriction of the time constant.

(Modification Mode 1)
In the above description, the boost voltage VGG is higher than the power supply voltage VDD of the operational amplifier A1, but it is assumed here that the boost voltage VGG is lower than the power supply voltage VDD of the operational amplifier A1. In this case, low power consumption can be achieved in addition to high-speed driving. This will be described with reference to FIG.

The power related to charging / discharging can be calculated from the amount of charge transferred to the load capacitance C _OUT . Considering this power, assuming that the initial value of the load drive voltage change is 0 V and the convergence voltage is the higher target drive voltage VH. When only the operational amplifier A1 is charged, the charge amount ΔQ has a convergence time τs,
ΔQ = I _OUT × τs (7)
It becomes. I _OUT is the output current of the operational amplifier A1. Here, when the power supply voltage of the operational amplifier A1 is VDD, the charge / discharge power P1 is
P1 = VDD × I _OUT (8)
It becomes.

  Next, consider a case where the boost voltage VGG is applied to the output terminal OUT for a predetermined period t1.

Now, let I _GG be the current that flows from the boost voltage VGG to the output.

ΔQ = I _GG × t1 + I _OUT (τs−t1) (9)
And the charge / discharge power P1 is
P1 = I _GG × VGG × t1 / τs + I _OUT × VDD × (τs−t1) / τs (10)
It can be expressed as.

  This indicates that the power consumption can be reduced by the proportional relationship between the ON time t1 of the boost voltage VGG and the ratio of the power supply voltage VDD and the boost voltage VGG of the operational amplifier A1.

  On the other hand, as already described, when the boost voltage VGG is higher than the power supply voltage VDD of the operational amplifier A1, the boost voltage VGG can be set higher, and the speed can be further increased.

(Modification Mode 2)
FIG. 7 relates to the modification 2 and is a combination of the configuration of the first embodiment shown in FIG. 1 and the configuration of the second embodiment shown in FIG. An input level control unit 1, a boost control switch Su, and a timing control unit 3 are provided.

  In the case of the first embodiment, by controlling the input level by the input level control unit 1, it is possible to converge at a high speed at a speed corresponding to a time shorter than the time constant of the load circuit 2 of the liquid crystal panel. However, in practice, it is necessary to increase the internal slew rate of the operational amplifier A1. That is, it is necessary to prepare as a high-speed operational amplifier, and there are some parts that are difficult to realize. In the case of the second embodiment shown in FIG. 4, the boost voltage VGG is applied via the boost control switch Su, so that it is converged at high speed regardless of the internal slew rate of the operational amplifier A1. On the other hand, when the boost control switch Su is turned off to switch to the output of the operational amplifier A1, switching noise occurs. Therefore, in the configuration of FIG. 7, first, when the boost control switch Su is turned on and converges to the vicinity of the higher target drive voltage VH, the output is switched to the output of the operational amplifier A1, and further, the input level control unit 1 performs liquid crystal display. A voltage corresponding to the charge / discharge charge to the load circuit 2 of the panel is added and input to the operational amplifier A1. As a result, it is possible to reduce the waveform distortion and overshoot and secure a smooth converged waveform, while achieving high speed.

(Embodiment 3)
FIG. 8 is a circuit diagram showing a configuration of a drive voltage control device for a liquid crystal panel according to Embodiment 3 of the present invention. In addition, the same code | symbol is attached | subjected about the same thing as the component mentioned above.

A target drive voltage VH on the higher DC side of the input signal determined according to the pixel data of the liquid crystal display with respect to the non-inverting input terminal (+) of the operational amplifier A1, and a boost voltage VHH higher than the target drive voltage VH on the higher side. Are selectively input via the input selection switch Si. A smoothing capacitor CC is inserted between the output terminal of the operational amplifier A1 and the ground, and an output control switch So is inserted between the smoothing capacitor CC and the load circuit 2 of the liquid crystal panel. The boost voltage VHH is higher than the target drive voltage VH on the higher side, and the difference ΔVHH = (VHH−VH) corresponds to the voltage corresponding to the charge charged to the smoothing capacitor CC, and the load capacitance C _{OUT of the} smoothing capacitor CC and the liquid crystal panel. Determined by the ratio of The timing control unit 3 performs on / off control of the input selection switch Si by the control signal TIN, and performs on / off control of the output control switch So by the control signal TON. The output control switch So is controlled based on the liquid crystal display timing.

In the OFF state of the output control switch So, the timing control unit 3 controls the input selection switch Si by the control signal TIN to select the boost voltage VHH, and charges the smoothing capacitor CC with the boost voltage VHH. Next, the output control switch So is turned on, and the boost voltage VHH of the smoothing capacitor CC is applied to the load circuit 2 of the liquid crystal panel. As a result, the load drive voltage V _OUT increases. The rise of the load drive voltage V _OUT at this time is high-speed target drive voltage VH at a high speed at a speed corresponding to a time shorter than the time constant determined by the load resistance R _OUT and the load capacitance C _OUT of the load circuit 2 of the liquid crystal panel. It will converge to the level of. The timing control unit 3 switches the input selection switch Si when the load drive voltage V _OUT reaches the level of the higher target drive voltage VH, and selects the higher target drive voltage VH as an input of the operational amplifier A1. If the internal slew rate of the operational amplifier A1 is set sufficiently high, when the target drive voltage VH on the higher side changes according to the pixel data, the load drive voltage V _OUT is the load resistance R _OUT and the load capacitance C _{OUT of the} liquid crystal panel. It will converge with the time constant of.

Here, it is assumed that the high-level target drive voltage _{VH_t0} = 2V is output at a certain time, and the high-level target drive voltage _{VH_t1} = 5V is output at the next timing of the liquid crystal display cycle. Further, it is assumed that the load capacitance C _OUT of the liquid crystal panel is 100 nF, the load resistance R _{OUT is} 100Ω, and the smoothing capacitor CC is 1 μF. _Assuming that the slew rate of the operational amplifier A1 is sufficiently high, the convergence time τs in the case of convergence to 95% of the higher target drive voltage _{VH_t1} = 5.0V is expressed as: time constant τ = C _OUT × R _OUT
τs = 3τ = 3C _OUT × R _OUT = 30 μs (11)
Is required. Here, it is assumed that the liquid crystal panel is converged in 20 μs. In order to converge at 20 μs, it is necessary to be 2τ (τ = 10 μs). The boost voltage VHH that can be charged to 95% of the target drive voltage _{VH_t1} = 5.0V on the higher side with 2τ may be determined as follows.

ΔVHH = VHH−VH _{_t1} (12)
Then, from the charging equation,
_{ΔVHH = 0.95 (VH _t1 -VH _t0} ) / (1-exp (-2)) - (VH _t0 -VH _t0)
_{≒ 0.1 (VH _t1 -VH _t0)} = 0.3V ............... (13)
The boost voltage VHH is
_{VH_t1} + ΔVHH = 5.3V (14)
It becomes. By providing this voltage as a boost voltage VHH, the voltage difference between the target drive voltage VH _{_T0} boost voltage VHH and high side, the voltage _{0.95 (VH} _t1 -VH _t0) Since converge at 2.tau, the apparent Above, the output seems to require a convergence time τs of 2τ, which previously required 3τ. By performing such faster, fast speed corresponding to a time shorter than the time constant from the target drive voltage VH _{_T0} the high-level side with respect to the load resistance and the load capacitance of the liquid crystal panel to the target drive voltage VH _{_T1} the high side It is possible to converge to

Conversely, it is verified whether there is a problem with the charge conservation law of the load capacitance C _OUT and the smoothing capacitance CC of the liquid crystal panel. Expressing the transport of charges as a formula:
_{VHH = (VH _t1 -VH _t0)} × C OUT / CC + VH _t1 ............... (15)
If a voltage equal to or higher than is applied and the smoothing capacitor CC is charged from the operational amplifier A1, the charge conservation law is established.

In this case, the boost voltage VHH = 5.3V, and the even drive capability of the operational amplifier A1 is low, before switching the high side voltage from VH _{_T0} to VH _{_T1,} if an electric charge is charged in the smoothing capacitor can be converged It shows that. Furthermore, although this is speeding up, the operational amplifier A1 has only to store the charge in the smoothing capacitor using the entire period of the liquid crystal driving cycle, so that the capability of the operational amplifier A1 is lowered. Indicates that can be done. If the capacity of the operational amplifier A1 can be reduced, it becomes easy to provide a circuit having a small area, low power consumption, and excellent oscillation stability.

(Modification of Embodiment 3)
The higher target drive voltage VH, the lower target drive voltage VL, and the convergence time τs are determined by the material of the liquid crystal panel and the drive method. In a liquid crystal panel applied to a large, high-definition television receiver or the like, low-temperature polysilicon is used, and dot inversion driving is often used. In this case, although the voltage applied to the common electrode is constant, the positive and negative voltages are switched and driven with a period of about 2 μs to 5 μs based on the video data for each of the sources of the liquid crystal element. In the case of such driving, the technique of the present invention can be applied to driving to the source. In the small and medium-sized, OCB (Optically Compensated Birefringence) liquid crystal and TN (TwistedNematic) liquid crystal are often used for frame inversion driving, line inversion driving, and N line inversion driving. In this case, positive and negative voltages are driven with a period of 16 ms for frame inversion with a common voltage, and with a period of 30 to 50 μs with line inversion. Furthermore, the load capacity is on the order of nF to several hundreds of nF. When the technology of the present invention is applied when driving such a load at a high speed, AC drive can be performed at a high speed at a speed corresponding to a time shorter than the time constant. It becomes possible.

  In addition, in any driving system and panel material, the panel load may vary when there are manufacturing variations or manufacturing bases are different. Further, in addition to the panel load, a parasitic capacitance, a parasitic resistance, and a parasitic inductor are attached when the driving circuit and a circuit including the driving circuit are mounted. In addition, the panel load itself is actually a complex distributed constant model, and it is often difficult to accurately approximate it with a simple model of capacitance and resistance.

  Therefore, in the modified embodiment of the third embodiment, when the panel load is slightly different from the estimated value, when the panel and the apparatus including the same vary in manufacturing, as a result, the panel load varies, or even different panels or panel A configuration for automatically adjusting to an appropriate convergence time τs and power even when the load is different will be described.

In the third embodiment, automatic control is performed when the load drive voltage varies periodically from the result of the equation (15). That is, although the load capacitance C _OUT and the higher-side target drive voltage VH differ for each liquid crystal panel, the convergence time τs (2 μs in the above example) is made constant even when this parameter changes. Here, description will be made with reference to the flowchart of FIG. 9 and the waveform diagram of FIG.

  First, in step S1 of FIG. 9, each initial value is set based on the panel material and the driving method. If the fixed period for switching between positive and negative voltages with respect to the common electrode for line inversion driving is 50 μs, the convergence time τs of the driving circuit is 40 μs with a margin, and the high-side target driving voltage VH and the low-side target driving voltage VL. Suppose that it is required to drive at VH = 3V and VL = -3V based on the brightness and contrast of the liquid crystal panel.

  In step S1 to step S2, a driving circuit is connected to the liquid crystal panel, and the waveform is confirmed by alternately driving the high-side target driving voltage VH and the low-side target driving voltage VL. At this time, when the estimated load capacity and load resistance of the liquid crystal panel are accurate and the operational amplifier A1 can also be made according to the load, the convergence time τs reaches the intended 40 μs, as shown in FIG. Get the waveform. Step S3 for determining whether or not driving can be performed in time for the convergence time τs is YES, and NO for step S4 for determining whether the margin is too large for the convergence time τs. In this case, since there is no need for adjustment, automatic adjustment is not performed and the process is terminated. After that, it is only necessary to actually operate as it is.

  Next, when the estimated load capacity and load resistance of the liquid crystal panel are small and converge at a speed faster than expected, the capacity of the operational amplifier A1 has an excessive capacity with respect to the load. In this case, the determination in step S3 is YES, and the determination in step S4 is YES. In step S5, in order to adjust the excessive capacity, the bias current of the operational amplifier A1 is reduced to, for example, 3/4. In general, since the speed of the operational amplifier A1 is proportional to the square root of the current, the capacity is reduced by about 13.4% (since the square root of 3/4 is about 86.6%). The current consumption is roughly proportional to the bias current and can be reduced by 25%.

  After performing this adjustment, in step S2, the high-order target drive voltage VH and the low-order target drive voltage VL are alternately driven to check the waveform. As long as the margin of the convergence time τs is excessive, the bias current is reduced by a factor of 3/4 each time, and the process returns to step S2. The state of such adjustment is shown in the waveform of FIG.

  Thus, the counter electrode that satisfies the convergence time τs can be driven by suppressing the electric power by adjusting the capacity necessary for driving the panel load.

  Here, the control information of the bias current obtained by the automatic adjustment may be stored in the memory. Moreover, by setting this as an initial value as a register, when the corresponding panel is turned on and actually operated, it is suitably driven by giving an automatic adjustment value as an initial value from the beginning by controlling the bias current. be able to.

Next, when the estimated load capacity or load resistance of the liquid crystal panel is large and does not converge at a speed higher than expected, or when the target drive voltage VH on the higher side and the target drive voltage VL on the lower side are not reached. Then, the boost voltage VHH (= VH + ΔV) is generated and automatic adjustment is performed so as to be within the convergence time τs. In this case, the determination in step S3 is NO. Here, in order to improve the driving capability, the process proceeds to step S6, and the boost voltage increase ΔV is set to 50 mV. If the rise does not converge within the convergence time τs,
VH = VH + ΔV (16)
And If the trailing edge does not converge within the convergence time τs,
VL = VL−ΔV (17)
And Also, if neither rise nor fall converge within the convergence time τs,
VH = VH + ΔV, VL = VL−ΔV (18)
And

  Next, returning to the process of step S2, the process of step S6 is repeated until the convergence time τs is satisfied. This state is shown in FIG.

  By performing the automatic adjustment as described above, it is possible to control the drive voltage control device without re-adjusting it as a semiconductor device and re-manufacturing it. Even so, it is possible to provide a drive voltage control device that satisfies the convergence time τs and has an appropriate current consumption.

  The explanation has been made on the assumption that the internal slew rate of the operational amplifier A1 is sufficiently larger than the external slew rate. However, in addition to the adjustment of the boost voltage increase ΔV in step S6, the bias current of the operational amplifier A1 is changed. By adding processing such as 1.5 times, automatic adjustment including the internal slew rate of the operational amplifier A1 can be performed.

  Further, a case where the load drive voltage can be converged to the target drive voltage within the required convergence time τs regardless of the load circuit will be described.

  FIG. 11 is a circuit diagram showing a configuration of a drive voltage control device for a liquid crystal panel that can converge the load drive voltage to the target drive voltage during the requested convergence time τs, without using the load circuit according to the third embodiment of the present invention. is there. In addition, the same code | symbol is attached | subjected about the same thing as the component mentioned above. In FIG. 11, 5 is a comparator that compares the load drive voltage with the target drive voltage, 6 operates according to the comparison result of the comparator 5, and when the load drive voltage is higher than the target drive voltage, the boost voltage VHH is stepped down. If the load drive voltage is equal to the target drive voltage, the boost voltage VHH is not changed. When the load drive voltage is lower than the target drive voltage, the boost voltage control unit boosts the boost voltage VHH. In the illustrated example, the boost voltage control unit 6 includes an arithmetic circuit 7 and a DA converter 8. The boost voltage control unit 6 is controlled by the timing control unit 3 at a predetermined timing. That is, the timing of the arithmetic circuit 7 and the DA converter 8 is controlled. The arithmetic circuit 7 actually calculates the boost voltage increase ΔV, and the DA converter 8 converts this into an analog control signal, and adjusts the boost voltage increase ΔV in the boost voltage VHH.

  A control operation for converging the load drive voltage to the target drive voltage in the required convergence time τs will be described.

  If only the operational amplifier A1 is driven, the load drive voltage is determined by the slew rate of the operational amplifier A1 and the required convergence time τs. At this time, if the capacity and resistance of the load circuit 2 are sufficiently smaller than the internal slew rate of the operational amplifier A1, and the slew rate of the operational amplifier A1 is sufficiently high, the load drive voltage can be output in the required convergence time τs. However, when the capacity and resistance of the load circuit 2 are large and the load is heavy, the load circuit 2 is limited by its time constant and does not converge to the target drive voltage within the convergence time τs. Conversely, when the boost voltage VHH is selected as the input voltage, if the boost voltage VHH is too high, the load drive voltage overshoots and does not converge. Further, the load of the load circuit 2 is not always constant due to the change of the liquid crystal panel and the manufacturing variation.

  Therefore, when the load circuit 2 or its time constant fluctuates, the amount of change is detected and the optimum boost voltage VHH is applied, thereby realizing control for reliably converging to the target drive voltage within the required convergence time τs. For this purpose, a comparator 5 and a boost voltage controller 6 are provided.

  Now, when the load drive voltage is 0V and the required convergence time τs has elapsed, the comparator 5 compares the load drive voltage with the target drive voltage, and the arithmetic circuit 7 performs the following calculation.

  (A) When the load drive voltage is equal to the target drive voltage, the boost voltage VHH is not changed.

  (B) When the load drive voltage is higher than the target drive voltage, the boost voltage VHH is changed to a voltage having a smaller absolute value than the original boost voltage VHH.

  (C) When the load drive voltage is lower than the target drive voltage, the boost voltage VHH is changed to a voltage having a larger absolute value than the original boost voltage VHH.

  By repeating this, even if the liquid crystal panel is changed or the liquid crystal panel varies, the target drive voltage can be output during the required convergence time τs. In the above description, the load drive voltage being equal to the target drive voltage means that the load drive voltage only needs to fall within an error range (for example, a range of target drive voltage ± 10 mV).

  As described above, even when the liquid crystal panel changes or the load varies, the load drive voltage can be reliably converged to the target drive voltage within the required convergence time τs.

  If the panel load and the convergence time τs are equal, the boost voltage VHH and the bias current may be the same. Therefore, the processing in the comparator 5 does not need to be changed unless the panel load and the convergence time τs are changed. Therefore, after setting the panel load and the convergence time τs and converging to the optimum boost voltage for a certain time, the value of the optimum boost voltage VHH can be transmitted to and stored in the control register. The device 5 may not operate. By setting the boost voltage VHH in the test before the actual transfer and display of images to the liquid crystal panel, the convergence time τs can be set freely with low power consumption, regardless of the panel load, without increasing power during display. It becomes possible to do.

(Embodiment 4)
FIG. 12 is a circuit diagram showing a configuration of a drive voltage control device for a liquid crystal panel according to Embodiment 4 of the present invention. In addition, the same code | symbol is attached | subjected about the same thing as the component mentioned above.

  In FIG. 12, A1 is a first operational amplifier that inputs a high-side target drive voltage VH, converts the impedance, and outputs a load drive voltage V1, and A2 is a boost voltage VHH having a higher potential than the high-side target drive voltage VH. Is input to perform impedance conversion and output a boot drive voltage V2 higher than the load drive voltage V1. Ss is an output selection switch for selecting the load drive voltage V1 of the first operational amplifier A1 and the boot drive voltage V2 of the second operational amplifier A2. CC is a smoothing capacitor inserted between the output selection switch Ss and the ground. , So is an output control switch interposed between the smoothing capacitor CC and the load circuit 2 of the liquid crystal panel, and 3 is a timing control unit. The timing control unit 3 performs on / off control of the output selection switch Ss by the control signal TS, and performs on / off control of the output control switch So by the control signal TON. The timing control unit 3 also has a function of controlling the operation and operation stop of the operational amplifier A1 and the second operational amplifier A2 by the control signals TH and THH.

  The timing control unit 3 selects the boost voltage VHH of the second operational amplifier A2 by controlling the output selection switch Ss by the control signal TS in the off state of the output control switch So, and the smoothing capacitor CC is selected by the boost voltage VHH. Charge. At this time, the first operational amplifier A1 in the non-selected state is powered off by the control signal TH to achieve low power consumption.

Next, the timing control unit 3 turns on the output control switch So by the control signal TON according to the display timing, and applies the boost voltage VHH of the smoothing capacitor CC to the load circuit 2 of the liquid crystal panel. As a result, the load drive voltage V _OUT increases. The rise of the load drive voltage V _OUT at this time is high-speed target drive voltage VH at a high speed at a speed corresponding to a time shorter than the time constant determined by the load resistance R _OUT and the load capacitance C _OUT of the load circuit 2 of the liquid crystal panel. It will converge to the level of. When the load drive voltage V _OUT reaches the level of the higher target drive voltage VH, the output selection switch Ss is switched to select the load drive voltage V1 of the first operational amplifier A1. At this time, the second operational amplifier A2 in the non-selected state is powered off by the control signal THH to achieve low power consumption. If the internal slew rate of the first operational amplifier A1 is set sufficiently high, the load drive voltage V _OUT is equal to the load resistance R _OUT of the liquid crystal panel and the load when the high-side target drive voltage VH changes according to the pixel data. It converges with a time constant due to the capacitance C _OUT .

  According to the present embodiment, it is possible to increase the speed without depending on the internal slew rate of the operational amplifier A1. Furthermore, in the non-selected state, the first operational amplifier A1 and the second operational amplifier A2 can be powered off to achieve low power consumption.

(Embodiment 5)
FIG. 13 is a circuit diagram showing a configuration of a drive voltage control device for a liquid crystal panel according to Embodiment 5 of the present invention. In addition, the same code | symbol is attached | subjected about the same thing as the component mentioned above.

  This embodiment corresponds to a configuration in which the output selection switch Ss is omitted in FIG. 12 in the case of the fourth embodiment. In a period in which the boot drive voltage V2 of the second operational amplifier A2 is selected, the timing control unit 3 sets the operational amplifier A1 in a high impedance state by the control signal TH, and conversely, the load drive voltage V1 of the first operational amplifier A1. In the period when is selected, the timing control unit 3 puts the second operational amplifier A2 in a high impedance state by the control signal THH.

  According to the present embodiment, the output selection switch Ss between the first operational amplifier A1 and the second operational amplifier A2 and the smoothing capacitor CC becomes unnecessary. Since the output impedance can be reduced, the operation can be further speeded up. In addition, a voltage free from noise at the time of switching can be obtained.

(Embodiment 6)
FIG. 14 is a circuit diagram showing a configuration of a drive voltage control device for a liquid crystal panel according to Embodiment 6 of the present invention. In addition, the same code | symbol is attached | subjected about the same thing as the component mentioned above.

  The load circuit 2 of the liquid crystal panel is connected to the output terminal of the operational amplifier A1 via the timing control switch St and the output control switch So. The connection point between the timing control switch St and the output control switch So is connected to the power supply of the boost voltage VGG having a higher potential than the target drive voltage VH on the higher side via the boost control switch Su. A smoothing capacitor CC is inserted between the connection point of the timing control switch St and the output control switch So and the ground. The timing control unit 3 performs on / off control of the output control switch So by the control signal TON, performs on / off control of the boost control switch Su by the control signal TP, and turns on / off the timing control switch St by the control signal TOP. It comes to perform control. The output control switch So is controlled based on the liquid crystal display timing.

The timing control unit 3 controls the boost control switch Su to be turned on by the control signal TP when the output control switch So is in the off state, and charges the smoothing capacitor CC with the boost voltage VGG. Next, the boost control switch Su is controlled to be turned off. Then, the output control switch So is turned on according to the display timing, and the boost voltage VGG of the smoothing capacitor CC is applied to the load circuit 2 of the liquid crystal panel. As a result, the load drive voltage V _OUT increases. The rise of the load drive voltage V _OUT at this time is high-speed target drive voltage VH at a high speed at a speed corresponding to a time shorter than the time constant determined by the load resistance R _OUT and the load capacitance C _OUT of the load circuit 2 of the liquid crystal panel. It will converge to the level of. When the load drive voltage V _OUT reaches the level of the higher target drive voltage VH, the timing control switch St is turned on by the control signal TOP, and the output V1 of the operational amplifier A1 by the higher target drive voltage VH is selected.

  According to the present embodiment, the charge for charging the load circuit 2 of the liquid crystal panel is stored in advance in the smoothing capacitor CC, so that the operation speed can be increased.

  As a modification, as shown in FIG. 15, the timing control switch St may be omitted, and the output of the operational amplifier A1 may be set to high impedance by the control signal TH from the timing control unit 3. Furthermore, the operational amplifier A1 may be powered off to reduce power consumption.

(Embodiment 7)
FIG. 16 is a circuit diagram showing a configuration of a drive voltage control device for a liquid crystal panel in the seventh embodiment of the present invention. In addition, the same code | symbol is attached | subjected about the same thing as the component mentioned above.

  A feedback control switch Sf is inserted in a feedback line between the output terminal and the inverting input terminal (−) of the operational amplifier A1, and this feedback control switch Sf is on / off controlled by a control signal TCO of the timing control unit 3. It is like that. A smoothing capacitor CC is inserted between the output terminal of the operational amplifier A1 and the ground, and an output control switch So is inserted between the smoothing capacitor CC and the load circuit 2 of the liquid crystal panel. The output control switch So is also controlled to be turned on / off by a control signal TON from the timing control unit 3.

  The operational amplifier A1 operates as a voltage follower when the feedback control switch Sf is turned on and the inverting input terminal (−) is short-circuited to the output terminal, and operates as a comparator when it is turned off and the inverting input terminal (−) is short-circuited to the ground. Operate. When operating as a comparator, the operational amplifier A1 outputs an H level (power supply voltage VDD).

  The timing controller 3 turns off the feedback control switch Sf for a predetermined period by the control signal TCO when the output control switch So is in the off state. As a result, the inverting input terminal (−) of the operational amplifier A1 is short-circuited to the ground, and the operational amplifier A1 operates as a comparator and outputs an H level (power supply voltage VDD). As a result, the smoothing capacitor CC is charged with the power supply voltage VDD.

Then, when the timing control unit 3 turns on the output control switch So by the control signal TON according to the display timing, the smoothing capacitor CC charges the load circuit 2 of the liquid crystal panel with the power supply voltage VDD. This charging is fast. When the load drive voltage V _OUT becomes substantially equal to the convergence target voltage in the load circuit 2 of the liquid crystal panel, the feedback control switch Sf is switched on, and the output terminal and the inverting input terminal (−) of the operational amplifier A1 are short-circuited. When the operational amplifier A1 operates as a voltage follower, the load drive voltage output from the operational amplifier A1 converges to the higher-side target drive voltage VH determined according to the pixel data.

  At this time, the smoothing capacitor CC is charged in advance at a power supply voltage level higher than the convergence target voltage, and further, the load circuit 2 of the liquid crystal panel is charged from the smoothing capacitor CC. Can be converged at a high speed at a speed corresponding to a time shorter than the time constant of the load circuit 2.

(Embodiment 8)
FIG. 17 is a circuit diagram showing a configuration of a drive voltage control device for a liquid crystal panel according to Embodiment 8 of the present invention. In addition, the same code | symbol is attached | subjected about the same thing as the component mentioned above.

  A comparator CM1 is provided separately from the operational amplifier A1. The smoothing capacitor CC is connected to the output terminal of the operational amplifier A1, and the load circuit 2 of the liquid crystal panel is connected via the output control switch So. A connection point between the output control switch So and the load circuit 2 is connected to the power supply voltage VDD via the boost control switch Su. The step-up control switch Su is controlled to be turned on / off by the output of the comparator CM1. The non-inverting input terminal (+) of the comparator CM1 is connected to a connection point between the output control switch So and the load circuit 2, and a predetermined reference voltage (VH−ΔV) is applied to the inverting input terminal (−). .

  The smoothing capacitor CC is charged by the load drive voltage output from the operational amplifier A1. This is a voltage corresponding to the higher target drive voltage VH corresponding to the pixel data input to the operational amplifier A1. The timing control unit 3 turns on the output control switch So by the control signal TON. At this time, the voltage applied to the non-inverting input terminal (+) of the comparator CM1 is relatively low and the comparator CM1 outputs “L” level, so that the boost control switch Su is turned on. It has become. As a result, the higher power supply voltage VDD is applied to the load circuit 2 via the boost control switch Su and further applied to the smoothing capacitor CC via the output control switch So, and the smoothing capacitor CC is charged with the power supply voltage VDD. . The comparator CM1 compares the voltage applied to the load circuit 2 with a reference voltage. When the voltage applied to the load circuit 2 reaches the reference voltage as the charging of the smoothing capacitor CC proceeds, the comparator CM1 outputs an “H” level, and the boost control switch Su is turned off. The output control switch So remains in the on state, and the higher target drive voltage VH corresponding to the pixel data input to the operational amplifier A1 is reflected in the load circuit 2.

  According to the present embodiment, it is possible to speed up the effective operation of the load circuit 2 of the liquid crystal panel by applying the higher power supply voltage VDD to the smoothing capacitor CC.

  The operation of the operational amplifier A1 may be stopped during the operation period of the comparator CM1, and conversely, the operation of the comparator CM1 may be stopped during the operation period of the operational amplifier A1. Electricity can also be achieved.

(Embodiment 9)
FIG. 18 is a circuit diagram showing a configuration of a drive voltage control device for a liquid crystal panel according to Embodiment 9 of the present invention. In the present embodiment, a load driving voltage for driving the load circuit 2 of the liquid crystal panel in an alternating manner is generated. This is a power supply voltage for driving the counter electrode necessary for the line inversion of the liquid crystal panel, and a positive potential (for example, +3 V) and a negative potential (for example, -3 V) suitable for driving the liquid crystal panel. It outputs alternately.

  The high-side target drive voltage VH on the positive side and the boost voltage VHH on the positive side higher than the high-side target drive voltage VH via the input selection switch SHi with respect to the non-inverting input terminal (+) of the positive-side operational amplifier A1. Are selectively input. The difference between the boost voltage VHH on the positive side and the target drive voltage VH on the higher side is calculated according to the equation (1). The inverting input terminal (−) of the positive operational amplifier A1 is connected to the output terminal. A smoothing capacitor CC1 is connected to the output terminal of the positive operational amplifier A1.

  Also, the negative input side low-side target drive voltage VL and the negative input side lower-side target drive voltage VL are connected to the non-inverting input terminal (+) of the negative-side operational amplifier A3 via the input selection switch SLi. The boost voltage VLL is selectively inputted. The difference between the target drive voltage VL on the lower input side and the boost voltage VLL on the negative side is calculated according to the equation (1). The inverting input terminal (−) of the negative operational amplifier A3 is connected to the output terminal. A smoothing capacitor CC2 is connected to the output terminal of the operational amplifier A3 on the negative electrode side.

  The output terminal of the positive operational amplifier A1 and the output terminal of the negative operational amplifier A3 are selectively connected to the load circuit 2 of the liquid crystal panel via the output changeover switch Sx. The timing control unit 3 performs switching control of the output selector switch Sx by the control signal SEL in accordance with the display timing. Further, the timing control unit 3 controls the timing of the input selection switch SHi and the input selection switch SLi.

  Next, the operation of the drive voltage control apparatus of the present embodiment configured as described above will be described.

  (I) In a period in which the output selector switch Sx selects the output of the negative-side operational amplifier A3, the positive-side input selection switch SHi selects the higher positive-side boost voltage VHH and the positive-side operational amplifier A1. To enter. As a result, the positive-side smoothing capacitor CC1 is charged with the higher positive-side boost voltage VHH. At this time, the input selector switch SLi on the negative side selects the normal target drive voltage VL on the lower side of the input and inputs it to the operational amplifier A3 on the negative side. Since the output terminal of the operational amplifier A3 on the negative side is connected to the load circuit 2 of the liquid crystal panel by the output changeover switch Sx, the load circuit 2 is driven by the target drive voltage VL on the negative input DC low side.

  (Ii) In a period in which the output selector switch Sx selects the output of the positive operational amplifier A1, the negative input selection switch SLi selects the lower negative boost voltage VLL and the negative operational amplifier A3. To enter. As a result, the negative-side smoothing capacitor CC2 is charged with the lower negative-side boost voltage VLL. At this time, the input selector switch SHi on the positive side selects the normal higher target drive voltage VH and inputs it to the operational amplifier A1 on the positive side. Since the output terminal of the operational amplifier A1 on the positive electrode side is connected to the load circuit 2 of the liquid crystal panel by the output changeover switch Sx, the load circuit 2 is driven with the target drive voltage VH on the positive input DC high side.

  And the timing control part 3 switches the state of said (i) and the state of (ii) alternately with the output switch Sx.

When switching from (i) to (ii), the smoothing capacitor CC1 has already been charged with the higher positive-side boost voltage VHH, so the load drive voltage _VOUT for the load circuit 2 converges at high speed. Convergence to voltage. Similarly, when switching from (ii) to (i), the smoothing capacitor CC2 has already been charged with the lower negative boost voltage VLL, so that the load drive voltage V _OUT for the load circuit 2 is high-speed. Converges to the convergence target voltage.

  The above operation is cyclically repeated to obtain an output waveform as shown in FIG.

According to the present embodiment, in the drive voltage control device for driving the liquid crystal panel, the load is driven at a high speed at a speed corresponding to a time shorter than the time constant determined by the load (C _OUT × R _OUT ) of the liquid crystal panel. Can do.

(Embodiment 10)
FIG. 19 is a circuit diagram showing a configuration of a drive voltage control device for a liquid crystal panel according to Embodiment 10 of the present invention. In addition, the same code | symbol is attached | subjected about the same thing as the component mentioned above.

  A smoothing capacitor CC1 on the positive side is inserted between the output terminal of the operational amplifier A1 on the positive side and the ground. The power supply of the boost voltage VGG on the positive side higher than the target drive voltage VH on the high side on the positive side is connected to the output terminal of the operational amplifier A1 on the positive side via the boost control switch TR1 on the positive side. A smoothing capacitor CC2 on the negative electrode side is inserted between the output terminal of the operational amplifier A3 on the negative electrode side and the ground. The power supply of the boost voltage VNN on the negative side lower than the target drive voltage VL on the lower side of the input signal on the negative side is connected to the output terminal of the operational amplifier A3 on the negative side via the boost control switch TR2 on the negative side. Yes. The output of the positive operational amplifier A1 and the output of the negative operational amplifier A3 are connected to the load circuit 2 via the output changeover switch Sx. The timing control unit 3 alternately switches the output changeover switch Sx at a predetermined timing. In addition, timing control is performed on the positive side boost control switch TR1 and the negative side boost control switch TR2. When the output selector switch Sx selects the output of the operational amplifier A1 on the positive side, the boost control switch TR2 on the negative side is turned on, and when the output switch Sx selects the output of the operational amplifier A3 on the negative side, The boost control switch TR1 is turned on.

  (I) In a period in which the output changeover switch Sx selects the output of the negative-side operational amplifier A3 under the control of the timing control unit 3, at this time, the negative-side boost to the negative-side smoothing capacitor CC2 is already performed on the negative-side. Charging with the voltage VNN is complete, and the negative-side operational amplifier A3 inputs the negative-side input signal to the load circuit 2 in a stable voltage state. When the positive-side boost control switch TR1 is turned on, charging of the positive-side smoothing capacitor CC1 is started with the higher positive-side boost voltage VGG.

  (Ii) In a period in which the output changeover switch Sx selects the output of the positive operational amplifier A1 under the control of the timing control unit 3, at this time, the positive boost to the smoothing capacitor CC1 on the positive side is already performed on the positive side. Charging with the voltage VGG is completed, and the positive operational amplifier A1 inputs the positive input signal to the load circuit 2 in a stable voltage state. Then, when the boost control switch TR2 on the negative electrode side is turned on, charging of the smoothing capacitor CC2 on the negative electrode side is started with the boost voltage VNN on the lower negative electrode side.

  And the timing control part 3 switches the state of said (i) and the state of (ii) alternately with the output switch Sx.

  When switching from (i) to (ii), since the positive-side smoothing capacitor CC1 has already been charged with the positive-side boost voltage VGG, the load drive voltage for the load circuit 2 is rapidly converged to the target voltage. Converge to. Similarly, when switching from (ii) to (i), the negative-side smoothing capacitor CC2 has already been charged with the negative-side boost voltage VNN, so the load drive voltage for the load circuit 2 is high-speed. It converges to the convergence target voltage. The above operation is cyclically repeated to obtain a voltage waveform for driving the load in an alternating manner. Also in this case, it is possible to drive the load at a high speed at a speed corresponding to a time shorter than the time constant determined by the load of the liquid crystal panel.

(Embodiment 11)
FIG. 20 is a circuit diagram showing a configuration of a drive voltage control apparatus for a liquid crystal panel according to Embodiment 11 of the present invention. In addition, the same code | symbol is attached | subjected about the same thing as the component mentioned above.

  A smoothing capacitor CC1 on the positive side is inserted between the output terminal of the operational amplifier A1 on the positive side and the ground. Also, a negative-side smoothing capacitor CC2 is inserted between the output terminal of the negative-side operational amplifier A3 and the ground. The output of the positive operational amplifier A1 and the output of the negative operational amplifier A3 are connected to the load circuit 2 via the output changeover switch Sx. The timing controller 3 controls the timing of the output selector switch Sx.

  The connection point between the output changeover switch Sx and the load circuit 2 is connected to the power source of the positive boost voltage VGG higher than the positive target drive voltage VH via the positive boost control switch Su. At the same time, it is connected to the power source of the negative boost voltage VNN lower than the lower target drive voltage VL of the negative input signal via the negative boost control switch Sd.

  Further, the potential of the smoothing capacitor CC1 on the positive electrode side is monitored, and when the voltage is lower than a predetermined reference voltage, the positive voltage boost control switch Su is controlled to be in an ON state, and when the voltage exceeds the reference voltage, the positive voltage boost control switch A positive-side comparator CM1 for controlling Su to an off state is provided. Further, the potential of the smoothing capacitor CC2 on the negative electrode side is monitored, and when the reference voltage exceeds a predetermined reference voltage, the negative voltage step-up control switch Sd is controlled to be in an ON state, and when the voltage becomes equal to or lower than the reference voltage, the negative voltage boost control switch is controlled. A negative-side comparator CM2 that controls Sd to an off state is provided.

  Next, the operation of the drive voltage control apparatus of the present embodiment configured as described above will be described.

  (I) In a period in which the timing control unit 3 controls the output selector switch Sx to select the output of the positive operational amplifier A1, the positive boost control switch Su is in the ON state, and the output selector switch Sx The boost voltage VGG on the positive electrode side is applied to the smoothing capacitor CC1 on the positive electrode side, and charging of the smoothing capacitor CC1 with the boost voltage VGG on the positive electrode side is started. The charging voltage of the smoothing capacitor CC1 is applied to the load circuit 2. The voltage applied to the load circuit 2 is monitored by the positive comparator CM1, and when the voltage is less than a predetermined reference voltage, the positive voltage boost control switch Su is held in the on state, but when the voltage exceeds the reference voltage. The positive-side boost control switch Su is controlled to be in the OFF state. Thereafter, the smoothing capacitor CC1 is charged only with the normal high-order target drive voltage VH from the positive-side operational amplifier A1. The applied voltage to the load circuit 2 is also applied to the non-inverting input terminal (+) of the negative-side comparator CM2. However, the comparator CM2 outputs an “H” level and the negative-side boost control switch. Since Sd is held in the OFF state, there is no influence of the boost voltage VNN on the negative electrode side.

In this case, since the boost voltage VGG on the positive side is applied to the load circuit 2 in the initial stage when the power is turned on and when the output selector switch Sx is switched from the negative side to the positive side, the load drive voltage V _OUT for the load circuit 2 is high-speed. Converges to the convergence target voltage.

  (Ii) In the period in which the timing control unit 3 controls the output changeover switch Sx to select the output of the negative side operational amplifier A3, the negative side boost control switch Sd is in the ON state, and the output changeover switch Sx The negative boost voltage VNN is applied to the negative smoothing capacitor CC2, and charging of the smoothing capacitor CC2 with the negative boost voltage VNN is started. The charging voltage of the smoothing capacitor CC2 is applied to the load circuit 2. The voltage applied to the load circuit 2 is monitored by the negative-side comparator CM2, and when the voltage exceeds a predetermined reference voltage, the negative-side boost control switch Sd is held in the on state, but when the voltage becomes lower than the reference voltage. The negative side boost control switch Sd is controlled to be in an OFF state. Thereafter, the smoothing capacitor CC2 is charged only at the lower target drive voltage VL of the normal input signal from the negative operational amplifier A3. Note that the voltage applied to the load circuit 2 is also applied to the non-inverting input terminal (+) of the positive comparator CM1, but an “L” level is output from the comparator CM1 and the positive boost control switch. Since Su is held in the OFF state, there is no influence of the boost voltage VGG on the positive electrode side.

In this case, since the boost voltage VNN on the negative side is applied to the load circuit 2 in the initial stage when the power is turned on and when the output selector switch Sx is switched from the positive side to the negative side, the load drive voltage V _OUT for the load circuit 2 is high speed. Converges to the convergence target voltage.

  The timing controller 3 switches the state (i) and the state (ii) alternately by the output selector switch Sx.

  As described above, according to the present embodiment, in obtaining a voltage waveform for driving the load in an alternating current manner, a high speed is obtained at a speed corresponding to a time shorter than the time constant determined by the load of the liquid crystal panel on the positive electrode side or the negative electrode side. Further, the boost control switches Su and Sd are controlled by monitoring the applied voltage to the load circuit 2 with the positive comparator CM1 and the negative comparator CM2. The timing control becomes highly accurate.

  In relation to the above, there is a circuit configuration as shown in FIG. In this case, the boost function works regardless of the voltage of the smoothing capacitor CC1. This is because the operational amplifiers A1 and A3 only need to drive near the convergence voltage, and up to near the convergence voltage, it may be driven by the boost function, so that further increase in speed can be achieved. In addition, the configuration does not depend much on the capabilities of the operational amplifiers A1 and A3, and the design of the operational amplifiers A1 and A3 becomes easy.

(Embodiment 12)
FIG. 22 is a circuit diagram showing a configuration of a drive voltage control apparatus for a liquid crystal panel according to Embodiment 12 of the present invention. In addition, the same code | symbol is attached | subjected about the same thing as the component mentioned above.

  This embodiment corresponds to the eleventh embodiment of FIG. 20 in which the positive-side comparator CM1 and the negative-side comparator CM2 are changed to the dual-use type. The connection point between the output changeover switch Sx and the load circuit 2 is connected to the power source of the positive boost voltage VGG higher than the positive target drive voltage VH via the positive boost control switch Su. At the same time, it is connected to the power source of the negative boost voltage VNN lower than the lower target drive voltage VL of the negative input signal via the negative boost control switch Sd. This point is the same as in FIG. 17, except that the positive-side boost control switch Su and the negative-side boost control switch Sd are used as a common control target, and are dual-purpose type comparators CM for controlling them exclusively. Is provided. The non-inverting input terminal (+) of the comparator CM is connected to the output terminal of the output changeover switch Sx. Further, a positive reference potential and a negative reference potential are connected to the inverting input terminal (−) of the comparator CM via reference potential changeover switches Sh and Sg. The comparator CM compares the voltage applied to the load circuit 2 with the reference potential from one of the reference potential change-over switches Sg and Sh, and sets the positive side boost control switch Su and the negative side boost control switch Sd. On / off control in contradiction. The timing control unit 3 performs timing control on the output changeover switch Sx and the reference potential changeover switches Sh and Sg.

  Next, the operation of the drive voltage control apparatus of the present embodiment configured as described above will be described.

  (I) During the period in which the timing control unit 3 controls the output changeover switch Sx to select the output of the operational amplifier A1 on the positive electrode side, the timing control unit 3 turns on the reference potential changeover switch Sh at the same time. The changeover switch Sg is turned off. The positive side boost control switch Su is in the ON state, and the negative side boost control switch Sd is held in the OFF state. The positive boost voltage VGG is applied to the positive smoothing capacitor CC1 via the positive boost control switch Su and the output changeover switch Sx, and charging of the smoothing capacitor CC1 with the positive boost voltage VGG is started. Is done. The charging voltage of the smoothing capacitor CC1 is applied to the load circuit 2. The voltage applied to the load circuit 2 is monitored by the dual-purpose type comparator CM. When the voltage is less than a predetermined reference voltage, the positive-side boost control switch Su is held in the ON state, but when the voltage exceeds the reference voltage. The positive-side boost control switch Su is controlled to be in the OFF state. Thereafter, the smoothing capacitor CC1 is charged only with the normal high-order target drive voltage VH from the positive-side operational amplifier A1. Note that the negative side boost control switch Sd is held in the OFF state.

In this case, since the boost voltage VGG on the positive side is applied to the load circuit 2 in the initial stage when the power is turned on and when the output selector switch Sx is switched from the negative side to the positive side, the load drive voltage V _OUT for the load circuit 2 is high-speed. Converges to the convergence target voltage.

  (Ii) In a period in which the timing control unit 3 controls the output changeover switch Sx to select the output of the negative-side operational amplifier A3, the timing control unit 3 turns on the reference potential changeover switch Sg at the same time. The changeover switch Sh is turned off. The negative side boost control switch Sd is in the ON state, and the positive side boost control switch Su is held in the OFF state. The negative boost voltage VNN is applied to the negative smoothing capacitor CC2 via the negative boost control switch Sd and the output selector switch Sx, and charging of the smoothing capacitor CC2 with the negative boost voltage VNN is started. Is done. The charging voltage of the smoothing capacitor CC2 is applied to the load circuit 2. The voltage applied to the load circuit 2 is monitored by a dual-purpose type comparator CM. When the voltage exceeds a predetermined reference voltage, the negative-side boost control switch Sd is held in the on state, but when the voltage is lower than the reference voltage. The negative side boost control switch Sd is controlled to be in an OFF state. Thereafter, the smoothing capacitor CC2 is charged only at the lower target drive voltage VL of the normal input signal from the negative operational amplifier A3. Note that the positive-side boost control switch Su is held in the OFF state.

In this case, since the boost voltage VNN on the negative side is applied to the load circuit 2 in the initial stage when the power is turned on and when the output selector switch Sx is switched from the positive side to the negative side, the load drive voltage V _OUT for the load circuit 2 is high speed. Converges to the convergence target voltage.

  The timing controller 3 switches the state (i) and the state (ii) alternately by the output selector switch Sx.

  As described above, according to the present embodiment, in the same manner as described above, in obtaining a voltage waveform for driving the load with an alternating current, the time is shorter than the time constant determined by the load of the liquid crystal panel on the positive electrode side or the negative electrode side. It is possible to drive the load at a high speed at a corresponding speed, and in addition, in order to make the timing control highly accurate, the applied voltage to the load circuit 2 as a cause of the on / off control of the boost control switches Su and Sd Since the comparator CM that serves as both the positive electrode side and the negative electrode side is configured as a comparator for monitoring the above, the circuit configuration can be simplified.

  In relation to the above, there is a circuit configuration as shown in FIG. In this case, the boost function works regardless of the voltage of the smoothing capacitor CC1. This is because the operational amplifiers A1 and A3 only need to drive near the convergence voltage, and up to near the convergence voltage, it may be driven by the boost function, so that further increase in speed can be achieved. In addition, the configuration does not depend much on the capabilities of the operational amplifiers A1 and A3, and the design of the operational amplifiers A1 and A3 becomes easy.

(Embodiment 13)
FIG. 24 is a circuit diagram showing a configuration of a drive voltage control apparatus for a liquid crystal panel according to Embodiment 13 of the present invention. In addition, the same code | symbol is attached | subjected about the same thing as the component mentioned above.

  Instead of the boost control switch Su in FIG. 4 of the second embodiment, a low breakdown voltage transistor TR1 and a clamp element CL1 are used. A series circuit of a clamp element CL1 and a low breakdown voltage transistor TR1 is interposed between the boost voltage VGG and the output terminal of the operational amplifier A1, and the low voltage transistor TR1 is controlled to be turned on / off by the timing control unit 3. Yes.

  Now, it is assumed that the input signal VH = 3.0V and the boost voltage VGG = 10V. It is assumed that there is no clamp element CL1. At this time, a difference of 7 V is applied to the low breakdown voltage transistor TR1, and a breakdown voltage higher than this is required. In general, when the breakdown voltage of a transistor is increased, the gate oxide film is thickened and the threshold voltage VT is also increased, so that the on-resistance is higher than that of a transistor with a low breakdown voltage. When the on-resistance of the low breakdown voltage transistor TR1 increases, an IR drop occurs when a high voltage is applied, and the set level cannot be output. Further, if the gate oxide film is thick, the signal from the timing control unit 3 is delayed due to the capacitance, and the high-speed control becomes complicated. Therefore, the clamp element CL1 is inserted between the low breakdown voltage transistor TR1 and the boost voltage VGG. By using the low withstand voltage transistor TR1, the boost voltage VGG can be set high, and the speed can be further increased.

  Other configurations and operations are the same as those in the second embodiment, and thus description thereof is omitted. The configuration of the present embodiment can also be applied to the configurations of FIGS. 7, 14, 15, 17, 17, 19, 20, 21, 22, and 23.

(Embodiment 14)
FIG. 25 is a circuit diagram showing a configuration of a drive voltage control apparatus for a liquid crystal panel in the fourth embodiment of the present invention. In addition, the same code | symbol is attached | subjected about the same thing as the component mentioned above.

  In the present embodiment, a plurality of clamp elements are provided. That is, n clamp elements CL1... CLn are connected in series and are inserted between the boost voltage VGG and the low breakdown voltage transistor TR1. A clamp control switch Sc1... Scn for short-circuiting is connected in parallel to each of the clamp elements CL1... CLn, and the plurality of clamp control switches Sc1.

  The load on the liquid crystal panel varies in a range of about 1 nF to 100 nF depending on the material of the liquid crystal panel. It is difficult to handle this in the same circuit in terms of speed, drive circuit stability, and the like. In this embodiment, the switch control unit 4 controls the clamp control switches Sc1... Scn to adjust the number of effective clamp elements, thereby making the operational amplifier A1 common, and the above variation. It can correspond to.

  That is, in the case of a liquid crystal panel with a relatively small load, the number of switches to be turned on may be increased to reduce the number of effective clamp elements. Note that setting the boost voltage VGG lower may be combined.

Conversely, in the case of a liquid crystal panel with a large load, it is sufficient to reduce the number of switches that are turned on and increase the number of clamp elements that are effective. Since each clamp element has a clamp of about 0.7 V to 1.0 V, the number of clamp elements is calculated according to the difference between the load drive voltage V _OUT and the boost voltage VGG so that the low voltage transistor TR1 can be used. Then, the switch control unit 4 may be controlled based on this. Note that the boost voltage VGG may be set higher.

  According to the present embodiment, even a plurality of types of liquid crystal panels with different loads can be driven at a high speed at a speed corresponding to a time shorter than a time constant determined by each load.

  The configuration of the present embodiment can also be applied to the configurations of FIGS. 7, 14, 15, 17, 17, 19, 20, 21, 22, and 23.

(Embodiment 15)
FIG. 26 is a circuit diagram showing a configuration of a drive voltage control apparatus for a liquid crystal panel in accordance with the fifteenth embodiment of the present invention. In addition, the same code | symbol is attached | subjected about the same thing as the component mentioned above.

  This embodiment corresponds to a structure in which the boost control switch Su is replaced with the low breakdown voltage transistor TR1 and the clamp element CL1 in FIG. 14 of the sixth embodiment. In this case, it is possible to realize a high-speed operation by applying a high voltage while suppressing an IR drop when a high voltage is applied.

  FIG. 27 is a circuit diagram showing a configuration of a drive voltage control device for a liquid crystal panel in Modification 1 of Embodiment 15. In FIG. The timing control switch St in FIG. 26 is omitted, and instead, the operational amplifier A1 has a high impedance function. In this case, low impedance driving is possible.

  FIG. 28 is a circuit diagram showing a configuration of a drive voltage control device for a liquid crystal panel according to a second modification of the fifteenth embodiment. In place of the clamp element CL1 in FIG. 26, similarly to FIG. 25, n clamp elements CL1... CLn connected in series and clamp control switches Sc1... Scn for short-circuit connected in parallel to the clamp elements CL1. And a switch control unit 4 for controlling on / off of the clamp control switches Sc1... Scn. According to this, even a plurality of types of liquid crystal panels having different loads can be driven at a high speed at a speed corresponding to a time shorter than a time constant determined by each load.

  FIG. 29 is a circuit diagram showing a configuration of a drive voltage control device for a liquid crystal panel according to a third modification of the fifteenth embodiment. The timing control switch St in FIG. 26 is omitted, and instead, not only can the operational amplifier A1 have a high-impedance function to lower its output but also have a power-off function to achieve low power consumption. It is.

FIG. 30 shows a specific example of the clamp element. 30A is a diode-connected Pch transistor, FIG. 30B is a diode-connected Nch transistor, FIG. 30C is a transistor biased in a saturation region, FIG. 30D is a diode, and FIG. ) Is resistance. When a plurality of clamp elements are connected in series, these may be used in combination. When the voltage difference between the boost voltage VGG and the load drive voltage _VOUT is large (1 V or more), it is desirable to combine transistors or diodes or to use them alone in order to securely clamp. Conversely, if the voltage difference is small, there is no problem with the resistance.

  The comparator is preferably configured using a hysteresis comparator for the purpose of stabilizing the comparison operation.

  In the above-described embodiment, the MOS transistor is used for explanation, but it goes without saying that a similar circuit can be configured using a bipolar transistor.

  Furthermore, the present invention is not limited to the above-described embodiments, and can be freely modified and changed within the scope described in the claims.

  The technology of the present invention is useful as a drive voltage control device for driving a liquid crystal panel at a high speed at a speed corresponding to a time shorter than a time constant determined by a load. In addition, it is useful as a drive voltage control device for driving a large-screen, high-definition liquid crystal panel with a small mounting area and low power consumption.

1 is a circuit diagram showing a configuration of a drive voltage control device for a liquid crystal panel in Embodiment 1 of the present invention. Waveform diagram showing the operation of the drive voltage control device for the liquid crystal panel in the first embodiment of the present invention The circuit diagram of the drive voltage control apparatus at the time of using a source follower circuit instead of an operational amplifier in the modification of Embodiment 1 of this invention The circuit diagram which shows the structure of the drive voltage control apparatus for liquid crystal panels in Embodiment 2 of this invention Waveform diagram showing the operation of the drive voltage control device for the liquid crystal panel in the second embodiment of the present invention The wave form diagram which shows operation | movement of the drive voltage control apparatus in the aspect 1 of the deformation | transformation of Embodiment 2 of this invention. The circuit diagram which shows the structure of the drive voltage control apparatus in the deformation | transformation aspect of Embodiment 2 of this invention. The circuit diagram which shows the structure of the drive voltage control apparatus for liquid crystal panels in Embodiment 3 of this invention The flowchart which shows operation | movement of the drive voltage control apparatus in the deformation | transformation aspect of this Embodiment 3. Waveform diagram showing the operation of the drive voltage control apparatus in a variation of the third embodiment The circuit diagram which shows the structure of the drive voltage control apparatus in the modification of this Embodiment 3. The circuit diagram which shows the structure of the drive voltage control apparatus for liquid crystal panels in Embodiment 4 of this invention FIG. 7 is a circuit diagram showing a configuration of a drive voltage control device for a liquid crystal panel in a fifth embodiment of the present invention. The circuit diagram which shows the structure of the drive voltage control apparatus for liquid crystal panels in Embodiment 6 of this invention The circuit diagram which shows the structure of the drive voltage control apparatus in the deformation | transformation aspect of Embodiment 6 of this invention. The circuit diagram which shows the structure of the drive voltage control apparatus for liquid crystal panels in Embodiment 7 of this invention The circuit diagram which shows the structure of the drive voltage control apparatus for liquid crystal panels in Embodiment 8 of this invention The circuit diagram which shows the structure of the drive voltage control apparatus for liquid crystal panels in Embodiment 9 of this invention FIG. 10 is a circuit diagram showing a configuration of a drive voltage control device for a liquid crystal panel in Embodiment 10 of the present invention. The circuit diagram which shows the structure of the drive voltage control apparatus for liquid crystal panels in Embodiment 11 of this invention The circuit diagram which shows the structure of the drive voltage control apparatus in the deformation | transformation aspect of Embodiment 11 of this invention. FIG. 12 is a circuit diagram showing a configuration of a drive voltage control device for a liquid crystal panel in Embodiment 12 of the present invention. The circuit diagram which shows the structure of the drive voltage control apparatus in the deformation | transformation aspect of Embodiment 12 of this invention. The circuit diagram which shows the structure of the drive voltage control apparatus for liquid crystal panels in Embodiment 13 of this invention Circuit diagram showing a configuration of a drive voltage control apparatus for a liquid crystal panel in Embodiment 14 of the present invention FIG. 15 is a circuit diagram showing a configuration of a drive voltage control device for a liquid crystal panel in a fifteenth embodiment of the present invention. The circuit diagram which shows the structure of the drive voltage control apparatus for liquid crystal panels in the aspect 1 of the deformation | transformation of Embodiment 15 of this invention. The circuit diagram which shows the structure of the drive voltage control apparatus for liquid crystal panels in the deformation | transformation aspect 2 of Embodiment 15 of this invention. The circuit diagram which shows the structure of the drive voltage control apparatus for liquid crystal panels in the aspect 3 of the deformation | transformation of Embodiment 15 of this invention. Configuration diagram of clamp element in embodiment 15 of the present invention Block diagram showing the configuration of a general active matrix liquid crystal panel drive device Circuit diagram showing the configuration of a driving voltage control device for a liquid crystal panel in the prior art (part 1) FIG. 2 is a circuit diagram showing a configuration of a driving voltage control device for a liquid crystal panel in the prior art (part 2). Waveform diagram showing the operation of the drive voltage control device in the prior art (part 1) Waveform diagram showing the operation of the drive voltage control device in the prior art (part 2)

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Input level control part 2 Load circuit 3 Timing control part 4 Switch control part 5 Comparator 6 Boost voltage control part 7 Arithmetic circuit 8 DA converter A1 Operational amplifier (1st operational amplifier) on the positive electrode side
A2 Second operational amplifier A3 Negative side operational amplifier CM1 Positive side comparator CM2 Negative side comparator CC, CC1 Positive side smoothing capacitor CC2 Negative side smoothing capacitor CL1... CLn Clamp element C _OUT Load capacity of liquid crystal panel Load resistance of R _OUT liquid crystal panel Si Input selection switch So Output control switch Ss Output selection switch St Timing control switch Su Boost control switch Sc1 ... Scn Short-circuit clamp control switch TR1, TR2 Low breakdown voltage transistor VH High level of input signal on the positive side Low side voltage VL Negative side input signal VGG, VHH Positive side boost voltage VNN, VLL Negative side boost voltage V _OUT Load drive voltage ΔV Boost voltage increase

Claims (6)

A buffer for supplying a load drive voltage obtained by impedance conversion of the input signal to the load circuit;
A drive voltage control apparatus comprising: an input level control unit that switches to a target drive voltage after giving a boost voltage whose absolute value is equal to or higher than the power supply voltage of the buffer for a certain period as an input voltage to the buffer . A comparator for comparing the target drive voltage and the load drive voltage;
It operates according to the comparison result of the comparator, and when the load drive voltage is higher than the target drive voltage, the boost voltage is stepped down, and when the load drive voltage is equal to the target drive voltage, the boost voltage is changed. The drive voltage control device according to claim 1, further comprising a boost voltage control unit that boosts the boost voltage when the load drive voltage is lower than the target drive voltage. The drive voltage control device according to claim 2 , wherein the comparator repeats the comparison operation a plurality of times with a set reference time as a cycle. If the requested convergence time is not updated, or when said load circuit is not changed, stores the boosted voltage, the drive voltage control device according to claim 2 or claim 3 wherein the comparator is turned off . A step of driving a load by inputting a boost voltage whose absolute value is equal to or higher than the power supply voltage of the buffer to the buffer;
Comparing the load drive voltage with the target drive voltage;
When the load drive voltage reaches the target drive voltage, inputting the target drive voltage into the buffer;
A drive voltage switching method comprising: A buffer for supplying a load driving voltage to a load circuit;
A comparator for comparing the load drive voltage with the target drive voltage;
As an input voltage to the buffer, a boost voltage whose absolute value is greater than or equal to the power supply voltage of the buffer is given. An input level control unit as a drive voltage;
A drive voltage switching device.

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