TWI374431B - Liquid crystal display device and method of driving the same - Google Patents

Description

1374431 The driving circuit 6〇 includes: a meter and a batch. μ A data drive 4〇 and a power supply 5 work. & 3, the system's complex external signal to generate the data control signal i = ^ i04 spear, the gate control signal to the closed-circuit driver 3 〇; the capital, generate (ICs). Moreover, the timing control is crying 2 〇 j price bottle circuit 40. The spur mouth (9) outputs the Beizhou Lu number to the data drive to 曰ίΓ=the device 30, and according to the gate control signal of the timing controller 20, the gate voltage of the control state is-single-single-level synchronization. The lines GL1 to GLn are turned on, so that the gate is sequentially applied to the inter-electrode connection to the material π hemp-pole line GU to GLn and the thin film electric day and body (TFTs) body (TFT; iiJ start · taste & When the thin film transistors (TFTs) corresponding to a single gate line are turned on, the material signal passes through the pixels in the pixel area of the panel 10. Wang Lm adds the liquid to the daily data according to the timing controller 2G. The data control signal 'selects: voltage, applies the selected reference voltage to the rotation angle of the liquid crystal panel 1 〇 knife. The power supply 115G generates a voltage source (4), the gate driver 30 and the data driver 4〇, and the power supply is $5G generated. - a common voltage is supplied to the liquid crystal panel 1 。. When the power of the liquid crystal display device of the technology f is turned off, the thin film electric crystal port: L / followed by (5), the data signal is stored in the liquid crystal capacitor (Clc) and the storage capacitor = Cst ) 'and' was retained without being released. Since the aforementioned retained greedy signal drives the liquid crystal panel in a short time_unusually, it causes the liquid crystal panel to show an unnecessary image or an abnormal image. SUMMARY OF THE INVENTION [Technical Problem to be Solved] Accordingly, embodiments of the present invention address one or more problems arising from prior art liquid crystal display devices and methods of driving, thereby avoiding the limitations of the prior art.

c S 6 1374431 and insufficient. One of the embodiments of the present invention is directed to a method, wherein 'includes a method for retaining a data message and its _, wherein the voltage-detection-display device and its illuminating device are included. It is too easy to see, or you can read and pay for the application and the scope of the application and the second technical solution of the problem-solving technique. According to the purpose of the embodiment of the present invention, the helmet is widely described, a driving electric power::, other advantages 'as the liquid crystal display =, the material of the switching element of the tributary material line and the interpolar line; - m na move it ·, the signal is applied to the capital Ϊ Ϊ = ^ signal to the data and the gate drive power supply ^ ί ί ; ; ; 以及 以及 以及 以及 以及 以及 以及 以及 以及 以及 以及 以及 以及 以及 以及 以及 以及 以及 以及 以及 以及 以及 以及 以及 以及 以及 以及 以及Hu /, the first 4 5 tiger is applied to the gate driver. There is a method for driving a liquid crystal display device, and the liquid crystal display device is tested, and the voltage is applied to the interrogator driver when the power supply voltage is laterally lower than a reference portion "^ii". The first signal will be a method for driving the display device, the crystal display device has a line, a plurality of data lines, and the connection to the gate line and the data modulo t 2 a gate driver The driving gate line 'includes: in the second operation sequentially with 1 sister-"-the power supply voltage, and the switching elements are arranged in a row according to the power supply house; after the operation mode, when The supply voltage is below the voltage of the voltage to cause all of the switching elements to operate synchronously during a discharge period. The following is a detailed description of the present invention, and an exemplary embodiment of the present invention will be described in detail below with reference to the following detailed description of the present invention. And the symbol of the component, and the method is more detailed, and the person skilled in the art can, after studying the specification, according to the embodiment of the present invention, a liquid crystal display (LCD device), including: one way' Is a problem for solving a residual image or an abnormal image? According to the present invention, a discharge of the remaining data signal in the liquid crystal display device is repeated (four) 2, and the image is wiped, after the power of the liquid crystal display device is turned off, In a predetermined period of time, the gate of the open-open state is also connected to a pole certificate, and then a thin film transistor (TFT) T is turned on. , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , The device includes: a liquid crystal panel for displaying an image and a driving circuit for the liquid crystal panel. The liquid crystal panel includes: a plurality of two: "lines GL1 to GLn" and a plurality of data lines Du to DLm. The plurality of strips GL1 to 5 intersect with the plurality of data lines DL1 to DLm to define a complex number, a region, and each of the pixel regions includes: a thin film transistor (TFT) T, a second: a tantalum capacitor (Clc) and a storage capacitor (4) for displaying an image. The secondary side driving circuit 160 includes: a timing controller 12A, a gate driver 13A, a power supply $14, a power supply 1115, and a discharge circuit 19G. The meter 12G generates a gate drive control signal for the gate driver by using a plurality of external signals of the external system, and the gate driver 13 includes: a plurality of "ICs" and a tributary driver ι4 〇 Generate data control signals, the capital 1374431 ·= extremely ^ i multiple data The body circuit (ics) ° asks the pole gate dipole output signal (G〇E), the gate displacement clock signal (GSC) signal (GSP) 'and 'the data control signal can include: a source Extremely, - miscellaneous sampling time (condition), - polarity reversal letter rushing (ssp). Moreover, the section (4) (9) - output to the data driver 14 〇. In addition, the timing control _ signal (FLK And the -DPM hold signal (DPWVCC), using the ^ circuit 190 'and 'provide the blinking signal (FLK), the DpM security number (DPM? CC) and the gate displacement clock signal (GSQ to the discharge circuit 190? °

When not controlling the 11 12G gate control number, the gate drive H 130 control ί ^ day panel 100 _ a plurality of thin film transistors (TFTs) on / off operation. The gate voltage is sequentially applied to the gates / ΐτ I to GU1 ' using a single horizontal synchronization time (1H) and the thin film transistor TFTs are connected to the gate line GL1 η. When the thin film transistor TFTs correspond to the opening of a single interrogation line, the data lines DU to DLm are applied to the pixels in the pixel area of the liquid crystal panel (10). Fun H 140 according to the timing control || 12〇 of the (four) control succession number select the - bedding signal ^ test, and mention the county's reference dragon ship crystal panel · upper 'use = adjust the rotation angle of liquid crystal molecules. The power supply 15 generates the first and third secret vcc, VDD and GND, and supplies the county voltage to the chirp timing controller 120, the data driver 14 and the discharge circuit 19A. In addition, the power supply 150 generates a gate high voltage VGH, a gate low voltage VGL and a common voltage Vcom ' and provides a gate high voltage (VGH) and a gate low voltage (VGL) to the closed end. Drive $13〇' to turn on and off a plurality of thin film transistors (TFTs)' and provide a common voltage Vc〇m to the liquid crystal panel 1〇〇. - The flip-flop circuit 190 includes four partial circuits that sing and hold a discharge apostrophe (ALL-H) during the silent time. For example, when the first source voltage VCc is depressed compared to the cutoff reference, the discharge circuit 190 generates the discharge signal (ALL_H) and supplies the 5 Hz to the gate driver 13A. The cut reference voltage can be. 1374431 IC194a, a second capacitor C2, a second resistor R2, a third resistor R3 and a first transistor T1. The second voltage detecting iCi94a may have an output terminal v〇m, a power supply terminal Vps and a ground terminal Vgd, and the first transistor T1 may be a positive-negative-positive (PNP) bipolar type. Because the output terminal v〇m of the second voltage detecting IC丨94a is connected to the base of the first transistor τι, the second voltage detecting lci94a controls the first transistor τι and determines the DPM through the first transistor T1. The guaranteed signal (bDPM-VCC) is the first change blinking signal (V_FLK1). For example, when the first source voltage vcc is lower than the cut-off reference voltage, the DPM hold signal (DPM - Vcc) is output from the second partial circuit 194 as the first change flicker signal (V - FLK1). Referring back to FIG. 4, when the first source voltage VCC is higher than the cut reference voltage, the third partial circuit 196 generates a flicker signal (FLK) as a second change flicker signal (V_FLK2)' and supplies it to Fourth partial circuit 198. Therefore, the third partial circuit 196 receives the flicker signal (FLK) and a gate shift clock signal (Gs&: and controls the flicker signal (FLK) as a second change flicker signal (vjpLUK supply. The flicker signal (FLK) is For the flashing & image in the LCD panel. For example: According to the flashing age 'LK), the pole pulse _ the rear may be employed, so that the pole pulse corresponds to a single period of the pole displacement clock signal (GSC) The long front region has a high voltage and has a low voltage in the short back region of the single-period. When the source voltage vcc is higher than the cutoff reference voltage, the third partial circuit & The device 12 〇 provides (in FIG. 3) a blinking signal (FLK squeaking signal (v-FLK2) to the fourth partial circuit 198, and when the =-breaking reference county, the _signal (·) is not supplied to the fourth partial circuit 8. Alternatively, the gate shift signal f_sc may be provided as a second change flicker signal #u(v_FLK2). As shown in FIG. 5C, the third partial circuit 196 may include: - a third capacitor C3, a fourth to a first person resistor R4 to a second transistor T2. Detection may have lci% a - Toru output terminal, and a power input terminal Vps - Vgd ground terminal, and the second electrically, because the third bipolar voltage detecting Icl96a'C2 1374431

Connected to the base of the second transistor T2, then the third voltage is measured by the lci%a transistor T2' and the flicker signal (FLK) is determined to be the second variation flash signal (V-FLK2). For example, when the first-voltage source vcc is higher than the cut-off reference voltage, the flicker signal (FLK) is output from the third partial circuit 196 as the second change Lu (V_FLK2). Further, when the first source voltage vcc is lower, the flicker signal (FLK) is not output from the third partial circuit 196 (yLK2). Alternatively, the second partial circuit 194 outputs a ## (〇卩1^一VCC) as the first change flicker signal (V_FLK丨). ',

Returning to the reference 4' according to the first and second change flicker signals (v-FLK1) and (V_FLK2) 'the fourth partial circuit 198, that is, a power supply module, for holding the signal (VGH-M) early, and It is provided to the interrogator 13 (Fig. 3). When the voltage is higher than the cut-off reference voltage, the liquid crystal display device is turned on, and the ίί, ί ί 198 and the flicker signal (FLK) are used together to modulate the gate signal, thereby generating a discharge retention VGH-M, New York Wei The holding money (VGH-M) is provided by the provider 130 (in Fig. 3) to operate the liquid crystal display without flickering. ; ί Γΐΐί pressure is lower than the cut-off reference voltage, the liquid crystal display device is turned off, the four-station 邛 circuit 198 and DPM hold signal DPM_VCC () (in FIG. 3) ' is used to determine the discharge signal (the period of the pre-turn time of the machine. Although not shown in the drawing, at least two of the first to third electrical measurements ICs 92a, 194a and 196a may form a single ic. 6 is a further embodiment of the present invention, the discharge circuit of the liquid crystal display device, J7A and FIG. 7B are respectively another embodiment of the present invention, the first and second partial circuits of the liquid crystal display device In FIG. 6, the discharge circuit, the second and third partial circuits 292, 294 and 298 and the first, second and third source voltages VCC, VDD and GND are received. When the reference voltage is cut off, the first partial circuit 292 outputs a discharge signal (έ - Η) to the gate driver (not shown). The cut reference voltage can be large, and the spoon is 2.5V. When the source voltage vcc is higher than the cutoff reference voltage, the third 374431

In the table 2, when the state is not on, the first source voltage vCC is higher than the cut-off reference voltage, and when it is off, it is lower than the cut-off reference voltage. When the first source voltage vcc is in an on state, the first transistor T21 is turned on and the second transistor T22 is turned off. In the state where the first source voltage vcc is in the _ state, the first transistor T21 is turned off and the second transistor T22 is turned on. As a result, the first partial circuit 392 outputs a flicker signal (FLK) in a state where the first source voltage VCC is turned on, and outputs a DPM hold signal (DPM VCC) as a change in the state in which the source voltage VCC is turned off. Jg number V_FLK. Therefore, the first partial circuit 392 having a single voltage to be measured jC392a in FIG. 8 and the first, second, and third portions having the first, second, and third voltage detecting ICs 92a, 194a, and 196a in FIG. Circuits 192, 194 and 196 have the same function.

VCC T21 T22 V-FLK On On Off FLK Off 1--- Off On DPM-VCC According to another embodiment of the present invention, FIG. 1A is a circuit diagram of a partial circuit of a discharge circuit of a liquid crystal display device. As shown in Fig. 10, the components of the first partial circuit 492 to the first partial circuit 392 in Fig. 9 are similar. Therefore, the first partial circuit includes a voltage detecting integrated circuit (IC) 492a, a first capacitor C31, first and fourth resistors R31 to R34, and first to second transistors T31 and T32. The 兮 voltage detection IC 492a has an output terminal Vout, a power input ps, and a =1 = vgd. In addition, the first transistor T31 may be negative-positive-negative (N; N)' double and the second transistor T32 may be positive-negative-positive (PNP) bipolar. In the first partial circuit 492, at least one blinking signal (FLK) and a gate displacement clock signal (GSC) of the timing controller 12 (in FIG. 3) are input to the first, third and fourth resistors R34 through the first, third and fourth resistors R34, respectively. The collector of the first transistor T31. Therefore, when the first voltage source VCC is higher than the cutoff reference voltage, the first electric body body outputs at least one _ signal (FLK) and the gate displacement clock signal (four) M changes flash signal (V- FLK). As a result, the first transistor Ώ1 and the first: electricity 1 344 431. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a schematic view of a prior art liquid crystal display device; FIG. 2 is a view showing a data signal retained in a liquid crystal display device according to an embodiment of the present invention. FIG. 3 is a schematic diagram of a liquid crystal display device according to an embodiment of the present invention; FIG. 4 is a block diagram of a discharge circuit of a liquid crystal display device according to an embodiment of the present invention; 5Α to 5C are respectively A circuit diagram of first to third partial circuits of a discharge circuit of a liquid crystal display device of an embodiment of the invention;

6 is a block diagram of a discharge circuit of a liquid crystal display device according to another embodiment of the present invention; and FIGS. 7A to 7B are circuit diagrams of first to second partial circuits of a discharge circuit of a liquid crystal display device according to another embodiment of the present invention, respectively. 8 is a block diagram of a discharge circuit of a liquid crystal display device according to another embodiment of the present invention; FIG. 9 is a circuit diagram of a first partial circuit of a discharge circuit of a liquid crystal display device according to another embodiment of the present invention; A circuit diagram of a partial circuit of a discharge circuit of a liquid crystal display device of another embodiment; and FIG. 11 is a timing chart showing a plurality of seven tigers for driving a liquid crystal display device according to another embodiment of the present invention. [Main component symbol description] 10 LCD panel 20 Timing controller 30 Gate driver 40 Data driver 50 Power supply 60 Drive circuit 100 LCD panel 120 Timing controller 130 Gate driver 18 < S ) 1374431 140 Data driver 150 Power supply 160 drive circuit 190 discharge circuit 192 first partial circuit 192a first voltage detection integrated circuit (1C) 194 second partial circuit

194a second voltage detection 1C 196 third partial circuit

196a third voltage detection 1C 198 fourth partial circuit 290 discharge circuit 292 first partial circuit 292a first detection integrated circuit (1C) 294 second partial circuit 298 third partial circuit 390 discharge circuit 392 first partial circuit 392a Voltage detection integrated circuit 398 second partial circuit 492 first partial circuit 492a voltage detecting integrated circuit C1 first capacitor C11 first capacitor C12 second capacitor C2 second capacitor C21 first capacitor C3 third capacitor C31 first Capacitor 1374431 R1 first resistor R11 first resistor R12 to R14 second to fourth resistor R2 second resistor R21 to R23 first to third resistor R3 third resistor R31 to R34 first to fourth resistor R4 to R8 fourth To the eighth resistor T1, the first transistor

T11~T12 first and second transistors T2 second transistors T21~T22 first and second transistors T31~T32 first and second transistors

20

Claims (1)

1374431 Patent application park: 1 circuit 'for driving - liquid crystal display device' the liquid crystal display device and - data drive n 'application of a plurality of data signals to the data line; - gate driver, applying a plurality of gate signals To the gate line; drive = control H, provide a plurality of (four) signals to the data driver and the closed-pole power supply for generating - the power supply voltage; and the first signal, when the discharge circuit side to the power supply voltage is low And the reference circuit maintains the signal; and when the discharge circuit detects the high voltage correction of the power supply voltage, the second signal corresponds to at least one of the flicker signal and the interpole displacement ^2, the electric circuit uses the power supply voltage generated by the power supply Applying 5 tigers and a second signal to the idler driver, 2. The driving circuit according to claim i, wherein when the power supply voltage is lower than a reference voltage, the first road detector 3. If the claim is for the purchase of the secret, the towel, the power supply, the ribs, the ribs, the ribs, the ribs, the ribs, the ribs, the ribs, the ribs, the ribs, the ribs, the ribs, the ribs, the ribs, the ribs, the ribs, the ribs Start time data signal. ',,. ^ ^ The driving circuit described in claim 1, wherein the discharge circuit package 21 is a partial circuit for comparing the power supply disk - the first = ???, and the first - ☆ pressure '' and when the source Electric 丄: in the 4»_ with the second electric, the device; /, keep 彳 5 旎 response timing control; ^ private circuit, used to compare the power supply voltage 盥 meter test, the source voltage is higher than the reference voltage When, the second; voltage, Ya, and when the electrical; and ^ for the control letter _ should be timed to control a fourth bureau's 'transfer _ interesting saki's ~. 6·H is the purchase of the circuit described in item 5, in the basin, the first-part includes: a first-electron-in-the-middle; "the first-voltage detection integrated body. The second partial circuit includes: a first a two-phase voltage integrated circuit; and an 11-turn transistor and a second second partial circuit include: a third capacitor-voltage detecting integrated circuit. 11 a transistor and a third φ 7. The driving method described in item 5 of the scope of the patent application is based on the purchase circuit described in the item _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ It is used to compare the power supply and the power supply to the lower limit of the reference power. The output of the first signal is compared with the first one. When the power supply is a first partial circuit, it is used to relocate the power supply to the whole earth voltage below the reference power. , providing a companion heart ^ comparison 'when the power supply: =; higher than the reference power】 = 22 22nd rn: for receiving the hold signal from the second partial circuit and the control signal includes: wherein the first partial electric circuit Including: Didi: ii; detection, body circuit; the second partial integrated circuit. Yi, a first transistor and a second voltage detection ι〇. The drive according to item 8 of the patent application scope is based on the gate displacement clock signal from the timing controller and the tiger system. The driving circuit, the power, the riding circuit package is referenced to the power; the source is one Ϊ 2 power; the electric ί: the controller; and the 仏 仏 仏 control signal response timing ❿ > letter ^ 2 _ self-partial circuit receiving Buying signals and controlling the first part 12. If the electricity = profit = item II, ♦ - control signal - second;,, letter f - the first - transistor, output 丽 detection complex Circuit. βθ controls the first-and second-electrode-electron-negative bipolar transistor. “Japanese-Japanese body, the first transistor contains a negative-positive- 23 1374431. From the timing of the batch circuit 'where' the control signal -. Guardian's gate displacement pulse signal and flicker signal 15 detect the aforementioned power supply voltage; and the second signal to the gate driver, the gate, coincidence-reference voltage 'apply-first-signal to mj The domain will open all of the aforementioned switching elements corresponding to a control signal ΐ 当 当 = = pressure; 'second signal corresponding - Bao #4 · Temple 1 ~ also 丨 gt. The method of claim 15, wherein the method of applying the method of claim 15, wherein the method is as described in claim 15 The steps of the first-disk first-domain are based on a single voltage fine-body circuit. The method of claim 15, wherein the method of detecting the integrated circuit according to a first voltage is based on a first voltage detecting integrated circuit. The method of claim 15, wherein the step of applying the first letter 24 1374431 is based on a first voltage integration step according to the second and third powers. ^The road applies the second signal 20. According to the scope of claim 15th, the closed-pole displacement clock from a timing controller === according to 21. pole ^ @ & 'The liquid crystal display device has a plurality of strips Open Dube material, spring, a plurality of opening and connecting parts connected to the gate line and the data line, and a gate driver for driving the gate line; including: when in the -operation mode to generate - power supply, belly Based on the power supply. The switching elements are arranged in a row in a row; after the operation, 'when the power supply is lower than a reference power_, the switch 7L is synchronized during the discharge period; and the control signal is added during the discharge to The polarity driver, the control signal applies a hold signal to the gate driver according to one of the gate displacement pulse signal and the blinking signal. 25 1374431 _ M Day Correction Replacement Page _ _____J Figure 1 S is the device 50 power supply H葙镙璁S data driver T Λ 1 ClCxxCst vUi nr n V3U^ λι n ULo ΛΙ n DL 1 DL .2 Oi .3 DL .〇] 1〇; \u- 10