JP2010008541A - Display panel driving device, display device and driving method of display panel - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To prevent noise images from being displayed on a liquid crystal display panel immediately after power is supplied. <P>SOLUTION: In a liquid crystal display device, after panel power PVDD is supplied, the timing of the prescribed stop time TS is started by a programmable timer in synchronism with the rising timing of vertical synchronizing signals Vsync, and the output of enable signals ENB is started simultaneously with the timing completion of the stop time TS. Thus, the display of images is started by the liquid crystal display panel. As a result, since the liquid crystal display panel is controlled to a non-display state during a masking period from the supply of the panel power PVDD to the completion of the timing of the prescribed stop time TS, the noise images are prevented from being displayed on the display panel immediately after the power is supplied. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

The present invention relates to a display panel driving device for driving a display panel in which a plurality of pixels are two-dimensionally arranged along a predetermined horizontal direction and vertical direction.
The present invention also relates to a display device including a display panel in which a plurality of pixels are two-dimensionally arranged along a predetermined horizontal direction and vertical direction.
The present invention also relates to a display panel driving method for driving a display panel in which a plurality of pixels are two-dimensionally arranged along a predetermined horizontal direction and vertical direction.

The display panel driving device described in Patent Document 1 includes a plurality of two-dimensional liquid crystal elements that can switch between transmission and non-transmission of light using the electro-optical property of liquid crystal that changes the polarization state of transmitted light according to an applied voltage. The liquid crystal display means is disposed and controlled to display at least characters and images by the drive voltage, and the control means provides a mask period during which the liquid crystal display means is not displayed when the power is turned on / off.
In the liquid crystal display driving device disclosed in Patent Document 1, a plurality of types of control signals for controlling the display state of the liquid crystal display panel are applied to all white or all of the display panel during a mask period having a predetermined time length after the device power is turned on. Keep the level corresponding to black. As a result, the entire display screen of the liquid crystal display panel is completely white during the mask period during which noise such as image disturbance, pixel defects, and afterimages (rain memory) can be displayed on the display panel during synchronization signal and control signal acquisition. Alternatively, the display state is all black, and the display of the noise image is forcibly masked. Specifically, during the mask period, the signal levels of the “bright signal”, “COM potential”, “COM gain signal”, and “dynamic range signal” are all white or all black in the display state of the display panel. Controlled.

However, in the liquid crystal display device, immediately after the device power is turned on, a streak-like noise image may be instantaneously displayed near the end portion (for example, the upper end portion) of the display panel regardless of the image display signal. . This is because the display panel driving device that drives the display panel sets the level of the counter electrode voltage applied to the vertical scanning circuit and the counter electrode of the display panel to one pixel column (horizontal pixel column) extending along the horizontal direction. ) When the scanning line driving circuit (gate driver) that changes every time is built in, the rise of the counter electrode voltage until the upper limit (H level) of the counter electrode voltage reaches a predetermined rated voltage after the device power is turned on to cause.
That is, when the first vertical scan for the display panel is started during the above-described counter electrode voltage rising time, the H level of the counter electrode voltage applied to the counter electrode reaches the rated value immediately after the start of the vertical scan. In this state, when a gate selection signal is output from the scanning line driving circuit to the scanning line and an image is displayed by the horizontal pixel column, a black or white streak noise image is generated by the horizontal pixel column. Will be displayed momentarily.
JP-A-11-212522

  An object of the present invention is to provide a display panel driving device, a display device, and a display panel that can prevent a noise image from being displayed on the display panel immediately after power is turned on, and that can effectively suppress the complexity of the device structure. It is to provide a driving method.

A display panel driving apparatus according to the present invention is a display panel driving apparatus for driving a display panel in which a plurality of pixels are two-dimensionally arranged along a predetermined horizontal direction and a vertical direction, and the horizontal level in the display panel is determined. When a power source for driving a display panel and a scanning line driving circuit for outputting a scanning line driving signal for driving a scanning line provided corresponding to a horizontal pixel column in which pixels are arranged along a direction is turned on And a signal output stop means for stopping the output of the drive signal from the scan line drive circuit to the scan line during a mask period until a predetermined display stop time elapses.
In the display panel driving device according to the present invention, the signal output stop means is supplied from the scanning line driving circuit during a mask period from when the power for driving the display panel is turned on until a predetermined display stop time elapses. By stopping the output of the drive signal to the scan line, it is generated by the scan voltage generation circuit during the mask period from when the power supply for driving the display panel is turned on until the predetermined display stop time elapses. Since the scanning line driving signal can be prevented from being output to the scanning line corresponding to the horizontal pixel column, the display panel can be maintained in a non-display state where no image is displayed.

In the display panel driving device according to the present invention, the display panel can be maintained in the non-display state only by stopping the output of the scanning line driving signal generated by the scanning voltage generation circuit during the mask period. The complexity of the circuit and software associated with the addition of the mask setting unit for realizing various functions can be effectively suppressed.
As a result, according to the display panel driving device of the present invention, it is possible to prevent a noise image from being displayed on the display panel immediately after the power is turned on, and to effectively suppress the complexity of the device structure. .
The display panel driving apparatus according to the present invention further includes an enable control circuit for outputting an enable signal to the scanning line driving circuit in order to define a timing for outputting the scanning line driving signal to the scanning line to be driven. The signal output stop means is provided with a mask setting section for stopping the output of the enable signal from the enable control circuit during the mask period.

In the display panel driving device according to the present invention, the mask setting unit stops outputting the enable signal during the mask period, so that the scanning line is supplied during the mask period from when the power supply for driving the display panel is turned on. The driving circuit can be prevented from selectively outputting the scanning line driving signal to the scanning line corresponding to the horizontal pixel column in synchronization with the input of the enable signal, so that the display panel can be maintained in the non-display state during the mask period.
In the display panel driving device according to the present invention, the scanning line driving signal is applied to the scanning line only by stopping the output of only the enable signal which is a single control signal output to the gate selection circuit during the mask period. Since the output can be prevented and the display panel can be maintained in a non-display state, the complexity of the circuit and software accompanying the addition of the mask setting unit for realizing such a function can be effectively suppressed.
The display panel driving device according to the present invention is characterized in that the mask setting unit is provided with a variable timer unit for setting the display stop time.

In the display panel driving device according to the present invention, since the variable timer unit for setting the display stop time is provided in the mask setting unit, the length of the display stop time can be simplified according to changes in various conditions in the device. Can be set to
Further, the display panel driving device according to the present invention includes a common electrode voltage generation circuit that applies a common electrode voltage that constitutes a pixel in the display panel, and the time length of the display stop time is determined after the display panel is turned on. The counter electrode voltage applied to the counter electrode by the counter electrode voltage generation circuit is set to be longer than a time length until the counter electrode voltage reaches a predetermined rated voltage.
In the display panel driving device according to the present invention, the display stop time is from when the display panel is turned on until the counter electrode voltage applied to the counter electrode by the counter electrode voltage generation circuit reaches a predetermined rated voltage. By setting the time length longer than the time length, when the power of the display panel is turned on, the counter electrode voltage applied to the counter electrode does not reach the predetermined rated voltage, so that a noise image is displayed on the display panel. Can be prevented.

Further, the display panel driving apparatus according to the present invention includes a plurality of vertical pixel columns configured through data lines provided respectively corresponding to the plurality of vertical pixel columns in which pixels are arranged along the vertical direction in the display panel. The display line is provided with a data line driving circuit that outputs a display signal to each of the pixels, and the display stop time is set such that the display signal output from the data line driving circuit reaches a predetermined rated output after the display panel is turned on. It is set longer than the time length until.
In the display panel drive device according to the present invention, the display stop time is set longer than the time until the display signal output from the data line driving circuit reaches a predetermined rated output after the display panel is turned on. Thus, when the display panel is powered on, the display signal output from the data line driving circuit does not reach a predetermined rated output, thereby preventing a noise image from being displayed on the display panel.

Hereinafter, a liquid crystal display device according to an embodiment of the present invention will be described with reference to the drawings.
(Liquid crystal display device)
FIG. 1 is a block diagram showing a liquid crystal display device according to an embodiment of the present invention. The liquid crystal display device 10 includes a liquid crystal display panel (hereinafter simply referred to as a “display panel”) 12 and a driving device thereof, and a plurality of pixels are provided on the display panel 12 as a reference for control. It is arranged two-dimensionally along the vertical direction (V direction) and the horizontal direction (H direction).
In FIG. 1, only 2 × 2 = 4 pixels are shown along the V direction and the H direction in order to simplify the display panel 12, but the number of such pixels is as follows. Any number can be set according to the size, pixel density, etc. of the display panel 12. In addition, with respect to a plurality of pixels (pixel columns) arranged along the H direction on the paper surface of FIG. 1, pixels (rows 1, 2, and 3) in order from the upper side to the lower side in the V direction ( Horizontal pixels), and a plurality of pixels (pixel columns) arranged along the V direction are pixels in the first, second, and third columns (vertical pixel columns) in order from the left in the H direction to the right. It shall be said.

The liquid crystal display device 10 includes a display panel 12, a data line driving circuit 20, a scanning line driving circuit 30, a display controller 40, and a power supply circuit 50. Note that the liquid crystal display device 10 does not have to include all these circuit blocks, and a part of the circuit blocks may be omitted. Here, the display panel 12 includes a plurality of scanning lines G _{1 to} G _M and a plurality of data lines S _{1 to} S _N.
Specifically, the display panel 12 is formed on an active matrix substrate (for example, a glass substrate). On this active matrix substrate, a plurality of scanning lines G _{1 to} G _M (M is a natural number of 2 or more) arranged in the V direction and extending in the H direction in FIG. 1, and data arranged in the H direction and extending in the V direction, respectively. Lines S _{1 to} S _N (N is a natural number of 2 or more) are arranged. Further, the scanning line _{G K (1 ≦ K ≦ M} , K is a natural number) and the data line _{S L (1 ≦ L ≦ N} , L is a natural number) at a position corresponding to the intersection of the thin film transistor 14 _KL as a switching element ( In a broad sense, a switching element) is provided.

The gate electrode of the thin film transistor 14 _KL is connected to the scan line G _K, a source electrode of the thin film transistor 14 _KL is connected to the data line S _L, the drain electrode of the thin film transistor 14 _KL is connected to the pixel electrode 13 _KL. Between the pixel electrode 13 _KL and the counter electrode 15 (common electrode, common electrode) facing the pixel electrode 13 _KL with the liquid crystal (electro-optical material in a broad sense) interposed therebetween, a liquid crystal capacitor 16 _KL (liquid crystal element) and An auxiliary capacitor 17 _KL is formed. Then, liquid crystal is formed between the active matrix substrate on which the thin film transistor 14 _KL and the pixel electrode 13 _KL are formed and the counter substrate on which the counter electrode 15 is formed, and the pixel electrode 13 _KL and the counter electrode 15 are formed. The transmissivity of the pixel changes according to the applied voltage between and.
Note that the voltage level (high potential side voltage VCOMH, low potential side voltage VCOML) of the counter electrode voltage VCOM applied to the counter electrode 15 is generated by a counter electrode voltage generation circuit included in the power supply circuit 50. Further, the counter electrode 15 may be formed in a strip shape so as to correspond to each of the scanning lines G _{1 to} G _M without being formed on one surface on the counter substrate.

The data line driving circuit 20 drives the data lines S ₁ to S _N of the display panel 12 based on display data. On the other hand, the scanning line driving circuit 30 scans (sequentially drives) the scanning lines G _{1 to} G _M of the display panel 12.
The display controller 40 controls the data line driving circuit 20, the scanning line driving circuit 30, and the power supply circuit 50 in accordance with the contents set by a host such as a central processing unit (CPU) (not shown). More specifically, the display controller 40 performs, for example, setting of the operation mode and supply of the internally generated vertical synchronization signal and horizontal synchronization signal to the data line driving circuit 20 and the scanning line driving circuit 30, For the power supply circuit 50, the polarity inversion timing of the voltage level of the common electrode voltage VCOM applied to the common electrode 15 is controlled.

The power supply circuit 50 determines various voltage levels (grayscale voltages) necessary for driving the display panel 12 and voltage levels (VCOMH, VCOML) of the counter electrode voltage VCOM of the counter electrode 15 based on a reference voltage supplied from the outside. ) Is generated. In the liquid crystal display device 10 having such a configuration, the data line driving circuit 20, the scanning line driving circuit 30, and the power supply circuit 50 display in cooperation with each other based on display data supplied from the outside according to the control of the display controller 40. The panel 12 is driven.
In the present embodiment, the liquid crystal display device 10 includes the display controller 40, but the display controller 40 may be provided outside the liquid crystal display device 10. Alternatively, the host may be included in the liquid crystal display device 10 together with the display controller 40. Further, the display driver 60 may be configured as a semiconductor device (integrated circuit, IC) by integrating the data line driving circuit 20, the scanning line driving circuit 30, and the power supply circuit 50.

(Power circuit)
FIG. 2 is a block diagram showing a configuration example of the power supply circuit 50 shown in FIG. The power supply circuit 50 includes a positive direction double boosting circuit 52, a scanning voltage generation circuit 54, and a counter electrode voltage generation circuit 56. The power supply circuit 50 is supplied with a system ground power supply voltage VSS and a system power supply voltage VDD.
The system ground power supply voltage VSS and the system power supply voltage VDD are supplied to the positive direction double booster circuit 52. Then, the positive direction double boosting circuit 52 generates a power supply voltage VOUT obtained by boosting the system power supply voltage VDD twice in the positive direction with reference to the system ground power supply voltage VSS. That is, the positive direction double boosting circuit 52 boosts the voltage difference between the system ground power supply voltage VSS and the system power supply voltage VDD by a factor of two. Such a positive direction double boosting circuit 52 can be constituted by a known charge pump circuit. The power supply voltage VOUT is supplied to the data line driving circuit 20, the scanning voltage generation circuit 54, and the counter electrode voltage generation circuit 56.

The scan voltage generation circuit 54 is supplied with the system ground power supply voltage VSS and the power supply voltage VOUT. Then, the scanning voltage generation circuit 54 generates the scanning voltage as the scanning line driving signal GLV. The scanning line driving signal GLV is a voltage signal applied to the scanning lines G _{1 to} G _M driven by the scanning line driving circuit 30. The high potential side voltage of the scanning line drive signal GLV is VDDHG, and the low potential side voltage is VEE.
The counter electrode voltage generation circuit 56 generates a counter electrode voltage VCOM. The common electrode voltage generation circuit 56 outputs the high potential side voltage VCOMH or the low potential side voltage VCOML as the common electrode voltage VCOM based on the polarity inversion signal POL. The polarity inversion signal POL is generated by the display controller 40 in accordance with the polarity inversion timing.

(Scanning line drive circuit)
FIG. 3 is a block diagram illustrating a configuration example of the scanning line driving circuit 30 in FIG. The scanning line driving circuit 30 is provided with a shift register 32 and a plurality of AND circuits 34 corresponding to the plurality of scanning lines G _{1 to} G _M , respectively. The scanning line driving circuit 30 includes an enable control circuit 70 that outputs an enable signal ENB in parallel to the plurality of AND circuits 34.
The shift register 32 is provided with a plurality of flip-flops provided corresponding to the scanning lines G _{1 to} G _M and sequentially connected. When the shift register 32 holds the scanning line driving signal GLV in the flip-flop in synchronization with the horizontal clock signal CKH, the shift register 32 sequentially shifts the scanning line driving signal GLV to the adjacent flip-flop in synchronization with the horizontal clock signal CKH. The plurality of flip-flops in the shift register 32 hold the scanning line driving signal GLV and output the scanning line driving signal GLV to the AND circuit 34.

  FIG. 4 is a block diagram illustrating a configuration example of the enable control circuit in FIG. The enable control circuit 70 outputs an enable signal ENB in parallel to the plurality of AND circuits 34 respectively corresponding to the scanning lines G1 to GM. The enable control circuit 70 includes a timer built-in register 74 and an AND circuit 76 to which the enable signal ENB output from the display controller 40 and the register signal REG output from the register 74 are input. . Here, the register 74 and the AND circuit 76 constitute a mask setting unit according to the present invention.

  The register 74 is constituted by, for example, a 32-bit processor (CPU) incorporating a programmable timer 78, and a stop time TS is set in advance in the programmable timer 78. The programmable timer 78 rises the vertical synchronization signal Vsync at the Rth time (R is an integer equal to or larger than 1 and set to R = 2 in the present embodiment) after the panel power supply PVDD (see FIG. 5) of the display panel 12 is turned on. Start timing in sync with. Here, the timing of the rise of the second vertical synchronizing signal Vsync defines the display start timing. The programmable timer 78 is timed up simultaneously with the elapse of the stop time TS from the start of timing. Simultaneously with this time-up, the register 74 starts outputting the register signal REG.

The stop time TS set in the programmable timer 78 can be changed to an arbitrary time length by rewriting data to the register 74. Further, after the panel power supply PVDD is turned on, the display controller 40 starts outputting the pulse waveform enable signal ENB in synchronization with the rise of the second vertical synchronization signal Vsync.
The enable control circuit 70 supplies the enable signal ENB to the AND circuit 34 during a mask period until a predetermined stop time TS elapses after the panel power supply PVDD is turned on and the second vertical synchronization signal Vsync rises. The output is stopped, and output of the enable signal ENB is started when the mask period elapses. In the present embodiment, the time length of the stop time TS is set to coincide with the time length of the 1V period defined by the vertical synchronization signal Vsync (see FIG. 5).

(Device operation when panel power is turned on)
Next, the operation when the panel power supply is turned on in the liquid crystal display device 10 according to the present embodiment will be described in comparison with the operation when the panel power supply PVDD is turned on in the conventional liquid crystal display device.
FIG. 5 shows an operation example when the panel power supply is turned on in the liquid crystal display device according to the present embodiment. In the liquid crystal display device 10, as shown in FIG. 5B, when the panel power supply PVDD is turned on, the panel drive voltage is boosted from the system ground power supply voltage VSS (= 0V) to the rated voltage VP over a certain period of time. To do.
Thereafter, as shown in FIGS. 5A, 5C, and 5D, the display controller 40 outputs the display signal Vid in synchronization with the falling timing of the vertical synchronization signal Vsync that defines the 1V period. And the supply of the counter electrode voltage VCOM from the power supply circuit 50 is started.

Here, the display signal Vid has a constant amplitude (= 5V) for each scanning line with respect to the center voltage VVG after a predetermined time (stabilization time T1) has elapsed since the panel power supply PVDD was turned on. The voltage signal is inverted. Also, the polarity of the counter electrode voltage VCOM is inverted with respect to the system ground power supply voltage VSS in one scanning line cycle after a predetermined time (stabilization time T2) has elapsed since the panel power supply PVDD is turned on. The signal has a symmetrical waveform that swings between the high potential side voltage VCOMH and the low potential side voltage VCOML.
On the other hand, during the period (unsteady period) before the stabilization time T1 elapses after the panel power supply PVDD is turned on, the display signal Vid has an amplitude between the high potential side voltage VVH and the low potential side voltage VVL. It is an asymmetric waveform signal that is narrow with respect to the amplitude between them and whose amplitude center is closer to the low potential side voltage VVL than the center voltage VVG. In the non-stationary period before the lapse of T1, the display signal Vid gradually approaches the amplitude defined by the high potential side voltage VVH and the low potential side voltage VVL with the passage of time, and the amplitude center is also the center voltage. Gradually approach VVG.
When the stabilization time T1 elapses and the display signal Vid transitions to the steady state, the amplitude of the display signal Vid matches the amplitude defined by the high potential side voltage VVH and the low potential side voltage VVL, and the center voltage is the center voltage. Consistent with VVG.

In the period before the stabilization time T2 elapses after the panel power supply PVDD is turned on (unsteady period), the counter electrode voltage VCOM also has an amplitude between the high potential side voltage VCOMH and the low potential side voltage VCOML. It is an asymmetric waveform signal whose amplitude center is narrower and whose amplitude center is closer to the low potential side voltage VCOML side than the system ground power supply voltage VSS. In the non-stationary period before the lapse of T2, the counter electrode voltage VCOM gradually approaches the amplitude defined by the high potential side voltage VCOMH and the low potential side voltage VCOML as time elapses, and the amplitude center is also the system. Gradually approaches the ground power supply voltage VSS. When the stabilization time T2 elapses and the state transitions to a steady state, the counter electrode voltage VCOM has an amplitude that matches the amplitude defined by the high potential side voltage VCOMH and the low potential side voltage VCOML, and the amplitude center is at the system center. It matches the ground power supply voltage VSS.
The display controller 40 outputs the horizontal start signal STH and the horizontal clock signal CKH shown in FIGS. 5E and 5F to the data line driving circuit 20 and also shown in FIGS. The vertical start signal STV and the vertical clock signal CKV are output to the scanning line driving circuit 30.

FIG. 6 shows an operation example when the panel power is turned on in the conventional liquid crystal display device, and FIG. 7 shows an image display state in the conventional liquid crystal display device when the panel power is turned on.
As shown in FIG. 6, even in the conventional liquid crystal display device 150, after the panel power supply PVDD is turned on, the panel drive voltage, the display signal Vid, and the counter electrode voltage VCOM are substantially the same as those of the liquid crystal display device 10 according to the present embodiment. The output starts at the same timing, and the output changes in the same manner.
On the other hand, in the liquid crystal display device 150, as shown in FIGS. 6A, 6B, and 6G, after the panel power supply PVDD is turned on, the display controller controls the vertical synchronization signal Vsync in synchronization with the rising timing. The output of the pulse waveform enable signal ENB starts from (not shown). As a result, the display panel 151 starts displaying an image. As described above, at this time, the display signal Vid has an amplitude defined by the normal high potential side potential VVH and the low potential side potential VVL. And an asymmetric waveform signal whose amplitude center is closer to the low potential side voltage VVL than the center voltage VVG.

The counter electrode voltage VCOM is also narrower than the amplitude defined by the normal high potential side voltage VCOMH and the low potential side voltage VCOML, and the center of the amplitude is closer to the low potential side voltage VCOML side than the system ground power supply voltage VSS. Asymmetrical waveform signal. At this time, comparing the stabilization time T1 of the display signal Vid with the stabilization time T2 of the counter electrode voltage VCOM, the time length of the stabilization time T2 is usually longer.
When the liquid crystal display device 150 starts displaying an image in the unsteady state, as shown in FIG. 7, one or more horizontal lines on the display start side along the vertical direction (V direction) in the display panel 151 are displayed. Depending on the pixel column, a black or white streak-like noise image GN may be displayed.

  In contrast to the conventional liquid crystal display device 150, in the liquid crystal display device 10 according to the present embodiment, as shown in FIGS. 5A, 5B, and 5G, after the panel power supply PVDD is turned on, the vertical synchronization signal Vsync is set. The output of the enable signal ENB is started from the display controller 40 in synchronism with the rising timing of each of the scanning lines. At this timing, the output of the register signal REG from the register 74 is not started. The enable signal ENB is not output to the AND circuits 34 corresponding to G1 to GM, respectively. Then, the thin film transistor corresponding to each scanning line is kept off, and the voltage from the data line is not applied to the corresponding pixel electrode.

On the other hand, the register 74 starts measuring the stop time TS by the programmable timer 78 simultaneously with the start of the output of the enable signal ENB by the display controller 40, and outputs the register signal REG to the AND circuit 76 simultaneously with completion of the stop time TS. Start. As a result, the output of the enable signal ENB from the enable control circuit 70 to the AND circuit 34 is started, so that the display panel 12 starts image display.
At this time, the time length of the stop time TS is set to coincide with the time length of the 1V period defined by the vertical synchronization signal Vsync (see FIG. 5A), and the time length of the 1V period is Usually, it is sufficiently longer than the stabilization time T1 of the display signal Vid and the stabilization time T2 of the counter electrode voltage VCOM.

As a result, in the liquid crystal display device 10 according to the present embodiment, after the panel power supply PVDD is turned on, the timing of the stop time TS is completed from the rising timing of the R-th vertical synchronization signal Vsync (second time in the present embodiment). In the period up to (mask period), since the display panel 12 is controlled to a state in which no image is displayed (non-display state), the display signal Vid or the counter electrode voltage VCOM does not reach the rated voltage. It is possible to surely prevent the streak-like noise image from being displayed on the panel 12.
In the liquid crystal display device 10 according to the present embodiment, as compared with the conventional liquid crystal display device 150, basically, only the register 74 is added to the enable control circuit 70, and output to the gate selection circuit 24 during the mask period. Since the output of the enable signal ENB can be prevented and the display panel 12 can be in a non-image display state, it is possible to effectively suppress the complexity of the circuit and software of the apparatus in order to realize such a function.

In the liquid crystal display device 10 according to the present embodiment, the time length of the stop time TS is set to be the same as the time length of the 1V period defined by the vertical synchronization signal Vsync, but this stop time TS is not necessarily the 1V period. It is not necessary to set the time length equal to the time length. For example, the time length obtained by multiplying the 1V period by an integral multiple (2 times or 3 times) may be set. Conversely, the time length may be set shorter than the 1V period. May be. Specifically, the stabilization times T1 and T2 of the display signal Vid and the counter electrode voltage VCOM in the apparatus may be measured and set appropriately according to the measured time.
In the liquid crystal display device 10, the stop time TS in the programmable timer 78 can be extended or shortened by rewriting data (stop time TS) to the programmable timer 78 in the register 74. As a result, even when various display conditions in the apparatus change, characteristics of each element constituting the circuit change, and the stabilization time of various signals including the display signal Vid and the counter electrode voltage VCOM changes, for example, The stop time TS can be easily set to an appropriate value according to the longest stable time.

It is a block diagram which shows the structure of the liquid crystal display device which concerns on embodiment of this invention. FIG. 2 is a block diagram showing a configuration of a power supply circuit in the liquid crystal display device shown in FIG. FIG. 2 is a block diagram showing a configuration of a scanning line driving circuit in the liquid crystal display device shown in FIG. FIG. 4 is a block diagram showing a configuration of an enable control circuit in the scanning line driving circuit shown in FIG. 3. 4 is a timing chart for explaining an operation example when a panel power supply is turned on in the liquid crystal display device according to the embodiment of the present invention. It is a timing chart for demonstrating the operation example at the time of power activation of the panel in the conventional liquid crystal display device. It is a front view which shows typically the noise image displayed on a display panel at the time of power activation of a panel in the conventional liquid crystal display device.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 Liquid crystal display device, 12 Display panel (liquid crystal display panel), 13 Pixel electrode, 14 Thin-film transistor, 15 Counter electrode, 16 Liquid crystal capacity, 17 Auxiliary capacity, 20 Data line drive circuit, 24 Gate selection circuit, 30 Scan line drive circuit, 32 shift register, 34 AND circuit, 40 display controller, 50 power supply circuit, 52 double booster circuit, 54 scanning voltage generation circuit, 56 counter electrode voltage generation circuit, 60 display driver, 70 enable control circuit, 74 register, 76 AND circuit , 78 the programmable timer, CKH horizontal clock signal, CKV vertical clock signal, ENB enable signal, G ₁ -G _M scan lines, GLV scanning line drive signals, GN noise image, POL polarity inversion signal, PVDD panel power, REG register signal , S ₁ -S _N data line, STH horizontal star Signal, STV vertical start signal, T1 stabilization time, T2 stabilization time, TS stop time, VCOM counter electrode voltage, VDD system power supply voltage, Vid display signal, VSS system ground power supply voltage, Vsync vertical synchronization signal

Claims (7)

A scanning line, a data line, a switching element provided corresponding to the intersection of the scanning line and the data line, a pixel electrode provided corresponding to the switching element, and a pixel electrode corresponding to the pixel electrode A display panel driving device for driving a display panel provided with a counter electrode provided,
A scanning line driving circuit for outputting a scanning line driving signal for driving the scanning line;
The output of the scanning line driving signal from the scanning line driving circuit to the scanning line is stopped during a mask period from when the power supply for driving the display panel is turned on until a predetermined display stop time elapses. Signal output stop means;
A display panel driving device comprising: An enable control circuit for outputting an enable signal for defining a timing for outputting the scan line drive signal to the scan line;
2. The display panel driving apparatus according to claim 1, wherein the enable control circuit includes a mask setting unit that stops the output of the enable signal to the signal output stop means during the mask period.   The display panel driving device according to claim 2, wherein the mask setting unit is provided with a variable timer unit that sets the mask period. A counter electrode voltage generation circuit for applying a counter electrode voltage to the counter electrode;
The time length of the mask period is set longer than the time length until the counter electrode voltage applied to the counter electrode by the counter electrode voltage generation circuit reaches a predetermined voltage after the display panel is turned on. 4. A display panel driving device according to claim 2, wherein A data line driving circuit for outputting a display signal to the pixel electrode through the data line;
The time length of the mask period is set longer than the time length until the display signal output from the data line driving circuit to the data line reaches a predetermined voltage after the display panel is powered on. The display panel driving device according to claim 2, wherein A display device comprising the display panel driving device according to any one of claims 1 to 5. A scanning line, a data line, a switching element provided corresponding to the intersection of the scanning line and the data line, a pixel electrode provided corresponding to the switching element, and a pixel electrode corresponding to the pixel electrode A driving method of a display panel provided with a counter electrode provided,
A scanning line driving circuit for outputting a scanning line driving signal for driving the scanning line;
An enable control circuit for outputting an enable signal for defining a timing for outputting the scan line drive signal to the scan line, and
The scanning line driving is performed by stopping the output of the enable signal from the enable control circuit during a mask period from when a power supply for driving the display panel is turned on until a predetermined display stop time elapses. A method of driving a display panel, wherein output of the scanning line driving signal from the circuit to the scanning line is stopped.

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