JP2015197484A - Liquid crystal display device and manufacturing method of liquid crystal display device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To suppress a reduction in display quality and prevent continuous application of voltage to picture pixels while the power is turned off.SOLUTION: A liquid crystal display device performs, during image display period, waveform adjustment processing of a gate signal creation voltage (scanning signal creation voltage) VGH for reducing the difference between picture pixels of a signal waveform of a gate signal (scanning signal) Vgh that is input to each of the picture signal on a gate line (scanning signal line) selected as a writing target, and does not perform the waveform adjustment processing during power-off processing.

Description

  The present invention relates to a technique for suppressing a voltage from being continuously applied to picture elements (pixels) when a power source is turned off in a liquid crystal display device.

  Conventionally, in a liquid crystal display device, it is known that if an electric field having the same polarity is continuously applied to a picture element, the liquid crystal molecules are polarized, causing problems such as changes in display characteristics and image burn-in. Further, when the power of the liquid crystal display device is turned off while displaying an image, the applied voltage immediately before the power is turned off remains applied to each picture element, and the same image is continuously drawn. Therefore, also in this case, problems such as seizure phenomenon occur.

  For this reason, in the conventional liquid crystal display device, when the power is turned off, a predetermined power-off process for discharging the charge applied to each pixel of the liquid crystal panel is executed.

  For example, in Patent Document 1, an electrolytic capacitor is provided in a power circuit, and when the power of the liquid crystal display device is turned off, a power-off process is performed on the entire screen of the liquid crystal panel using charges stored in the electrolytic capacitor. A technique for performing a process of drawing a predetermined pattern is described.

  Conventionally, due to the dullness of the waveform of the gate signal due to the wiring resistance of the gate line, the gate signal input between the picture element arranged near the gate driver and the picture element arranged far from the gate driver. It is known that the waveforms are different. For this reason, especially in a large-sized liquid crystal display device, the amount of the source signal drawn by the gate signal input to each pixel varies depending on the position on the gate line (according to the wiring path length from the gate driver). And display quality deteriorates.

  As a technique for preventing the deterioration of display quality due to such a dull waveform of the gate signal, for example, Patent Document 2 describes adjusting the signal waveform of the gate signal output from the gate driver. Yes.

JP 2000-131671 (May 12, 2000) International Publication No. 2012/005044 Pamphlet (released on January 12, 2012)

  However, in the configuration in which the signal waveform of the gate signal is adjusted as in Patent Document 2, when the power-off process is executed when the power is turned off as in Patent Document 1, each pixel is adjusted by adjusting the signal waveform of the gate signal. There is a problem that the voltage of the input gate signal is lowered, the pixel switching element cannot be driven, and a predetermined pattern for power-off processing cannot be drawn on the pixel.

  FIG. 11 is an explanatory diagram for explaining the above-described problem (note that the configuration shown in FIG. 11 is devised by the inventor of the present application in order to explain the above-described problem, and is not a known technique). .

  FIG. 11A shows the signal waveform during normal driving (when displaying an image according to image data) when the signal waveform of the gate signal is not adjusted (when the gate slope signal is not provided). FIG. 11B shows the signal waveform during normal driving (when displaying an image according to image data) when adjusting the signal waveform of the gate signal (when there is a gate slope signal). FIG. 11C shows a signal waveform during power-off processing (when applying a predetermined potential for power-off processing to each pixel) when adjusting the signal waveform of the gate signal. . 11A to 11C, the upper row shows control signals for controlling the operation of the gate driver used in the control circuit of the liquid crystal display device, and the lower row shows picture elements (gate lines in the liquid crystal panel). The input signal to the picture element near the edge part on the side and the picture element near the center part) is shown.

  As shown in the upper part of FIG. 11A, the operation of the gate driver is controlled based on the gate start pulse GSP, the gate clock signal GCK, and the gate signal generation voltage VGH. The gate driver sequentially outputs a gate signal Vgh corresponding to the gate signal generation voltage VGH to each gate line at a timing corresponding to the gate start pulse GSP and the gate clock signal GCK.

  As a result, as shown in the lower part of FIG. 11, the gate signal Vgh is sequentially applied to each gate line. At this time, since the wiring resistance of the gate line is relatively small, the gate signal Vgh substantially the same as the output potential from the gate driver is input to the picture element near the end on the gate driver side in the liquid crystal panel (in the drawing). (See the solid line part). On the other hand, the input potential to the picture element near the center of the liquid crystal panel (or near the end on the side far from the gate driver) is larger than the output potential from the gate driver due to the relatively high wiring resistance of the gate line. Dull (see broken line in the figure). For this reason, the signal waveform and the arrival potential of the gate signal Vgh input to each picture element differ depending on the arrangement position of each picture element on the gate line.

  For this reason, there is a variation in the amount of the source signal drawn by the gate signal Vgh between the pixel near the edge on the gate driver side and the pixel near the panel center (or near the edge far from the gate driver), As a result, the display quality is lowered.

  On the other hand, as shown in FIG. 11B, the control circuit provided in the previous stage of the gate driver adjusts the waveform of the gate signal generation voltage VGH supplied to the gate driver, thereby inputting each pixel. The variation in the voltage of the gate signal Vgh to be generated can be reduced, and the deterioration of display quality can be suppressed.

  In the example of FIG. 11, the gate signal generation voltage VGH is supplied from the control circuit to the gate driver during the period when the gate clock signal GCK is at the low level. Further, when the gate slope signal GSLOP is switched to the high level in the second half of the period when the gate clock signal GCK is at the low level, and the gate slope signal GSLOP is switched to the high level, the potential of the gate signal generation voltage VGH gradually decreases. To be adjusted. As a result, the arrival potential of the gate signal Vgh input to each picture element becomes substantially uniform for each picture element regardless of the position on the gate line, and the amount of the source signal drawn by the gate signal Vgh becomes substantially uniform. This suppresses the deterioration of display quality.

  However, during the power-off sequence, the input power supply during normal driving for the liquid crystal display device is shut off, and the power-off process is executed using the power stored in the charging means such as an electrolytic capacitor. Gradually decreases.

  For this reason, when the gate signal waveform is adjusted during the power-off sequence in the same manner as during normal driving, the potential of the gate signal Vgh input to each pixel decreases as shown in FIG. The threshold voltage Th of the switching element of the picture element is below, and it becomes impossible to appropriately apply a predetermined potential for power-off processing to each picture element.

  The present invention has been made in view of the above problems, and an object of the present invention is to provide a liquid crystal capable of suppressing a reduction in display quality and preventing a voltage from being continuously applied to a picture element when the power is turned off. It is to provide a display device.

  A liquid crystal display device according to one embodiment of the present invention is provided at each intersection of a plurality of scanning signal lines, a plurality of video signal lines intersecting with the scanning signal lines, and the video signal lines and the video signal lines. And a scanning signal line driver for outputting a scanning signal for selecting a scanning signal line to be written to the scanning signal line, and a potential corresponding to image data to each video signal line. A video signal line driving unit; and a voltage control unit that supplies a scanning signal generation voltage for generating the scanning signal to the scanning signal line driving unit, and the scanning signal line driving unit includes the scanning signal generation voltage. In the liquid crystal display device that outputs a scanning signal corresponding to the scanning signal line to be written, during the image display period, the voltage control unit applies to each pixel on the scanning signal line to be selected as the writing target. Difference of the input signal waveform of the scanning signal for each picture element For adjusting the waveform of the scanning signal generation voltage to reduce the image signal, and the video signal line driving unit outputs a potential corresponding to the image data to each video signal line, and the power-off process of the liquid crystal display device In some cases, the voltage control unit does not perform the waveform adjustment processing, and the video signal line driving unit outputs a predetermined potential for power-off processing to each video signal line.

  According to the liquid crystal display device according to one embodiment of the present invention, it is possible to suppress deterioration in display quality due to dullness of the scanning signal corresponding to the position on the scanning signal line during the image display period. Also, during power-off processing, the waveform adjustment processing of the scanning signal generation voltage prevents the potential of the scanning signal input to the picture element from dropping, and a predetermined potential for power-off processing is applied appropriately to each picture element. Thus, the charge accumulated in the picture element can be released. Therefore, it is possible to suppress the deterioration of display quality during the image display period and appropriately prevent the voltage from being continuously applied to the picture element when the power is turned off.

It is explanatory drawing which shows the structure of the liquid crystal display device concerning one Embodiment of this invention. FIG. 2 is an explanatory diagram illustrating a gate slope signal generation unit and a voltage adjustment unit provided in the gate control signal generation unit of the liquid crystal display device illustrated in FIG. 1. It is explanatory drawing which shows the structure of the liquid crystal panel with which the liquid crystal display device shown in FIG. 1 is equipped. It is explanatory drawing which shows the structure of the TFT substrate with which the liquid crystal panel shown in FIG. 3 is equipped. It is explanatory drawing which shows the structure of the picture element with which the liquid crystal panel shown in FIG. 3 is equipped. FIG. 6 is an equivalent circuit diagram of the picture element shown in FIG. 5. FIG. 6 shows an example of voltages applied to the gate terminal and the source terminal of a TFT provided in the picture element shown in FIG. 6 is a graph showing characteristics of a TFT included in the picture element shown in FIG. 5 and a TFT according to a comparative example. FIG. 2 is an explanatory diagram illustrating waveforms of gate driver control signals and input signals to each pixel in the liquid crystal display device illustrated in FIG. 1. It is explanatory drawing which shows the structure of the liquid crystal display device concerning other embodiment of this invention. It is explanatory drawing for demonstrating the problem which the conventional liquid crystal display device has.

Embodiment 1
An embodiment of the present invention will be described.

  FIG. 1 is an explanatory diagram showing a schematic configuration of a liquid crystal display device 100 according to the present embodiment. As shown in this figure, a liquid crystal display device 100 includes a power supply circuit 1, a control circuit (control unit) 2, a gate driver (scanning signal line driving unit) 3, a source driver (video signal line driving unit) 4, and a liquid crystal panel. 5 is provided.

  The power supply circuit 1 receives power supplied from an external power supply (for example, commercial power supply, private power generation power supply, charging device) for the power supply circuit 1 and supplies power to each block (each unit) of the liquid crystal display device 100. A voltage drop detection circuit 11, a main power supply circuit 12, and an auxiliary power supply circuit 13 are provided.

  The voltage drop detection circuit (voltage detection unit) 11 monitors the input voltage from the external power supply to the power supply circuit 1 to turn off the power of the liquid crystal display device 100 (power off by user operation, power supply due to power failure, disconnection, etc.). Off). In the present embodiment, the voltage drop detection circuit 11 monitors the supply voltage from the external power supply. However, the present invention is not limited to this. For example, the output voltage of the main power supply circuit 12 may be monitored.

  The main power supply circuit 12 distributes the power supplied from the external power supply to each block of the liquid crystal display device 100 during normal driving (during an image display period in which an image corresponding to image data is displayed).

  The auxiliary power supply circuit 13 includes a charging means (not shown) such as a capacitor, for example, and charges the charging means with electric power supplied from an external power source, and also supplies the charging means when the liquid crystal display device 100 is turned off. The charged power is supplied to each block that performs a power-off process (power-off sequence) in the liquid crystal display device 100. In the power-off process, when the liquid crystal display device 100 is powered off, a predetermined potential for the power-off process (for example, the potential of the counter electrode or substantially the same potential as the ground potential) is applied to the pixel electrode of each pixel of the liquid crystal panel 5. This is a process for releasing the charge accumulated in each picture element. Details of the power-off process will be described later.

  The power for charging the charging means provided in the auxiliary power supply circuit 13 may be input directly from the external power supply to the auxiliary power supply circuit 13 or may be input from the main power supply circuit 12.

  The control circuit 2 generates a control signal for causing the liquid crystal panel 5 to display an image corresponding to an input signal input from the outside of the control circuit 2, and outputs the control signal to the gate driver 3 and the source driver 4. An image data input unit 21, an image processing unit 22, a synchronization processing unit 23, a gate control signal generation unit (voltage control unit) 24, and a source control signal generation unit 25 are provided. The image data input unit 21, the image processing unit 22, the synchronization processing unit 23, the gate control signal generation unit 24, and the source control signal generation unit 25 may be configured by one chip, and a plurality of It may be composed of a chip.

  The image data input unit 21 receives an input signal input from the outside of the control circuit 2, outputs an image signal included in the input signal to the image processing unit 22, and outputs a synchronization signal included in the input signal to the synchronization processing unit 23. Output.

  The image processing unit 22 converts the image signal input from the image data input unit 21 into a signal corresponding to the input format of the source driver 4 and outputs the signal to the source driver 4.

  The synchronization processing unit 23 generates horizontal position information and vertical position information of each picture element based on the synchronization signal input from the image data input unit 21, and generates vertical position information as a gate control signal. The position information in the horizontal direction is output to the source control signal generator 25.

  The gate control signal generator 24 controls the gate driver 3 based on the vertical position information input from the synchronization processor 23 (gate start pulse GSP, gate clock signal GCK, gate output enable GOE). Etc.) and sent to the gate driver 3.

  In addition, the gate control signal generation unit 24 includes a gate slope signal generation unit 26 and a voltage adjustment unit 27, as shown in FIG.

  Based on the control signal input from the synchronization processing unit 23 and the control signal input from the voltage drop detection circuit 11, the gate slope signal generation unit 26 outputs a gate signal generation voltage (for generating a scanning signal) to the gate driver 3. A gate slope signal VSLOP for controlling the signal waveform of the (voltage) VGH is generated and output to the voltage adjusting unit 27.

  The voltage adjustment unit 27 outputs to the gate driver 3 a gate signal generation voltage VGH obtained by adjusting the potential of the input signal from the power supply circuit 1 (constant potential (26 V in this embodiment)) based on the gate slope signal GSLOP signal. . The control circuit 2 is provided with potential conversion means for converting the potential of the input signal from the power supply circuit 1 to a predetermined constant potential, and the potential converted to the constant potential by the potential conversion means is supplied to the voltage adjusting unit 27. You may do it. Details of processing in the gate control signal generation unit 24 and the voltage adjustment unit 27 will be described later.

  The source control signal generation unit 25 is configured to control the source driver 4 based on the horizontal position information input from the synchronization processing unit 23 (latch pulse, polarity inversion signal for AC driving of liquid crystal, etc.) ) And output to the source driver 4.

  FIG. 3 is an explanatory diagram showing a schematic configuration of the liquid crystal panel 5. As shown in this figure, the liquid crystal panel 5 includes a TFT substrate 51 and a counter substrate 52 which are arranged to face each other via a spacer 53, and a liquid crystal layer made of a liquid crystal material sealed between the TFT substrate 51 and the counter substrate 52. 54, the first polarizing plate 55 disposed on the back surface side of the TFT substrate 51 (the surface opposite to the surface facing the counter substrate 52), and the surface side of the counter substrate 52 (the surface facing the TFT substrate 51). And a second polarizing plate 56 disposed on the opposite surface side). A backlight 57 is disposed on the back side of the liquid crystal panel 5.

  The first polarizing plate 55 transmits only light according to the polarization axis direction of the first polarizing plate 55 among the light emitted from the backlight 57. In addition, a voltage corresponding to image data is applied to the liquid crystal layer 54 of each picture element (subpixel), whereby the birefringence of the liquid crystal in each picture element changes according to the image data, The polarization direction of the light passing through each picture element changes according to the image data. The second polarizing plate 56 transmits only light according to the polarization axis direction of the second polarizing plate 56 out of the light that has passed through the liquid crystal layer 54. Thereby, the image display is performed by controlling the amount of light transmitted through the liquid crystal panel 5 for each picture element according to the image data.

  In the area corresponding to each picture element in the counter substrate 52, any one of R (red), G (green), and B (blue) color filters is formed. One picture element (pixel) is formed by a combination of picture elements. As a result, the R, G, and B transmitted light amounts of each pixel are controlled for each pixel according to the image data, and an image according to the image data is displayed. In the present embodiment, R, G, and B picture elements are provided. However, the present invention is not limited to this, and other color picture elements may be provided.

  In the present embodiment, a case where the liquid crystal display device 100 is a transmissive liquid crystal display device 100 that performs display using light emitted from a backlight will be described. It may be a reflective liquid crystal display device that reflects incident light to be used as display light, and is a transflective liquid crystal display device that combines the functions of a transmissive liquid crystal display device and the reflective liquid crystal display device. It may be.

  In this embodiment, a liquid crystal display device in which a pixel electrode is provided on the TFT substrate 51 and a counter electrode is provided on the counter substrate 52 will be described. However, the present invention is not limited to this, and both the pixel electrode and the counter electrode are provided. The structure provided in the same board | substrate may be sufficient.

  FIG. 4 is an explanatory diagram showing a schematic configuration of the TFT substrate 51. As shown in this figure, on the TFT substrate 51, a large number of gate lines (scanning signal lines) 31, a large number of source lines (video signal lines) 41 arranged so as to intersect each gate line 31, A picture element 50 provided at each intersection of the gate line 31 and the source line 41 is provided.

  FIG. 5 is an explanatory diagram showing the picture element structure of the picture element 50 provided in the liquid crystal panel 5.

  As shown in FIG. 5, each picture element 50 includes a TFT (Thin Film Transistor) 61 as a switching element, a picture element electrode 62, and a counter electrode 63. The gate terminal of the TFT 61 is connected to the gate line 31, the source terminal is connected to the source line 41, and the drain terminal is connected to the pixel electrode 62.

  In the present embodiment, a TFT having a channel layer made of an indium gallium zinc oxide semiconductor (oxide semiconductor) is used as the TFT 61. However, the configuration of the TFT 61 is not limited to this, and may include a channel layer made of an oxide semiconductor other than an indium gallium zinc oxide semiconductor, or may have a channel layer made of a material other than an oxide semiconductor. May be.

  Each gate line 31 is connected to the gate driver 3, and each source line 41 is connected to the source driver 4. The counter electrode 63 is connected to a reference potential (counter potential) through a counter wiring (not shown) disposed on the counter substrate 52.

  Accordingly, the gate driver 3 periodically switches the gate line 31 to be written, and the source driver 4 is synchronized with the gate driver 3 to select the voltage applied to each source line as the writing target in the image data. By controlling according to the pixel value of each pixel connected to the gate line, a voltage corresponding to image data is applied to the liquid crystal layer 54 of each pixel 50 to control the orientation direction of the liquid crystal molecules, and display I do.

  FIG. 6 is an equivalent circuit diagram of the picture element 50. When the voltage of the gate terminal of the TFT 61 becomes higher than the voltage of the source terminal of the TFT 61 by a predetermined value or more (or when the voltage exceeds a predetermined threshold Th), the TFT 61 is turned on, and a current flows between the source terminal and the drain terminal. The potential of the source line 41 is applied to the liquid crystal capacitance (liquid crystal layer 54). In the equivalent circuit diagram, the pixel electrode 62, the counter electrode 63, and the liquid crystal layer 54 are represented as capacitors. In the example shown in FIG. 6, a liquid crystal storage capacitor (CS) arranged in parallel with the liquid crystal capacitor (the pixel electrode 62, the liquid crystal layer 54, and the counter electrode 63) for maintaining the potential of each pixel. However, the liquid crystal auxiliary capacitor 64 is not an essential component and may be omitted.

  The gate driver 3 controls the voltage applied to each gate line 31 provided in the liquid crystal panel 5 based on the control signal input from the gate control signal generator 24 (the gate signal is set to the high level and the low level). By switching), the gate line 31 to be written is periodically switched.

  The source driver 4 controls the voltage applied to each source line 41 at a timing synchronized with the switching cycle of the gate line 31 to be written by the gate driver 3 based on the control signal input from the source control signal generator 25. To do. Specifically, a potential applied to each source line 41 according to a signal input from the image processing unit 22 and a polarity inversion signal input from the source control signal generation unit 25 (connected to each source line 41). (A potential applied to a picture element connected to the gate line 31 to be written) among the selected picture elements), and the generated potential is determined according to a latch pulse LS input from the source control signal generation unit 25. To each source line 41.

  That is, the source driver 4 simultaneously switches the potential written to each source line 41 every time the latch pulse LS becomes high level. Therefore, the source driver 4 writes data for one line (one gate line) every time the latch pulse LS becomes high level.

  The gate driver 3 sequentially outputs a high-level potential line by line to each gate line 31 at a timing synchronized with the latch pulse LS.

  When the potential of the gate line 31 becomes high level, the potential of the gate terminal of the TFT 61 of each pixel connected to the gate line 31 becomes high level (threshold voltage TH or higher), and the source terminal of the TFT 61 changes from the drain terminal to the drain terminal. A current flows, and the potential of the source line 41 connected to the TFT 61 is applied to the pixel electrode 62. By sequentially performing this operation for all the gate lines 31, one screen is displayed. The operation of applying a potential to the pixel electrode of each pixel in this way is referred to as writing.

  FIG. 7 shows an example of a voltage applied to the gate terminal and the source terminal of the TFT 61. When the applied voltage (gate signal Vgh) to the gate terminal is at a high level (more than the threshold voltage Th of the TFT 61), the source terminal and the drain terminal are electrically connected, and the voltage applied to the source terminal via the source line 41 Is applied to the pixel electrode 62.

  As described above, in the present embodiment, a TFT having a channel layer made of an indium gallium zinc oxide semiconductor is used as the TFT 61.

  FIG. 8 shows a TFT made of indium gallium zinc oxide semiconductor (Example), a TFT made of low-temperature polysilicon (LTPS) (Comparative Example 1), and a TFT made of amorphous silicon (a-Si) (Comparative Example 2). It is the graph which compared the characteristic. The horizontal axis in FIG. 8 indicates the potential difference (Vg−Vs) between the gate and the source of the TFT, and the vertical axis indicates the current flowing between the source and the drain.

  As shown in FIG. 8, a TFT made of an indium gallium zinc oxide semiconductor has an off-leakage current (current flowing between the source and drain when the TFT is off) of 1 / TFT that is made of amorphous silicon (a-Si). It has a characteristic that it is 1000 or less and 1 / 10,000 or less of TFT made of low temperature polysilicon (LPTS).

  The above-described characteristics of TFTs made of an indium gallium zinc oxide semiconductor with low off-leakage current lead to improved driving characteristics (reduction of low power consumption, etc.), while the power supply of the liquid crystal display device is turned off. When this is done, there is a problem that the charges accumulated in the picture element electrodes are difficult to escape. If charges remain in the pixel electrode, an electric field in a certain direction is applied to the liquid crystal layer due to the potential difference between the pixel electrode and the counter electrode, and polarization occurs in the liquid crystal molecules composed of polar molecules, resulting in characteristic deviation and image Problems such as burn-in may occur.

  For this reason, in the liquid crystal display device 100 according to the present embodiment, a predetermined power-off process is performed to remove charges accumulated in the pixel electrodes when the power is turned off.

(1-2. Gate signal waveform adjustment processing and power-off processing)
Next, the waveform adjustment process of the gate signal and the power-off process performed when the power of the liquid crystal display device 100 is turned off will be described.

  FIG. 9A shows a control signal of the gate driver 3 generated or used by the gate control signal generation unit 24 during normal driving (an image display period in which an image corresponding to image data is displayed) and an input to each picture element. FIG. 9B shows the waveform of the control signal of the gate driver 3 and the signal input to each pixel generated or used by the gate control signal generator 24 during the power-off process. Yes.

  As shown in the upper part of FIG. 9A, the gate slope signal generation unit 26 of the gate control signal generation unit 24 responds to the gate clock signal GCK when the voltage drop detection circuit 11 does not detect power off. At the same timing, the gate slope signal VSLOP for adjusting the signal waveform of the gate signal generation voltage VGH input from the power supply circuit 1 is generated.

  Specifically, in this embodiment, the gate signal generation voltage VGH is supplied from the control circuit 2 to the gate driver 3 during a period when the gate clock signal GCK is at a low level. Further, the gate slope signal GSLOP is switched to the high level in the second half of the period when the gate clock signal GCK is at the low level.

  The voltage adjustment unit 27 is for generating a gate signal that gradually lowers the potential of the input signal from the power supply circuit 1 in an inclined manner when the gate slope signal VSLOP input from the gate slope signal generation unit 26 switches to a high level. A waveform adjustment process of the voltage VGH is performed.

  The gate driver 3 sequentially outputs a gate signal Vgh corresponding to the gate signal generation voltage VGH to each gate line at a timing corresponding to the gate clock signal GCK. In the present embodiment, the gate signal Vgh is output during a period when the gate clock signal GCK is at a low level.

  Thus, the waveform of the gate signal output from the gate driver 3 to each gate line becomes a waveform corresponding to the gate signal generation voltage VGH adjusted by the voltage adjustment unit 27. As a result, as shown in the lower part of FIG. 9A, the input signal waveform to the picture element near the end of the liquid crystal panel 5 on the gate driver 3 side and the picture element near the center of the liquid crystal panel 5 The difference from the input signal waveform is reduced as compared with the case where the waveform adjustment processing of the gate signal is not performed. Therefore, variation in the arrival potential of the gate signal Vgh input to each picture element can be reduced, and deterioration in display quality can be suppressed.

  In the power-off process, as shown in the upper part of FIG. 9B, the gate control signal generator 24 fixes the gate start pulse GSP to a high level and fixes the gate slope signal GSLOP to a low level. . That is, when the detection signal from the voltage drop detection circuit 11 indicates that the power supply is off, the gate slope signal generation unit 26 sets the gate slope signal GSLOP to the low level (the waveform adjustment processing of the gate signal generation voltage VGH). To a potential indicating that no operation is performed). As a result, the voltage adjustment unit 27 outputs the input potential from the power supply circuit 1 to the voltage adjustment unit 27 (constant potential 26 V in this embodiment) to the gate driver 3 as it is. When the gate start pulse GSP is fixed at a high level, the gate lines 31 are sequentially selected as write targets, and the gate lines 31 selected as write targets are subsequently not written. Without being maintained as a gate line to be written. That is, the TFT 61 of each picture element on the gate line 31 selected as a writing target is maintained in a conductive state between the source terminal and the drain terminal.

  As a result, as shown in the lower part of FIG. 9B, the gate signal Vgh corresponding to the gate signal generation voltage VGH not subjected to waveform adjustment processing is output to each gate line.

  Therefore, during the power-off process, the supply voltage from the charging means to the gate control signal generation unit 24 decreases and the gate signal generation voltage VGH supplied from the gate control signal generation unit 24 to the gate driver 3 decreases. However, it is possible to prevent the potential of the gate signal Vgh inputted to each picture element from further decreasing due to the waveform adjustment processing of the gate signal. As a result, the potential of the gate signal Vgh input to each picture element can be maintained to be equal to or higher than the threshold voltage Th of the TFT 61 of each picture element, and a predetermined potential for power-off processing is appropriately applied to each picture element. Can do.

  Alternatively, the capacity (power supply capability) required for the charging means to appropriately apply a predetermined potential for power-off processing to each pixel is reduced compared to when the gate signal waveform adjustment processing is performed during power-off processing. it can. Therefore, an inexpensive charging unit having a smaller capacity than that in the case of performing the waveform adjustment process of the gate signal during the power-off process can be used, so that the cost can be reduced.

[Embodiment 2]
Still another embodiment of the present invention will be described. In addition, the same code | symbol as the said embodiment is attached | subjected to the member which has the same function as embodiment mentioned above, and the description is abbreviate | omitted.

  FIG. 10 is an explanatory diagram showing the configuration of the liquid crystal display device 100b according to the present embodiment. 1 is different from the liquid crystal display device 100 shown in FIG. 1 in that a timing controller 2b is provided instead of the image data input unit 21, image processing unit 22, and synchronization processing unit 23, and gate control is performed separately from the timing controller 2b. A signal generator 24 and a source control signal generator 25 are provided. As the timing controller 2b, for example, a conventionally used timing controller IC can be used.

  In the example illustrated in FIG. 10, a control signal for controlling the operation of the gate driver 3 is input from the timing controller 2 b to the gate control signal generation unit 24, and the operation of the source driver 4 is performed from the timing controller 2 b to the source control signal generation unit 25. A control signal for controlling is input. The configurations and operations of the gate control signal generation unit 24 and the source control signal generation unit 25 are the same as those in the first embodiment.

  Also in the liquid crystal display device 100b having such a configuration, substantially the same effect as that of the liquid crystal display device 100 according to the first embodiment can be obtained.

[Embodiment 3]
In the first embodiment, the configuration in which the waveform adjustment processing of the gate signal generation voltage VGH is not performed when the gate slope signal GSLOP is at the low level has been described. On the other hand, in the present embodiment, when the gate slope signal GSLOP is at a high level, the waveform adjustment processing of the gate signal generation voltage VGH may not be performed. Also in this case, substantially the same effect as in the first embodiment can be obtained.

  It is more preferable that the gate slope signal GSLOP is a potential close to the ground potential among the high level and the low level, which indicates that the waveform adjustment processing of the gate signal generation voltage VGH is not performed. Thereby, the power consumption accompanying switching of the gate slope signal GSLOP during the power-off process can be reduced.

[Embodiment 4]
The control circuit 2 (particularly, the gate control signal generation unit 24, the source control signal generation unit 25, and the image processing unit 22) of the liquid crystal display device 100 is a logic circuit (hardware) formed in an integrated circuit (IC chip) or the like. It may be realized by software, or may be realized by software using a CPU (Central Processing Unit).

  In the latter case, the liquid crystal display device 100 includes a CPU that executes instructions of a program that is software that implements each function, and a ROM (Read Only Memory) in which the program and various data are recorded so as to be readable by a computer (or CPU). Alternatively, a storage device (these are referred to as “recording media”), a RAM (Random Access Memory) that expands the program, and the like are provided. And the objective of this invention is achieved when a computer (or CPU) reads the said program from the said recording medium and runs it. As the recording medium, a “non-temporary tangible medium” such as a tape, a disk, a card, a semiconductor memory, a programmable logic circuit, or the like can be used. The program may be supplied to the computer via an arbitrary transmission medium (such as a communication network or a broadcast wave) that can transmit the program. The present invention can also be realized in the form of a data signal embedded in a carrier wave in which the program is embodied by electronic transmission.

[Summary]
The liquid crystal display device 100 according to the first aspect of the present invention includes a plurality of scanning signal lines (gate lines 31), a plurality of video signal lines (source lines 41) intersecting the scanning signal lines (gate lines 31), and A pixel 50 provided at each intersection of the video signal line (source line 41) and the video signal line (source line 41), and a scanning signal line to be written to the scanning signal line (gate line 31). A scanning signal line driver (gate driver 3) that outputs a scanning signal for selecting (gate line 31), and a video signal line that outputs a potential corresponding to image data to each of the video signal lines (source line 41). A drive unit (source driver 4) and a voltage control unit (gate control signal generation unit) for supplying a scanning signal generation voltage for generating the scanning signal to the scanning signal line driving unit (gate driver 3) 4), and the scanning signal line driver (gate driver 3) outputs a scanning signal corresponding to the scanning signal generation voltage to the scanning signal line (gate line 31) to be written. In the image display period, the voltage control unit (gate control signal generation unit 24) scans the pixel 50 on the scanning signal line (gate line 31) selected as a writing target. The waveform adjustment processing of the scanning signal generation voltage for reducing the difference between the signal waveforms of the signals for each picture element is performed, and the video signal line driving unit (source driver 4) sets the potential corresponding to the image data to each of the above-described voltages. When the power is output to the video signal line (source line 41) and the liquid crystal display device 100 is turned off, the voltage control unit (gate control signal generation unit 24) does not perform the waveform adjustment process, and the video signal line drive is not performed. Part (a source driver 4) has a predetermined potential for power-off processing and outputting to the respective video signal lines (source lines 41).

  According to the above configuration, the voltage control unit (gate control signal generation unit 24) is input to each pixel 50 on the scanning signal line (gate line 31) selected as a writing target during the image display period. While the waveform adjustment processing of the scanning signal generation voltage is performed to reduce the difference of the signal waveform of the scanning signal for each picture element, the waveform adjustment processing of the scanning signal generation voltage is not performed during the power-off processing. Further, the video signal line driving unit (source driver 4) outputs a potential corresponding to the image data to each video signal line (source line 41) during the image display period. The potential is output to each video signal line (source line 41). Thereby, it is possible to suppress deterioration in display quality due to dullness of the scanning signal corresponding to the position on the scanning signal line (gate line 31) during the image display period. Further, during the power-off process, the scan signal generation voltage waveform adjustment process prevents the potential of the scanning signal input to the picture element 50 from being lowered, and a predetermined potential for the power-off process is reliably set in each picture element 50. And the charge accumulated in the picture element 50 can be released. Accordingly, it is possible to suppress the deterioration of display quality during the image display period and appropriately prevent the voltage from being continuously applied to the picture element 50 when the power is turned off.

  The liquid crystal display device 100 according to the second aspect of the present invention is the liquid crystal display device 100 according to the first aspect, wherein the main power supply circuit 12 supplies power supplied from an external power source to the voltage control unit (gate control signal generation unit 24). An auxiliary power supply circuit 13 that supplies power charged in a charging means provided in the apparatus 100 to the voltage control unit (gate control signal generation unit 24), and the voltage control unit (gate control signal generation unit 24) includes: During the image display period, the scanning signal generation voltage generated by subjecting the supply voltage from the main power supply circuit 12 to the waveform adjustment processing is output to the scanning signal line driver (gate driver 3), and the power-off processing is performed. In some cases, a voltage corresponding to the supply voltage from the auxiliary power supply circuit 13 is output to the scanning signal line driver (gate driver 3) as the scanning signal generation voltage.

  According to the above configuration, since the power-off process is performed using the supply voltage from the charging unit during the power-off process, the supply voltage from the charging unit gradually decreases. Since the potential can be prevented from decreasing, the power-off process can be appropriately performed. Further, since the capacity of the charging means required for appropriately completing the power-off process can be reduced, the cost can be reduced.

  The liquid crystal display device 100 according to the third aspect of the present invention includes the voltage detection unit (voltage drop detection circuit 11) that detects a decrease in the supply voltage from the external power source in the second aspect, and includes the voltage control unit (gate control). The signal generator 24) and the video signal line driver (source driver 4) perform the power-off process when the voltage detector detects that the supply voltage from the external power source has fallen below a predetermined value. It is the structure to perform.

  According to the above configuration, the power off of the liquid crystal display device 100 is detected by the voltage detection unit, and the power off process is automatically performed by the voltage control unit (gate control signal generation unit 24) and the video signal line drive unit (source driver 4). Can be done automatically.

  The liquid crystal display device 100 according to the fourth aspect of the present invention is the liquid crystal display device 100 according to any one of the first to third aspects, wherein the picture element 50 includes a picture element electrode 62, a counter electrode 63, a picture element electrode 62, and a counter electrode 63. The liquid crystal layer 54 disposed between the gate terminal is connected to the scanning signal line (gate line 31), the source terminal is connected to the video signal line (source line 41), and the drain terminal is connected to the pixel electrode 62. And the predetermined potential is substantially the same as the counter electrode 63 or the ground potential.

  According to the above configuration, the off-leak current of the switching element (TFT 61) is increased by setting the potential applied to the pixel electrode 62 during the power-off process to substantially the same potential as the counter electrode 63 or the ground potential. Accumulated charges can be easily removed.

  A liquid crystal display device 100 according to an aspect 5 of the present invention has a configuration in the aspect 4 in which the switching element is a thin film transistor including a channel layer made of an oxide semiconductor.

  A thin film transistor including a channel layer made of an oxide semiconductor has a characteristic that the off-leakage current is very small, and it is difficult for the charge accumulated in the pixel to escape, and the charge is accumulated in the pixel during the power-off period. Problems such as burn-in continue to occur. On the other hand, according to the above configuration, since the power stored in the picture element 50 can be removed by appropriately performing the power-off process, a thin film transistor including a channel layer made of an oxide semiconductor is used. Even if it is a case, it can prevent that malfunctions, such as image sticking, arise.

  The control method of the liquid crystal display device 100 according to the sixth aspect of the present invention includes a plurality of scanning signal lines (gate lines 31) and a plurality of video signal lines (source lines 41) intersecting with the scanning signal lines (gate lines 31). ), The pixel 50 provided at each intersection of the scanning signal line (gate line 31) and the video signal line (source line 41), and the scanning signal line (gate line 31) to be written. A scanning signal line driver (gate driver 3) that outputs a scanning signal for selecting a scanning signal line (gate line 31), and a potential corresponding to image data are output to each of the video signal lines (source line 41). A video signal line driver (source driver 4) and a voltage controller (gate control) for supplying a scanning signal generation voltage for generating the scanning signal to the scanning signal line driver (gate driver 3). And a scanning signal line driver (gate driver 3) that outputs a scanning signal corresponding to the scanning signal generation voltage to a scanning signal line (gate line 31) to be written. In the control method of the display device 100, during the image display period, each pixel 50 on the scanning signal line (gate line 31) selected as a writing target by the voltage control unit (gate control signal generation unit 24). The waveform of the scanning signal generation voltage for reducing the difference of the signal waveform of the scanning signal inputted to each pixel is reduced, and the video signal line driving unit (source driver 4) A potential corresponding to an image to be displayed on the video signal line (source line 41) is output, and when the liquid crystal display device 100 is powered off, the voltage control unit (gate control signal generation unit 24) transmits the wave. Without adjustment process is characterized in that for outputting a predetermined electric potential for power-off processing to the respective video signal lines (source lines 41) from the video signal line drive unit (source driver 4).

  According to the above method, it is possible to suppress a decrease in display quality due to the dullness of the scanning signal corresponding to the position on the scanning signal line (gate line 31) during the image display period. Further, during the power-off process, the scan signal generation voltage waveform adjustment process prevents the potential of the scanning signal input to the picture element 50 from being lowered, and a predetermined potential for the power-off process is reliably set in each picture element 50. And the charge accumulated in the picture element 50 can be released. Accordingly, it is possible to suppress the deterioration of display quality during the image display period and appropriately prevent the voltage from being continuously applied to the picture element 50 when the power is turned off.

  The present invention is not limited to the above-described embodiments, and various modifications can be made within the scope shown in the claims. That is, embodiments obtained by combining technical means appropriately modified within the scope of the claims are also included in the technical scope of the present invention.

  The present invention can be applied to a liquid crystal display device.

DESCRIPTION OF SYMBOLS 1 Power supply circuit 2 Control circuit 2b Timing controller 3 Gate driver (scanning signal line drive part)
4 Source driver (video signal line driver)
5 Liquid crystal panel 11 Voltage drop detection circuit (voltage detection part)
12 main power circuit 13 auxiliary power circuit 21 image data input unit 22 image processing unit 23 synchronization processing unit 24 gate control signal generation unit 25 source control signal generation unit (voltage control unit)
26 Gate slope signal generator (voltage controller)
27 Voltage regulator (voltage controller)
31 Gate line (scanning signal line)
41 Source line (video signal line)
50 picture element 54 liquid crystal layer 61 TFT (switching element)
62 picture element electrode 63 counter electrode 100 liquid crystal display device 100b liquid crystal display device

Claims (6)

A plurality of scanning signal lines, a plurality of video signal lines intersecting with each of the scanning signal lines, a picture element provided at each intersection of the video signal line and the video signal line, and writing to the scanning signal line A scanning signal line driving unit that outputs a scanning signal for selecting a scanning signal line to be embedded; a video signal line driving unit that outputs a potential corresponding to image data to each of the video signal lines; and the scanning signal line driving And a voltage control unit that supplies a scanning signal generation voltage for generating the scanning signal to the unit, and the scanning signal line driving unit scans the scanning signal corresponding to the scanning signal generation voltage as a writing target. A liquid crystal display device that outputs to a signal line,
During the image display period, the voltage control unit generates the scanning signal for reducing the difference of the signal waveform of the scanning signal input to each pixel on the scanning signal line selected as a writing target for each pixel. Voltage waveform adjustment processing, and the video signal line drive unit outputs a potential corresponding to image data to each video signal line,
In the power-off process of the liquid crystal display device, the voltage control unit does not perform the waveform adjustment process, and the video signal line driving unit outputs a predetermined potential for the power-off process to each video signal line. Liquid crystal display device. A main power supply circuit for supplying power supplied from an external power supply to the voltage control unit;
An auxiliary power supply circuit that supplies power charged in charging means provided in the liquid crystal display device to the voltage control unit,
The voltage control unit outputs the scanning signal generation voltage generated by performing the waveform adjustment process to the supply voltage from the main power supply circuit during the image display period to the scanning signal line driving unit, and performs a power-off process. 2. The liquid crystal display device according to claim 1, wherein a voltage corresponding to a supply voltage from the auxiliary power supply circuit is sometimes output to the scanning signal line driver as the scanning signal generation voltage. A voltage detection unit that detects a decrease in the supply voltage from the external power source,
The voltage control unit and the video signal line driving unit perform the power-off process when the voltage detection unit detects that the supply voltage from the external power source has decreased to a predetermined value or less. The liquid crystal display device according to claim 2. The picture element includes a picture element electrode, a counter electrode, a liquid crystal layer disposed between the picture element electrode and the counter electrode, a gate terminal connected to the scanning signal line, and a source terminal connected to the video signal line. A switching element connected and having a drain terminal connected to the pixel electrode,
4. The liquid crystal display device according to claim 1, wherein the predetermined potential is substantially the same potential as the counter electrode or the ground potential.   The liquid crystal display device according to claim 4, wherein the switching element is a thin film transistor including a channel layer made of an oxide semiconductor. A plurality of scanning signal lines, a plurality of video signal lines intersecting with each of the scanning signal lines, a picture element provided at each intersection of the video signal line and the video signal line, and writing to the scanning signal line A scanning signal line driving unit that outputs a scanning signal for selecting a scanning signal line to be embedded; a video signal line driving unit that outputs a potential corresponding to image data to each of the video signal lines; and the scanning signal line driving And a voltage control unit that supplies a scanning signal generation voltage for generating the scanning signal to the unit, and the scanning signal line driving unit scans the scanning signal corresponding to the scanning signal generation voltage as a writing target. A method of controlling a liquid crystal display device that outputs to a signal line,
During the image display period, the scan signal generation for reducing the difference of the signal waveform of the scan signal inputted to each picture element on the scan signal line selected as a writing target in the voltage control unit for each picture element. The voltage adjustment processing for the voltage is performed, and the electric potential corresponding to the image displayed on each video signal line is output from the video signal line driving unit,
In the power-off process of the liquid crystal display device, the voltage control unit does not perform the waveform adjustment process, and the video signal line driving unit outputs a predetermined potential for the power-off process to each video signal line. Control method for liquid crystal display device.

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