JP2015068856A - Liquid crystal display device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a liquid crystal display device that suppresses the accumulation of charge on pixels when the power is turned off.SOLUTION: The liquid crystal display device is configured such that the falling rate of an auxiliary capacitor potential VCS, which is a potential applied to a liquid crystal auxiliary capacitance through auxiliary capacitance wiring, is made faster than the falling rate of a counter potential VCOM, which is a potential applied to a counter electrode, during at least a part of a period from the start of power-off operation to the completion of the power-off operation.

Description

  The present invention relates to a technique for removing charges of each picture element when a liquid crystal display device is turned off.

  Conventionally, when an electric field having the same polarity is continuously applied to a picture element (or pixel) in a liquid crystal display device, polarization of liquid crystal molecules occurs, causing problems such as changes in gradation display characteristics of the picture element and image burn-in. It is known.

  Further, when the power of the liquid crystal display device is turned off while displaying an image, the applied voltage immediately before the power is turned off remains applied to each picture element, and the same image is continuously drawn. Therefore, it is known that a seizure phenomenon occurs also in this case.

  For this reason, in the conventional liquid crystal display device, when the power is turned off, a predetermined off sequence for discharging the charge applied to each pixel of the liquid crystal display panel is executed.

  For example, in Patent Document 1, an electrolytic capacitor is provided in a power supply circuit, and when the power of the liquid crystal display device is turned off, a predetermined amount is applied to the entire screen of the liquid crystal display panel using charges stored in the electrolytic capacitor. A technique for reducing the charge accumulated in a picture element by performing a process of drawing a fixed pattern is described.

JP 2000-131671 (May 12, 2000)

  By the way, in recent years, TFTs (thin film transistors) with low off-leakage current made of an oxide semiconductor (for example, indium gallium zinc oxide semiconductor) or the like are used as pixel switching elements, thereby reducing vertical shadows and reducing power consumption due to intermittent driving. Liquid crystal display devices that have been reduced have been developed.

  However, this type of liquid crystal display device has much less off-leakage current than a liquid crystal display device using TFTs made of amorphous silicon, low-temperature polysilicon, etc., so that the charge accumulated in the picture element when the power is turned off is small. It has the characteristic that it is hard to come off.

  FIG. 17 is a graph comparing off-leakage current characteristics of a TFT made of an indium gallium zinc oxide semiconductor, a TFT made of low-temperature polysilicon (LTPS), and a TFT made of amorphous silicon (a-Si). The horizontal axis in FIG. 17 indicates the potential difference (Vg−Vs) between the gate and source of the TFT, and the vertical axis indicates the current flowing between the source and drain.

  As shown in FIG. 17, a TFT made of an indium gallium zinc oxide semiconductor has a characteristic that an off-leakage current is 1/1000 or less of a TFT made of amorphous silicon and 1 / 10,000 or less of a TFT made of low-temperature polysilicon. doing.

  The above-described characteristics of TFTs made of an oxide semiconductor with low off-leakage current result in improved driving characteristics (low power consumption, etc.), but on the other hand, when the power of the liquid crystal display device is turned off. This causes a problem that the charges charged in the pixel electrodes are difficult to escape. If charges remain in the pixel electrode, an electric field in a certain direction is applied to the liquid crystal layer due to the potential difference between the pixel electrode and the counter electrode, and polarization occurs in the liquid crystal molecules composed of polar molecules, resulting in characteristic deviation and image Problems such as burn-in may occur.

  For this reason, when a TFT made of an oxide semiconductor or the like with a small off-leakage current is used, even if the charge accumulated in the picture element is reduced when the power is turned off by the process disclosed in Patent Document 1, the process does not remove it. In some cases, defects such as burn-in may occur due to the electric charge remaining in the picture elements. In addition, the technique disclosed in Patent Document 1 needs to include a circuit that executes an off sequence and a charging unit such as an electric field capacitor that charges electric power for executing the off sequence, which increases manufacturing costs. There is also a problem.

  The present invention has been made in view of the above problems, and an object of the present invention is to provide a liquid crystal display device in which charges are not easily accumulated in picture elements when the power is turned off.

  The liquid crystal display device according to one embodiment of the present invention is provided for each of a plurality of gate bus lines, a plurality of source bus lines intersecting with the gate bus lines, and an intersection of the gate bus lines and the source bus lines. A pixel terminal and a counter electrode arranged opposite to each other via a liquid crystal layer, a gate terminal connected to the gate bus line, a source terminal connected to the source bus line, and a drain. A liquid crystal display device comprising: a switching element having a terminal connected to the pixel electrode; and an auxiliary capacitance wiring that is disposed opposite to the pixel electrode and forms a liquid crystal auxiliary capacitance with the pixel electrode. Thus, during at least a part of the period from the start of the power-off operation to the completion of the power-off operation, the decreasing speed of the auxiliary capacitance potential, which is the potential of the auxiliary capacitance wiring, is Is characterized by faster than lowering speed of the opposing electric potential is the potential.

  According to the above configuration, since the potential of both electrodes (the pixel electrode and the auxiliary capacitance wiring) of the liquid crystal auxiliary capacitance changes so as to maintain the potential difference between the two electrodes, the picture can be obtained by rapidly reducing the auxiliary capacitance potential. The potential of the elementary electrode can be quickly reduced. As a result, since the potential difference between the gate terminal and the source terminal of the switching element can be increased, the leakage current of the switching element can be increased and the charge of the pixel electrode can be effectively released by the source bus line. This makes it possible to realize a liquid crystal display device with a simple configuration in which charges are not easily accumulated in the picture element when the power is turned off.

It is explanatory drawing which shows schematic structure of the liquid crystal display device concerning Embodiment 1 of this invention. It is explanatory drawing which shows the structure of the liquid crystal panel with which the liquid crystal display device shown in FIG. 1 is equipped. It is explanatory drawing which shows the structure of the TFT substrate with which the liquid crystal panel shown in FIG. 2 is equipped. It is explanatory drawing which shows the structure of the picture element with which the liquid crystal panel shown in FIG. 2 is equipped. FIG. 5 is an equivalent circuit diagram of the picture element shown in FIG. 4. It is explanatory drawing which shows the waveform of the output signal of the gate driver shown in FIG. FIG. 2 is an explanatory diagram showing voltage application timings for a source bus line and a gate bus line in the liquid crystal display device shown in FIG. 1. It is explanatory drawing which shows the example of the applied voltage to each pixel in the liquid crystal display device shown in FIG. 2 is a graph schematically showing voltage waveforms of respective parts when the power is turned off in the liquid crystal display device shown in FIG. 1. It is explanatory drawing which shows the structure of the power supply switching circuit with which the CS power supply circuit of the liquid crystal display device concerning Embodiment 2 of this invention is equipped. It is the graph which showed roughly the voltage waveform of each part at the time of power-off in the liquid crystal display device concerning Embodiment 2 of this invention. It is explanatory drawing which shows the structure of the power supply switching circuit with which the CS power supply circuit of the liquid crystal display device concerning Embodiment 3 of this invention is equipped. It is the graph which showed roughly the voltage waveform of each part at the time of power-off in the liquid crystal display device concerning Embodiment 3 of this invention. It is explanatory drawing which shows the structure of the pixel in the liquid crystal display device concerning Embodiment 4 of this invention. It is a transmission circuit diagram of the picture element with which the liquid crystal display device concerning Embodiment 4 of this invention is equipped. It is the graph which showed roughly the voltage waveform of each part at the time of power-off in the liquid crystal display device concerning Embodiment 4 of this invention. It is explanatory drawing which shows the off-leakage current characteristic according to the kind of TFT.

Embodiment 1
An embodiment of the present invention will be described.

  FIG. 1 is an explanatory diagram illustrating a schematic configuration of a liquid crystal display device 1 according to the present embodiment, and FIG. 2 is an explanatory diagram illustrating a configuration of a liquid crystal panel 20 provided in the liquid crystal display device 1.

  As shown in FIG. 2, the liquid crystal panel 20 is made of a TFT substrate 21 and a counter substrate 22 arranged to face each other via a spacer 23, and a liquid crystal material sealed between the TFT substrate 21 and the counter substrate 22. The liquid crystal layer 24, the first polarizing plate 25 disposed on the back side of the TFT substrate 21 (the side opposite to the side facing the counter substrate 22), and the surface side of the counter substrate 22 (with the TFT substrate 21) And a second polarizing plate 26 disposed on the surface opposite to the facing surface. A backlight 30 is disposed on the back side of the liquid crystal panel 20. The structure of the backlight 30 is not specifically limited, For example, the conventionally well-known backlight provided with the light source, the reflecting plate, and the 1 or several optical sheet can be used.

  The first polarizing plate 25 transmits only light having polarization according to the polarization axis direction of the first polarizing plate 25 among the light irradiated from the backlight 30. Further, a voltage corresponding to the image data is applied to the liquid crystal layer 24 of each picture element, whereby the birefringence of the liquid crystal in each picture element changes according to the image data, The polarization direction of the light passing through changes according to the image data. In addition, the second polarizing plate 26 transmits only light having polarization according to the polarization axis direction of the second polarizing plate 26 out of the light that has passed through the liquid crystal layer 24. As a result, the amount of light transmitted through the liquid crystal panel 20 is controlled for each picture element in accordance with the image data to display an image.

  In the region corresponding to each picture element (subpixel) in the counter substrate 22, any one of R (red), G (green), and B (blue) color filters is formed. One pixel is formed by a combination of the three B picture elements. As a result, the R, G, and B transmitted light amounts of each pixel are controlled for each pixel according to the image data, and an image according to the image data is displayed.

  FIG. 3 is an explanatory diagram showing a schematic configuration of the TFT substrate 21. As shown in this figure, on the TFT substrate 21, there are a large number of gate bus lines 31, a large number of source bus lines 32 arranged so as to intersect each gate bus line 31, the gate bus lines 31 and the source buses. A picture element 33 provided at each intersection with the line 32 is provided. Further, a CS wiring (auxiliary capacitance wiring) 38 that is substantially parallel to the gate bus line 31 is disposed in a region overlapping with each picture element 33 when viewed from the normal direction of the substrate surface. Each CS wiring 38 is connected to the CS power supply circuit 11 shown in FIG. 1 via a CS trunk wiring 38t.

  FIG. 4 is an explanatory diagram showing the picture element structure of the picture element 33 provided in the liquid crystal panel 20.

  As shown in FIG. 4, each picture element 33 includes a TFT (Thin Film Transistor) 34 as a switching element, a picture element electrode 35, and a counter electrode 36. The gate terminal of the TFT 34 is connected to the gate bus line 31, the source terminal is connected to the source bus line 32, and the drain terminal is connected to the pixel electrode 35. Further, a CS wiring 38 is provided so as to face the pixel electrode 35 with an insulating film (not shown) interposed therebetween. That is, in the present embodiment, a CS on common type liquid crystal panel 20 having a CS wiring 38 disposed so as to face each pixel electrode 35 is used.

  In the present embodiment, a TFT having a channel layer made of an indium gallium zinc oxide semiconductor (oxide semiconductor) is used as the TFT 34. However, the configuration of the TFT 34 is not limited to this. For example, a TFT 34 having a channel layer made of an oxide semiconductor other than an indium gallium zinc oxide semiconductor may be used. In addition, a material having a channel layer made of low-temperature polysilicon or the like may be used.

  Each gate bus line 31 is connected to the gate driver 4, each source bus line 32 is connected to the source driver 5, and each CS wiring 38 is connected to the CS power supply circuit 11 via a CS trunk wiring 38t. Has been. Further, the counter electrode 36 is connected to a counter power circuit 12 described later via a counter wiring (not shown) disposed on the counter substrate 22.

  At the time of image display, the gate driver 4 periodically switches the gate bus line 31 to be written, and the source driver 5 is connected to the gate bus line 31 selected as the write target in synchronization with the gate driver 4. An applied voltage corresponding to the gradation value of the image data is applied to the source bus line 32 corresponding to each picture element 33. As a result, a voltage corresponding to the image data is applied to the liquid crystal layer 24 of each picture element 33 to control the alignment direction of the liquid crystal molecules and display is performed.

  FIG. 5 is an equivalent circuit diagram of the picture element 33. When the potential of the gate terminal of the TFT 34 becomes higher than the potential of the source terminal of the TFT 34 by a predetermined value or more, the TFT 34 is turned on, a current flows between the source terminal and the drain terminal, and the potential of the source bus line 32 changes to the liquid crystal capacitance ( Applied to the liquid crystal layer 24). In the equivalent circuit diagram shown in FIG. 5, the pixel electrode 35, the counter electrode 36, and the liquid crystal layer 24 are represented as capacitors (liquid crystal capacitance). Further, as described above, the CS wiring 38 is provided at a position facing the pixel electrode 35 via an insulating layer (not shown), whereby the pixel electrode 35 and the CS wiring 38 are connected to each other. A liquid crystal auxiliary capacitance (coupling capacitance) 39 is formed therebetween. As shown in FIG. 5, the liquid crystal storage capacitor 39 is arranged in parallel with the liquid crystal capacitor (the pixel electrode 35, the liquid crystal layer 24, and the counter electrode 36), and corresponds to the image data applied to each pixel 33. It functions as a capacitor for holding the potential until the next voltage application (next frame).

  In the present embodiment, R, G, and B picture elements are provided. However, the present invention is not limited to this, and other color picture elements may be provided.

  As shown in FIG. 1, in addition to the liquid crystal panel 20 and the backlight 30, the liquid crystal display device 1 includes a timing controller 2, a gradation DAC (gradation digital-analog converter) 3, a gate driver 4, a source driver 5, and a gate. A power supply circuit 8, a source power supply circuit 9, a logic power supply circuit 10, a CS power supply circuit (auxiliary capacitor power supply circuit) 11, and a counter power supply circuit 12 are provided.

  The logic power supply circuit 10 converts an input potential Vin supplied from the outside into a potential corresponding to a driving voltage of a logic circuit (not shown) included in the timing controller 2, the gradation DAC 3, the gate driver 4, and the source driver 5. And output to each logic circuit.

  The gate power supply circuit 8 supplies driving power to the gate driver 4, converts the input potential Vin supplied from the outside into the high level side potential VGH of the gate driver 4 and supplies the gate driver 4 with the high level side A power supply circuit 8a and a low-level power supply circuit 8b that converts the low-level potential VGL and supplies the same to the gate driver 4 are provided. Note that the configurations of the high-level power supply circuit 8a and the low-level power supply circuit 8b are not particularly limited, and conventionally known power supply circuits can be used.

  The source power supply circuit 9 supplies driving power to the source driver 5, converts the input potential Vin supplied from the outside into the high level side potential VLS of the source driver 5 and supplies it to the source driver 5. A power supply circuit 9 a and a low-level power supply circuit 9 b that converts the low-level potential (in this embodiment, ground (GND) potential) and supplies the same to the source driver 5 are provided. Note that the high-level power supply circuit 9a also supplies analog power to the grayscale DAC 3. The low-level power supply circuit 9b also supplies power to the ground (GND) terminal of the grayscale DAC 3. In the present embodiment, the output potential from the low-level power supply circuit 9b to the source driver 5 is the ground potential. However, the present invention is not limited to this, and may be a potential lower than the ground potential, for example.

  The CS power supply circuit 11 converts an input potential Vin supplied from the outside into a predetermined CS potential (auxiliary capacitance potential) VCS and supplies it to each CS wiring 38 via a CS trunk wiring 38t. In the present embodiment, the CS potential during the power-on period (before starting the power-off operation) is set to 9V.

  The counter power supply circuit 12 converts the input potential Vin supplied from the outside into a predetermined counter potential VCOM (6 V in the present embodiment) and supplies it to each counter electrode 36.

  The timing controller 2 generates a control signal for controlling operations of the gate driver 4 and the source driver 5 based on image data input from the outside (for example, a control unit of the liquid crystal display device 1), and the gate driver 4 and the source Output to the driver 5.

  The gate driver 4 controls the voltage applied to each gate bus line 31 provided on the TFT substrate 21 of the liquid crystal panel 20 based on a control signal input from the timing controller 2, thereby writing a gate bus line to be written. 31 is switched periodically.

  FIG. 6 is a graph showing signal waveforms of the output signals OG (OG (0), OG (2),...) From the gate driver 4 to the gate bus lines 31. As shown in this figure, after the gate start pulse GSP is input from the timing controller 2, the gate driver 4 is supplied to the gate bus line 31 every time the gate clock signal GCK is input from the timing controller 2. High level voltage is applied sequentially. However, the driving waveform of the gate driver 4 is not limited to this, and a conventionally known driving method can be used.

  The gradation DAC 3 is used when the source driver 5 generates a voltage corresponding to the gradation value based on gradation reference data (output voltage value data) input from the outside (for example, the control unit of the liquid crystal display device 1). A gradation reference voltage to be used is generated and output to the source driver 5. The above gradation reference data is set, for example, at the time of production of the liquid crystal display device 1 so as to adjust the optimum gradation voltage variation caused by the stray capacitance of the picture element which is different for each liquid crystal panel.

  The source driver 5 applies to each source bus line 32 provided on the TFT substrate 21 of the liquid crystal panel 20 based on the control signal input from the timing controller 2 and the gradation reference voltage input from the gradation DAC 3. Control the voltage. Specifically, the source driver 5 applies a potential to be applied to each source bus line 32 (a potential to be applied to the writing target pixel 33 among the picture elements 33 connected to each source bus line 32). The generated potential is applied to each source bus line 32 at a timing synchronized with the switching operation of the gate bus line 31 to be written by the gate driver 4.

  FIG. 7 is an explanatory diagram showing the timing of voltage application to the source bus line 32 and the gate bus line 31. As shown in this figure, the source driver 5 outputs a potential for one gate bus line corresponding to the image data to each source bus line 32 at a timing corresponding to the latch pulse LS input from the timing controller 2. The gate driver 4 switches the supply voltage to the gate bus line 31 corresponding to the output of the source driver 5 to a high level at a timing synchronized with the output timing of the source driver 5. That is, n-th line data is output from the source driver 5 to each source bus line 32 during a period when the voltage of the n-th gate bus line 31 is at a high level. By sequentially performing this process for all the gate bus lines 31, a charge corresponding to the image data is charged to each picture element 33 to display one screen. The source driver 5 inverts the polarity of the output voltage to each source bus line 32 for each gate bus line based on the polarity inversion signal REV input from the timing controller 2.

  FIG. 8 is an explanatory diagram illustrating an example of a voltage waveform applied to each picture element 33 in the liquid crystal display device 1 according to the present embodiment. The gate waveform (VG) is a voltage applied to the gate terminal of the TFT 34, the source waveform (VS) is a voltage applied to the source terminal of the TFT 34, the counter potential is applied to the counter electrode 36, and the CS potential is CS wiring 38. The voltage applied to is shown.

  As shown in this figure, in this embodiment, the voltage applied to the gate terminal is set to 33V on the high level side and -9V on the low level side. As for the voltage applied to the source terminal, the maximum value (VH1023) in the case of + polarity is set to 15.6V, and the minimum value (VL1023) in the case of -polarity is set to 0V (GND potential). The counter potential is set to 6V, and the CS potential is set to 9V higher than the counter potential.

  As described above, the high-level voltage applied to the gate terminal is set sufficiently higher than the maximum value of the voltage applied to the source terminal so that the TFT 34 can be turned on regardless of the voltage applied to the source terminal. Has been. Further, the low-level voltage applied to the gate terminal is set sufficiently lower than the minimum value of the voltage applied to the source terminal so that the TFT 34 can be turned off regardless of the voltage applied to the source terminal. Yes. Accordingly, when the voltage applied to the gate terminal is at a high level, the TFT 34 is turned on, a current flows between the source terminal and the drain terminal, and the potential of the pixel electrode 35 is equal to the potential of the source bus line 32. Thus, writing to the picture element 33 is performed.

  FIG. 9 is a graph schematically showing the voltage waveform of each part when the power is off. As shown in this figure, when the power of the liquid crystal display device 1 is turned off, the voltage of each part is maintained by a capacitor or the like built in the liquid crystal display device 1 for a short period immediately after the power is turned off. It changes to potential.

  At this time, in the present embodiment, the CS potential VCS at the normal time (during the period when the power of the liquid crystal display device 1 is turned on) is set higher than the counter potential VCOM. The drop amount per unit time is larger than the drop amount per unit time of the counter potential VCOM. That is, the descending speed of the CS potential VCS becomes faster than the descending speed of the counter potential VCOM. Since the drop rate of the CS potential VCS is fast, the liquid crystal auxiliary capacitor 39 acts to maintain the potential difference between the electrode plates, so that the potential on the pixel electrode 35 side in the liquid crystal auxiliary capacitor 39 is lowered, thereby the pixel electrode. The potential of 35 drops.

  As a result, the potential difference between the gate and the source in the TFT 34 increases, the leakage current of the TFT 34 increases, and the charge accumulated in the picture element electrode 35 easily escapes to the source bus line 32.

  That is, as shown in FIG. 17 described above, the TFT has a characteristic that the leak current increases as the potential difference between the gate and the source increases. For this reason, by decreasing the potential of the pixel electrode 35 and increasing the potential difference between the gate and the source of the TFT 34, the leakage current of the TFT 34 can be increased and the charge of the pixel electrode 35 can be released to the source bus line 32. it can.

  As described above, in the liquid crystal display device 1 according to the present embodiment, the CS power supply circuit 11 causes the CS potential VCS during normal time (during the period when the power supply of the liquid crystal display device 1 is turned on) to be higher than the counter potential VCOM. Set high (set so that the potential difference from the ground potential is large).

  Thereby, when the power is turned off, the potential of the pixel electrode 35 can be lowered to increase the potential difference between the gate and the source of the TFT 34. Therefore, the leakage current of the TFT 34 is increased and the charge accumulated in the pixel electrode 35 is increased. It can escape to the source bus line 32. Therefore, it is possible to prevent problems such as burn-in due to the continued accumulation of charges in the pixel electrode 35 after the power is turned off.

  In particular, in the present embodiment, since a TFT made of an indium gallium zinc oxide semiconductor having a characteristic that the off-leakage current is very small is used as the TFT 34, charges tend to be accumulated in the pixel electrode 35 when the power is turned off. However, even when a TFT made of an indium gallium zinc oxide semiconductor is used, the charge accumulated in the pixel electrode 35 when the power is turned off can be reduced.

  In the present embodiment, the CS potential VCS at the normal time (when the power is turned on) is set to 9 V, and the counter potential VCOM is set to 6 V. However, the values of both these potentials are not limited to this, and at least the CS potential VCS is set. What is necessary is just to set suitably according to the characteristic etc. of the liquid crystal panel 20 so that the one may become higher than the opposing electric potential VCOM.

  In addition, in the conventional liquid crystal display device, for example, as in Patent Document 1 described above, a circuit that performs a process for removing charges from the pixel electrode when the power is turned off, and the circuit can be driven even when the power supply is cut off. Therefore, it is necessary to provide charging means such as a capacitor. On the other hand, according to the present embodiment, each picture is displayed when the power is turned off without providing the circuit and the charging means only by providing the CS power supply circuit 11 for setting the CS potential VCS higher than the counter potential VCOM. The elementary charge can be removed. Therefore, the manufacturing cost of the liquid crystal display device 1 can be reduced.

  However, in the liquid crystal display device 1 according to the present embodiment, the applied voltage at the time of driving is set as described above, and a circuit for performing processing for extracting charges from the pixel electrode when the power is turned off, and the circuit is supplied with power And charging means such as a capacitor for enabling driving even when the power is cut off, and each picture has a potential (ground potential or a potential close thereto) for reducing the charge accumulated in each picture element when the power is turned off. You may make it perform the process which writes in plain.

  In the present embodiment, the case where the liquid crystal display device 1 is a transmissive liquid crystal display device that performs display using light emitted from the backlight 30 is described, but the present invention is not limited to this. For example, a reflective liquid crystal display device that reflects incident light from the outside and uses it as display light may be used. The transflective liquid crystal display device has both the function of a transmissive liquid crystal display device and the function of a reflective liquid crystal display device. Type liquid crystal display device.

  In the present embodiment, the liquid crystal display device in which the pixel electrode is provided on the TFT substrate 21 and the counter electrode is provided on the counter substrate 22 has been described. However, the present invention is not limited thereto, and both the pixel electrode and the counter electrode are provided. The structure provided in the same board | substrate may be sufficient.

[Embodiment 2]
Another embodiment of the present invention will be described. For convenience of explanation, members having the same functions as those of the first embodiment are denoted by the same reference numerals as those of the first embodiment, and description thereof is omitted.

  In the first embodiment, the CS potential VCS during normal time (when the power is turned on) is set higher than the counter potential VCOM, so that the rate of decrease of the CS potential VCS when the power is off is faster than the rate of decrease of the counter potential VCOM. The configuration to be described has been described. On the other hand, in the present embodiment, the CS potential VCS and the counter potential VCOM are set to the same value during normal times (when the power is turned on), and the CS potential VCS is set when the power is turned off (during the power-off operation period). By switching to a potential lower than the counter potential VCOM, the rate of decrease of the CS potential VCS is made higher than the rate of decrease of the counter potential VCOM in at least a part of the period from the start to the end of the power-off operation.

  Specifically, the liquid crystal display device 1 according to the present embodiment includes a power supply switching circuit 110 a shown in FIG. 10 at the output stage of the CS power supply circuit 11.

  As shown in FIG. 10, the power supply switching circuit 110 a includes a voltage detection unit 111, a MOSFET 112, a resistor 113, and an operational amplifier 114.

  The voltage detector 111 is connected between the input power supply and the gate terminal G of the MOSFET 112, and controls the operation of the MOSFET 112 according to the input potential Vin (input power supply voltage). Specifically, the voltage detection unit 111 conducts between the source and drain of the MOSFET 112 when the input potential Vin is equal to or higher than a predetermined value, and the source and drain of the MOSFET 112 when the input potential Vin is lower than the predetermined value. The output voltage for the gate terminal G is controlled so as to interrupt the gap.

  A CS reference potential VCS_ref (in this embodiment, VCS_ref = VCOM) generated by the CS power supply circuit 11 is supplied to the source terminal S of the MOSFET 112, and the drain terminal D is connected to the input terminal of the operational amplifier 114. Therefore, when the input potential Vin is equal to or higher than a predetermined value, the CS reference potential VCS_ref is input to the operational amplifier 114. When the input potential Vin is less than a predetermined value, the source and drain of the MOSFET 112 are disconnected.

  One end of the resistor 113 is connected between the MOSFET 112 and the operational amplifier 114, and the other end is connected to the output side of the low-level power supply circuit 8 b (low potential supply source) of the gate driver 4.

  The operational amplifier 114 is a voltage follower circuit, and outputs the same potential as the input potential to the operational amplifier 114 to the CS trunk wiring 38t. Therefore, the output potential of the operational amplifier 114 is VCS_ref when the input potential Vin of the liquid crystal display device 1 is equal to or higher than a predetermined value, and is VGL when the input potential Vin is lower than the predetermined value.

  FIG. 11 is a graph schematically showing a change in potential of each part when the power is turned off when the CS reference potential VCS_ref is set to the same potential as the counter potential VCOM.

  As shown in this figure, the CS potential VCS is set to the same value as the counter potential VCOM (VCS_ref = VCOM) during the period in which the power source of the liquid crystal display device 1 is on, but the power source is turned off and the MOSFET 112 is turned on. When cut off, the CS potential VCS is lowered to the low level side potential VGL of the gate driver 4.

  At this time, the descending speed of the CS potential VCS becomes faster than the descending speed of the counter potential VCOM at least during the period when the MOSFET 112 is cut off and pulled down to VGL.

  For this reason, since the descending speed of the CS potential VCS is fast, the liquid crystal auxiliary capacitor 39 acts to maintain the potential difference between the electrode plates, and the potential on the pixel electrode 35 side in the liquid crystal auxiliary capacitor 39 is lowered. The potential decreases. As a result, the potential difference between the gate and the source in the TFT 34 increases, the leakage current of the TFT 34 increases, and the charge accumulated in the picture element electrode 35 easily escapes to the source bus line 32.

  As described above, in this embodiment, by switching the output potential for the CS trunk line 38t to a potential lower than the counter potential VCOM when the power is turned off, at least a part from the start of the power off operation to the completion of the power off operation is performed. The descending speed of the CS potential VCS in the period is made faster than the descending speed of the counter potential VCOM.

  As a result, as in the first embodiment, the potential difference between the gate and the source of the TFT 34 can be increased, and the charge of the pixel electrode 35 can easily escape to the source bus line 32.

  In the present embodiment, the low level side potential VGL of the gate driver 4 is inputted to the operational amplifier 114 when the power is turned off. However, the present invention is not limited to this, and at least a potential lower than the counter potential VCOM is inputted. Any configuration may be used. For example, the input side of the operational amplifier 114 may be connected to the ground (low potential supply source) when the power is turned off, or may be connected to various logic power supply circuits or the like (low potential supply source) whose output potential is lower than the counter potential VCOM. Good.

  In the present embodiment, the value of the CS potential VCS (VCS_ref) at the normal time (while the power is on) is set to the same value as the counter potential VCOM. However, the present invention is not limited to this. A value different from VCOM may be used. When the value of the CS potential VCS (VCS_ref) at the normal time is set to a value different from the counter potential VCOM, the potential input to the operational amplifier 114 when the MOSFET 112 is shut off when the power is turned off is the rate at which the CS potential VCS decreases. The connection destination (potential supply source for the operational amplifier 114) on the other end side of the resistor 113 may be selected so that becomes a potential that becomes faster than the decreasing speed of the counter potential VCOM.

[Embodiment 3]
Still another embodiment of the present invention will be described. For convenience of explanation, members having the same functions as those of the above-described embodiment are denoted by the same reference numerals as those of the embodiment, and description thereof is omitted.

  In the present embodiment, the CS potential VCS and the counter potential VCOM are set to the same value during normal times (during the period when the power of the liquid crystal display device 1 is turned on), and the CS potential VCS drops oppositely when the power is off. This is started at a timing earlier than the drop of the potential VCOM, thereby making the fall rate of the CS potential VCS faster than the fall rate of the counter potential VCOM in at least a part of the period from the start to the end of the power-off operation.

  Specifically, the liquid crystal display device 1 according to the present embodiment includes a power supply switching circuit 110b shown in FIG.

  As shown in FIG. 10, the power supply switching circuit 110 b includes a voltage detection unit 115, a MOSFET 116, a resistor 117, and an operational amplifier 118.

  The operational amplifier 118 is a voltage follower circuit, and outputs the same potential as the input potential to the operational amplifier 118. Further, the CS reference potential VCS_ref generated in the CS power supply circuit 11 (in this embodiment, VCS_ref = VCOM) is input to the input side of the operational amplifier 118. Therefore, the output potential of the operational amplifier 118 is VCS_ref.

  The voltage detector 115 is connected between the input power supply and the gate terminal G of the MOSFET 112, and controls the operation of the MOSFET 112 according to the input potential Vin (input power supply voltage). Specifically, the voltage detection unit 111 interrupts the source and drain of the MOSFET 112 when the input potential Vin is equal to or higher than a predetermined value, and the source and drain of the MOSFET 112 when the input potential Vin is lower than the predetermined value. The output voltage with respect to the gate terminal G is controlled so as to make the gap conductive.

  The source terminal S of the MOSFET 112 is connected to the ground, and the drain terminal D is connected between the output side of the operational amplifier 114 and the CS trunk line 38t via a resistor 117. Therefore, when the input potential Vin is greater than or equal to a predetermined value, the potential of the CS trunk line 38t becomes the CS reference potential VCS_ref output from the operational amplifier 114, and when the input potential Vin is less than the predetermined value, it becomes the ground potential.

  FIG. 13 is a graph schematically showing a change in potential of each part when the power is turned off when the CS reference potential VCS_ref is set to the same potential as the counter potential VCOM.

  As shown in this figure, while the power supply of the liquid crystal display device 1 is in the ON state, the CS potential VCS is set to VCS_ref having the same value as the counter potential VCOM. However, the voltage detection unit 115 reduces the input potential ( When the power supply of the liquid crystal display device 1 is detected and the MOSFET 116 is turned on, the CS potential VCS starts to drop toward the ground potential.

  At this time, the counter potential VCOM is maintained at the power-on potential by a capacitor or the like built in the liquid crystal display device 1 for a predetermined period immediately after the power is turned off, and thereafter starts to drop toward the ground potential.

  Therefore, the decrease in the CS potential VCS starts at a timing earlier than the decrease in the counter potential VCOM, and at least immediately after the decrease in the input potential Vin is detected, the decrease rate of the CS potential VCS decreases. Be faster than speed.

  For this reason, since the descending speed of the CS potential VCS is fast, the liquid crystal auxiliary capacitor 39 acts to maintain the potential difference between the electrode plates, and the potential on the pixel electrode 35 side in the liquid crystal auxiliary capacitor 39 is lowered. The potential decreases. As a result, the potential difference between the gate and the source in the TFT 34 increases, the leakage current of the TFT 34 increases, and the charge accumulated in the picture element electrode 35 easily escapes to the source bus line 32.

  As described above, in the present embodiment, at least the time from the start of the power-off operation to the completion of the power-off operation is generated by causing the fall start timing of the CS potential VCS to occur earlier than the start-up timing of the counter potential VCOM when the power is turned off. The falling speed of the CS potential VCS in a certain period is made faster than the falling speed of the counter potential VCOM.

  As a result, as in the first and second embodiments, the potential difference between the gate and the source of the TFT 34 can be increased, and the charge of the pixel electrode 35 can easily escape to the source bus line 32.

  In the present embodiment, the CS potential VCS value (VCS_ref) at the normal time (during the period when the power is turned on) is set to the same value as the counter potential VCOM. However, the present invention is not limited to this. A value different from VCOM may be used.

  In the present embodiment, the CS trunk line 38t is connected to the ground when the power is turned off. However, the present invention is not limited to this, and any structure may be used as long as it is connected to at least a potential source lower than the counter potential VCOM. For example, the CS trunk wiring 38t may be connected to various logic power supply circuits whose output potential is lower than the counter potential VCOM when the power is turned off.

[Embodiment 4]
Still another embodiment of the present invention will be described. For convenience of explanation, members having the same functions as those of the above-described embodiment are denoted by the same reference numerals as those of the embodiment, and description thereof is omitted.

  In each of the embodiments described above, the CS potential VCS is supplied from the CS power supply circuit 11 to the CS wiring 38. On the other hand, in the present embodiment, a CS on gate type liquid crystal panel 20 in which the CS wiring 38 is connected to the gate bus line 31 is used.

  FIG. 14 is an explanatory diagram showing the configuration of the picture element 33 of the liquid crystal panel 20 provided in the liquid crystal display device 1 according to the present embodiment, and FIG. 15 is an equivalent circuit diagram thereof.

  As shown in FIGS. 14 and 15, the CS wiring 38 is connected to the gate bus line 31 adjacent to the gate bus line 31 that drives the picture element 33 arranged to face the CS wiring 38. In the present embodiment, since the potential of the CS wiring 38 is controlled by the gate driver 4, the CS power supply circuit 11 is not provided.

  FIG. 16 is a graph schematically showing a change in potential of each part when the power is turned off in the liquid crystal display device 1 according to the present embodiment.

  As shown in FIG. 16, when the power of the liquid crystal display device 1 is turned off, the voltage of each part is maintained by a capacitor or the like built in the liquid crystal display device 1 for a short period immediately after the power is turned off. It changes to potential. In the present embodiment, the CS wiring 38 is connected to the gate bus line 31, and the high-level side potential VGH is supplied to each gate bus line 31 when the power is off.

  For this reason, since the CS potential VCH decreases from a potential higher than the counter potential VCOM toward the ground potential when the power is off, the rate of decrease of the CS potential VCS when the power is off is the counter potential as in the first embodiment. It becomes faster than the descending speed of VCOM. Since the drop in the CS potential VCS is fast, the liquid crystal storage capacitor 39 acts so as to maintain the potential difference between the electrode plates, and the potential on the pixel electrode 35 side in the liquid crystal storage capacitor 39 is lowered. Decreases.

  As a result, the potential difference between the gate and the source in the TFT 34 increases, the leakage current of the TFT 34 increases, and the charge accumulated in the picture element electrode 35 easily escapes to the source bus line 32.

[Summary]
The liquid crystal display device according to the first aspect of the present invention is provided for each of a plurality of gate bus lines, a plurality of source bus lines intersecting with the gate bus lines, and an intersection of the gate bus lines and the source bus lines. A pixel terminal, a gate terminal connected to the gate bus line, and a source terminal connected to the source bus line. A liquid crystal display device comprising: a switching element having a drain terminal connected to the picture element electrode; and an auxiliary capacity wiring that is arranged opposite to the picture element electrode and forms a liquid crystal auxiliary capacity with the picture element electrode And, during at least a part of the period from the start of the power-off operation to the completion of the power-off operation, the decreasing speed of the auxiliary capacitance potential, which is the potential of the auxiliary capacitance wiring, is Is characterized by faster than lowering speed of the opposing electric potential is the potential.

  According to the above configuration, since the potential of both electrodes (the pixel electrode and the auxiliary capacitance wiring) of the liquid crystal auxiliary capacitance changes so as to maintain the potential difference between the two electrodes, the picture can be obtained by rapidly reducing the auxiliary capacitance potential. The potential of the elementary electrode can be quickly reduced. As a result, since the potential difference between the gate terminal and the source terminal of the switching element can be increased, the leakage current of the switching element can be increased and the charge of the pixel electrode can be effectively released by the source bus line. This makes it possible to realize a liquid crystal display device with a simple configuration in which charges are not easily accumulated in the picture element when the power is turned off.

  The liquid crystal display device according to aspect 2 of the present invention has a configuration in the aspect 1, in which the auxiliary capacitance potential before the start of the power-off operation is set to a potential higher than the counter potential.

  According to the above configuration, since the auxiliary capacitance potential before the start of the power-off operation is set to a potential higher than the counter potential, the lowering speed of the auxiliary capacitance potential after the start of the power-off operation is higher than the lowering speed of the counter potential. Get faster. As a result, the potential of the pixel electrode is quickly lowered to increase the potential difference between the gate terminal and the source terminal of the switching element, and the leakage current of the switching element is increased to effectively charge the pixel electrode to the source bus line. Can escape.

  The liquid crystal display device according to aspect 3 of the present invention is the liquid crystal display device according to aspect 1, in which the auxiliary capacitance potential before the start of the power-off operation is set to the same potential as the counter potential or higher than the counter potential. The power supply switching circuit connects the auxiliary capacitance line to a low potential supply source that supplies a potential lower than the opposing potential in at least a part of the period from the start of the operation to the completion of the power off operation. .

  According to the above configuration, by connecting the auxiliary capacitance line to a low potential supply source that supplies a potential lower than the opposing potential during the power-off operation period, the auxiliary capacitance potential lowering speed is made higher than the opposing potential lowering speed. Can be fast. As a result, the potential of the pixel electrode is quickly lowered to increase the potential difference between the gate terminal and the source terminal of the switching element, and the leakage current of the switching element is increased to effectively charge the pixel electrode to the source bus line. Can escape.

  The liquid crystal display device according to aspect 4 of the present invention is the liquid crystal display device according to aspect 1, wherein the input power supply voltage is reduced to a predetermined value or less by the voltage detector that detects that the input power supply voltage has dropped to a predetermined value or less. And a power supply switching circuit that connects the auxiliary capacitance line to a low potential supply source that supplies a potential lower than the counter potential before the counter potential starts to drop after the detection. It is.

  According to the configuration described above, at least during the period from the start of the power-off operation to the start of the decrease in the counter potential, the storage capacitor potential can be decreased at a speed lower than that of the counter potential. As a result, the potential of the pixel electrode is quickly lowered to increase the potential difference between the gate terminal and the source terminal of the switching element, and the leakage current of the switching element is increased to effectively charge the pixel electrode to the source bus line. Can escape.

  The liquid crystal display device according to the fifth aspect of the present invention is the liquid crystal display device according to the first aspect, wherein the storage capacitor line is connected to the gate bus line. That is, the liquid crystal display device has a configuration in which each picture element has a CS on-gate structure.

  According to the above configuration, the rate of decrease of the auxiliary capacitance potential when the power is off can be made faster than the rate of decrease of the counter potential. As a result, the potential of the pixel electrode is quickly lowered to increase the potential difference between the gate terminal and the source terminal of the switching element, and the leakage current of the switching element is increased to effectively charge the pixel electrode to the source bus line. Can escape.

  In the liquid crystal display device of the present invention, the switching element according to any of the first to fifth aspects is a thin film transistor having a channel layer made of an oxide semiconductor.

  A thin film transistor including a channel layer made of an oxide semiconductor has a characteristic of extremely low off-leakage current, and a potential difference remains between a pixel electrode and a counter electrode when the power supply of the liquid crystal display device is turned off. In this case, the potential difference continues to be applied during the period when the power is turned off, so that problems such as burn-in are likely to occur.

  On the other hand, according to the above configuration, since the potential difference between the pixel electrode and the counter electrode accumulated when the power is turned off can be reduced, a thin film transistor including a channel layer made of an oxide semiconductor is used. Even so, it is possible to prevent the occurrence of defects such as image sticking due to a potential difference between the pixel electrode and the counter electrode.

  The present invention is not limited to the above-described embodiments, and various modifications can be made within the scope shown in the claims. That is, embodiments obtained by combining technical means appropriately modified within the scope of the claims are also included in the technical scope of the present invention.

  The present invention can be applied to a liquid crystal display device, and can be particularly preferably applied to a liquid crystal display device using a thin film transistor made of an oxide semiconductor or the like having a small off-leakage current as a switching element.

DESCRIPTION OF SYMBOLS 1 Liquid crystal display device 4 Gate driver 5 Source driver 8 Gate power supply circuit 8a High level side power supply circuit 8b Low level side power supply circuit 11 CS power supply circuit 12 Opposite power supply circuit 20 Liquid crystal panel 24 Liquid crystal layer 31 Gate bus line 32 Source bus line 33 Element 34 TFT (switching element)
35 picture element electrode 36 counter electrode 38 CS wiring 38t CS trunk wiring 39 liquid crystal auxiliary capacitance 110a, 110b power supply switching circuit 111, 115 voltage detection unit 112, 116 MOSFET
113,117 Resistance 114,118 Operational amplifier

Claims (6)

A plurality of gate bus lines, a plurality of source bus lines intersecting with the gate bus lines, and a picture element provided at each intersection of the gate bus line and the source bus line, The pixel electrode and the counter electrode arranged opposite to each other through the liquid crystal layer, the gate terminal is connected to the gate bus line, the source terminal is connected to the source bus line, and the drain terminal is connected to the pixel electrode. A liquid crystal display device comprising: a switching element; and an auxiliary capacitance line that is disposed opposite to the pixel electrode and forms a liquid crystal auxiliary capacitance with the pixel electrode,
During at least a part of the period from the start of the power-off operation to the completion of the power-off operation, the lowering speed of the auxiliary capacity potential that is the potential of the auxiliary capacity wiring is higher than the lowering speed of the counter potential that is the potential of the counter electrode. A liquid crystal display device characterized by being faster.   2. The liquid crystal display device according to claim 1, wherein the auxiliary capacitance potential before the start of power-off operation is set to a potential higher than the counter potential. The auxiliary capacitance potential before the start of the power-off operation is set to the same potential as the counter potential or higher than the counter potential,
Provided with a power supply switching circuit that connects the auxiliary capacitance wiring to a low potential supply source that supplies a potential lower than the opposing potential during at least a part of the period from the start of the power off operation to the completion of the power off operation. The liquid crystal display device according to claim 1. A voltage detector that detects that the input power supply voltage has dropped below a predetermined value;
After the voltage detection unit detects that the input power supply voltage has dropped below a predetermined value, the auxiliary capacitance wiring is supplied with a potential lower than the opposing potential before the opposing potential starts to drop. The liquid crystal display device according to claim 1, further comprising a power supply switching circuit connected to a supply source.   The liquid crystal display device according to claim 1, wherein the auxiliary capacitance line is connected to the gate bus line.   6. The liquid crystal display device according to claim 1, wherein the switching element is a thin film transistor having a channel layer made of an oxide semiconductor.

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