JP2008096861A - Active matrix type display device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an active matrix type liquid crystal display device which does not require enhancement of withstand-voltage design of a source driver, by using a simple constitution without changing the constitution of a pixel formation part or the like, for example. <P>SOLUTION: The active matrix type liquid crystal display device adds up an output voltage from a source driver 300 and an offset voltage from a first or second offset signal producing circuit 601, 602 on liquid crystal signal producing circuits 701 to 704 which incorporate charge pumping circuits containing prescribed capacitances and applies the sum of them to respective image signal lines SL(1) to SL(M) corresponding to the liquid crystal signal producing circuits 701 to 704. The offset voltage is a voltage in the range where light transmittance of liquid crystal hardly varies and a voltage obtained by subtracting the offset voltage from the voltage to be applied to the respective image signal lines suffices the output voltage from the source driver 300. As the result, the voltage-proof design of the source driver 300 can be suppressed low by using the simple constitution of attaching the circuit described above. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to an active matrix display device such as a liquid crystal display device using a switching element such as a thin film transistor.

  In general, an active matrix liquid crystal display device includes a display unit including two substrates sandwiching a liquid crystal layer, and one of the two substrates has a plurality of data as video signal lines. Lines and a plurality of gate lines as scanning signal lines are arranged in a lattice pattern, and a plurality of pixel formation portions are provided that are arranged in a matrix corresponding to the intersections of the plurality of data lines and the gate lines. Yes. Each pixel formation portion constitutes a display portion of the device. A TFT (Thin Film Transistor) which is a switching element in which a gate terminal is connected to a gate line and a source terminal is connected to a data line, and the TFT And a pixel electrode connected to the drain terminal. The substrate including these pixel formation portions is called a TFT substrate. The other substrate facing the TFT substrate out of the two substrates has a common electrode which is a common electrode provided in common for the plurality of pixel forming portions, and a color filter for forming a display color. (CF: Color Filter). This substrate is called a CF substrate.

  Such an active matrix liquid crystal display device includes a source driver for driving the data line of the display portion, a gate driver for driving the gate line of the display portion, and a common electrode driving circuit for driving the common electrode, , A source driver, a gate driver, and a display control circuit for controlling the common electrode driving circuit.

  In such an active matrix liquid crystal display device, the polarity of the voltage applied to the liquid crystal layer is generally inverted every frame period. This is because it is necessary to perform AC driving in order to prevent deterioration of the liquid crystal. In order to improve display quality, there is a line inversion driving method in which voltages having different polarities are applied every horizontal period as this AC driving method. However, in this line inversion driving method, a voltage having the same polarity is applied to pixel forming portions (specifically, pixel electrodes) arranged in the row direction (horizontal scanning direction), so that the display quality is deteriorated. In recent years, therefore, an active matrix liquid crystal display device often employs a dot inversion driving method in which voltages having different polarities are applied to each dot (each pixel forming portion in the horizontal scanning direction).

  FIG. 12 is a diagram simply showing a voltage change of a certain data line when this dot inversion driving method is adopted. Note that an active matrix liquid crystal display device that employs this driving method includes four gate lines and four data lines. As shown in FIG. 12, in one vertical period (one frame period) for displaying one image, the polarity of the applied voltage is inverted every horizontal period. That is, the positive polarity applied voltage Vp is applied to the data line in the first one horizontal period, the negative polarity applied voltage Vn is applied in the next one horizontal period, and the positive polarity applied voltage Vp and the negative polarity applied voltage are repeatedly applied. After the application of Vn, in the subsequent vertical period, these polarities are inverted, and the negative polarity applied voltage Vn and the positive polarity applied voltage Vp are repeatedly applied.

  FIG. 13 is a diagram showing the polarity of the voltage applied to each pixel forming portion by the dot inversion driving method as described above. As shown in FIG. 13, voltages having different polarities are applied to each pixel forming portion for each dot in a certain vertical period, and these applied voltages are inverted in the subsequent one vertical period. I understand.

  However, if this dot inversion driving method is employed, it becomes necessary to generate the positive polarity applied voltage Vp and the negative polarity applied voltage Vn as shown in FIG. 13, leading to a higher voltage of the source driver. That is, in an ordinary twisted nematic liquid crystal, an effective voltage of 5 Vrms is normally required for image display, and thus a voltage of 10 Vpp that is twice that of the effective voltage is required for AC driving. Therefore, a source driver for outputting this voltage requires a power supply of 10 V or higher and a withstand voltage. This causes problems such as an increase in the area of the internal transistor by increasing the withstand voltage design as compared with a general source driver operating at 5 V and an increase in chip cost due to the introduction of a high withstand voltage process.

In order to solve such a problem, various methods have been tried conventionally. For example, two source lines are alternately connected to one pixel formation unit for each frame period via different switching elements, and There is a conventional active matrix liquid crystal display device that lowers the breakdown voltage of a source driver by a configuration in which voltages having different polarities are fixedly applied to the two source lines by a source driver (see, for example, Patent Document 1).
JP 2000-20033 A

  However, in the conventional active matrix type liquid crystal display device, the number of switching elements and source lines in the pixel formation portion increases, and the configuration becomes complicated. Therefore, particularly in a high-definition display device (having a large number of pixels). The manufacturing cost is greatly increased.

  Accordingly, an object of the present invention is to provide an active matrix liquid crystal display device that does not require a high breakdown voltage design of a source driver with a simple configuration without changing the configuration of, for example, a pixel formation portion.

1st invention was provided in the several pixel formation part arrange | positioned at the display part for displaying an image corresponding to the cross | intersection part of several video signal lines and several scanning signal lines, respectively. A pixel electrode; a common electrode provided corresponding to the pixel electrode for applying a voltage between the pixel electrode; a common electrode driving circuit for applying a predetermined voltage to the common electrode; and the image A video signal line driving circuit that receives an image signal and applies a voltage to the plurality of video signal lines according to the image signal, a scanning signal line driving circuit that selectively drives the plurality of scanning signal lines, and the video signal An active matrix display device comprising a line drive circuit and a display control circuit for controlling the scanning signal line drive circuit,
The video signal line driving circuit includes:
A voltage signal whose polarity is reversed every predetermined period between positive and negative voltages which are predetermined two kinds of voltages applied to the pixel electrode with reference to the potential of the common electrode. A source driver that outputs a voltage signal obtained by subtracting a predetermined offset voltage from a voltage corresponding to the image signal;
An offset voltage generation circuit for generating the offset voltage;
A voltage corresponding to the image signal is generated by adding the offset voltage generated by the offset voltage generation circuit to a voltage signal output from the source driver, and the generated voltage is used as the plurality of videos. And a plurality of signal generation circuits applied to the signal lines.

According to a second invention, in the first invention,
The offset voltage generation circuit generates, as the offset voltage, a predetermined voltage within a range in which light transmittance hardly changes when applied from zero to a liquid crystal layer provided between the pixel electrode and the common electrode. It is characterized by.

According to a third invention, in the first invention,
The signal generation circuit includes:
One of the two electrodes is connected to the source driver, the other electrode is connected to the offset voltage generation circuit, and the source is changed by changing the potential of the other electrode by the offset voltage. A capacity charged with an addition voltage obtained by adding the offset voltage to the voltage output from the driver;
The source driver and the capacitor are connected or disconnected so that the added voltage is charged with respect to the capacitor, and the corresponding video signal line and the capacitor are connected so that the added voltage charged to the capacitor is applied. And switching means for connecting or disconnecting.

According to a fourth invention, in the third invention,
The capacitor has a capacitance value larger than a parasitic capacitance value parasitic on a corresponding video signal line.

According to a fifth invention, in the third invention,
The switching means has a time for connecting the source driver and the capacitor so that the added voltage is charged with respect to the capacitor, and a corresponding video signal line so that the added voltage charged in the capacitor is applied. And the capacity is longer than the connection time.

According to a sixth invention, in the third invention,
The capacity is
One of the two electrodes is connected to the source driver, the other electrode is connected to the offset voltage generation circuit, and the potential of the other electrode is set to a positive offset voltage of the offset voltage. By changing only the positive polarity capacitance charged with the positive addition voltage obtained by adding the positive polarity offset voltage to the voltage output from the source driver,
One of the two electrodes is connected to the source driver, the other electrode is connected to the offset voltage generation circuit, and the potential of the other electrode is set to the negative offset voltage of the offset voltage. A negative capacity capacitor charged with a negative addition voltage obtained by adding the negative offset voltage to the voltage output from the source driver,
The switching means is
The source driver and the positive capacitor are connected or disconnected so that the positive additive voltage is charged with respect to the positive capacitor, and the negative additive voltage is charged to the negative capacitor. Positive polarity switching means for connecting or disconnecting the corresponding video signal line and the positive capacitance so that the positive addition voltage charged in the positive capacitance is applied;
The source driver and the negative capacity capacitor are connected or disconnected so that the negative capacity voltage is charged with respect to the negative capacity, and the negative capacity voltage is charged when the positive capacity voltage is charged to the local capacity. Negative polarity switching means for connecting or disconnecting the corresponding video signal line and the negative capacitance so that the negative addition voltage charged in the negative capacitance is applied.

According to a seventh invention, in the third invention,
The signal generation circuit may connect a potential of the video signal line to a predetermined voltage less than a maximum withstand voltage of the source driver before connecting the corresponding video signal line and the capacitor so that the addition voltage is applied by the switching unit. It further includes connection potential setting means for setting the potential.

In an eighth aspect based on the seventh aspect,
The connection potential setting means sets the potential of the video signal line to the potential of the common electrode by connecting the video signal line and the common electrode.

According to a ninth invention, in any one of the first to eighth inventions,
In the source driver, the polarities of voltages applied to adjacent video signal lines by n (n is a natural number) are opposite to each other, and the polarity is reversed every m (m is a natural number) horizontal periods. Output voltage signal,
The common electrode driving circuit applies a fixed predetermined voltage in the vicinity of a midpoint voltage of the positive and negative voltages to the common electrode.

According to a tenth aspect of the present invention, a display unit for displaying an image is provided in a plurality of pixel formation units arranged in a matrix corresponding to intersections of a plurality of video signal lines and a plurality of scanning signal lines. A display method for an active matrix display device comprising: a pixel electrode; and a common electrode provided corresponding to the pixel electrode for applying a voltage between the pixel electrode,
A common electrode driving step of applying a predetermined voltage to the common electrode;
A video signal line driving step of receiving an image signal representing the image and applying a voltage to the plurality of video signal lines according to the image signal;
A scanning signal line driving step for selectively driving the plurality of scanning signal lines,
The video signal line driving step includes:
A voltage signal whose polarity is reversed every predetermined period between positive and negative voltages which are predetermined two kinds of voltages applied to the pixel electrode with reference to the potential of the common electrode. A source driving step of outputting a voltage signal obtained by subtracting a predetermined offset voltage from a voltage corresponding to the image signal;
An offset voltage generating step for generating the offset voltage;
A voltage corresponding to the image signal is generated by adding the offset voltage generated in the offset voltage generation step to the voltage signal output in the source driving step, and the generated voltage is set to the plurality of voltages. And a signal generating step applied to the video signal line.

  According to the first aspect of the invention, for example, a simple configuration in which the offset voltage from the offset voltage generation circuit is added to the output voltage from the source driver by the signal generation circuit without changing the configuration of the pixel formation unit, for example. Thus, the withstand voltage design of the source driver can be lowered.

  According to the second aspect, even when the offset voltage is set, the source driver has a low withstand voltage design while maintaining the state in which the light transmittance of the liquid crystal layer sufficiently changes according to the change in the output voltage from the source driver. can do.

  According to the third aspect of the present invention, the withstand voltage design of the source driver can be lowered with a simple configuration in which the added voltage is charged with respect to the capacitance by the connection and disconnection operations by the switching means included in the signal generation circuit.

  According to the fourth aspect of the invention, a sufficient voltage corresponding to the image signal can be applied to the corresponding video signal line without being affected by the parasitic capacitance value of the video signal line.

  According to the fifth aspect, since the charge necessary for the capacitor is charged, it is possible to avoid the shortage of the voltage applied to the video signal line due to the shortage of the charging time.

  According to the sixth aspect of the invention, when one of the positive polarity capacitor and the negative polarity capacitor is charged by the positive polarity switching unit and the negative polarity switching unit, the other is connected to the video signal line. The voltage can be applied to the video signal line for a period twice as long as that of the one configuration. Therefore, a sufficient video signal application time (pixel value writing time) can be secured in each pixel formation portion even in a high-definition display device.

  According to the seventh aspect, the connection potential setting means can prevent the source driver from being applied with a voltage greater than its maximum breakdown voltage.

  According to the eighth aspect of the invention, the driving load on the capacitor applied to the source driver can be reduced by setting the potential of the capacitor to the potential of the common electrode.

  According to the ninth aspect of the invention, in a source driver that employs a so-called dot inversion driving method, it is possible to keep the breakdown voltage design generally required to be low.

  According to the tenth aspect, the same effect as that of the first aspect can be achieved in the display method.

  Hereinafter, the configuration and operation of an active matrix liquid crystal display device according to each embodiment of the present invention will be described with reference to the accompanying drawings.

<1. First Embodiment>
<1.1 Overall Configuration and Operation of Liquid Crystal Display>
FIG. 1 is a block diagram showing the overall configuration of an active matrix liquid crystal display device according to a first embodiment of the present invention. This liquid crystal display device includes a source driver (data driver) 300 and a gate driver (scanning signal line drive circuit) 400, a first offset signal generation circuit 601 that outputs a first offset signal OS1 having a predetermined offset voltage, and A second offset signal generation circuit 602 for outputting a second offset signal OS2 having a predetermined offset voltage having a polarity opposite to that of the first offset signal OS1 (referenced to a predetermined midpoint potential); Liquid crystal signal generation circuits 701 to 704, a display control circuit 100 for controlling them, and a display unit 500.

  The display unit 500 includes a plurality (M) of video signal lines SL (1) to SL (M), a plurality (N) of scanning signal lines GL (1) to GL (N), and a plurality of these. A plurality of (M × N) pixels provided corresponding to the intersections of the video signal lines SL (1) to SL (M) and the plurality of scanning signal lines GL (1) to GL (N), respectively. The pixel forming portion corresponding to the intersection of the scanning signal line GL (n) and the video signal line SL (m) is indicated by the reference symbol “P (n, m)”. ), As shown in FIG. 2 and FIG. Here, FIG. 2 schematically shows a configuration of the display unit 500 in the present embodiment, and FIG. 3 shows an equivalent circuit of the pixel formation unit P (n, m) in the display unit 500.

  As shown in FIG. 2 and FIG. 3, each pixel forming portion P (n, m) has a video signal passing through the intersection while the gate terminal is connected to the scanning signal line SL (n) passing through the corresponding intersection. The TFT 10 which is a switching element having a source terminal connected to the line SL (m), the pixel electrode Epix connected to the drain terminal of the TFT 10, and the plurality of pixel formation portions P (i, j) (i = 1) ˜N, j = 1 to M) and a common electrode (also referred to as “counter electrode”) Ecom, and the plurality of pixel formation portions P (i, j) (i = 1 to N, j). = 1 to M) and a liquid crystal layer as an electro-optic element sandwiched between the pixel electrode Epix and the common electrode Ecom.

  Note that each pixel formation portion P (n, m) shown in FIG. 2 is labeled with “+” or “−”. It indicates whether the potential is positive or negative with respect to the common electrode Ecom. As shown in FIG. 2, “+” and “+” both in the direction along the video signal lines SL (1) to SL (M) and in the direction along the scanning signal lines GL (1) to GL (N). The symbols “−” are alternately arranged, and these symbols are inverted every frame. Thus, this display device employs a dot inversion driving method similar to that of the conventional display device shown in FIG. 13, for example.

  In each pixel forming portion P (n, m), a liquid crystal capacitor Clc is formed by the pixel electrode Epix and a common electrode Ecom that faces the pixel electrode Epix across the liquid crystal layer, and an auxiliary capacitor Cs is formed in the vicinity thereof. .

  When the scanning signal G (n) applied to the scanning signal line GL (n) becomes active, the TFT 10 is selected and becomes conductive. The drive video signal S (m) is applied to the pixel electrode Ep via the video signal line SL (m). As a result, the voltage of the applied drive video signal S (m) (voltage based on the potential of the common electrode Ecom) is set as a pixel value in the pixel formation portion P (n, m) including the pixel electrode Ep. Written.

  The display control circuit 100 receives a display data signal DAT and a timing control signal TS sent from the outside, and controls a digital image signal DV, a source start pulse signal SSP for controlling the timing of displaying an image on the display unit 500, a source A clock signal SCK, a latch strobe signal LS, a gate start pulse signal GSP, a gate clock signal GCK, a control signal CS for controlling the first and second offset signal generation circuits 601 and 602, and a liquid crystal signal generation circuit 701 Switch control signals SWa to SWd for controlling switches to be described later included in ˜704 and a control signal φ for operating or stopping the common electrode drive circuit 200 are output.

  The common electrode driving circuit 200 applies a voltage signal having a predetermined common electrode potential Vcom to the common electrode in response to the control signal φ from the display control circuit 100. Note that the common electrode potential Vcom is constant, and the polarity of the voltage applied to each video signal line greatly changes between positive polarity and negative polarity, as described above with reference to FIG.

  The source driver 300 receives the digital image signal DV, the source start pulse signal SSP, the source clock signal SCK, and the latch strobe signal LS output from the display control circuit 100, and the video signals D (1) to D (m) before the offset. ) Is generated. Hereinafter, the video signals D (1) to D (m) before the offset are simply referred to as video signals D (1) to D (m) and are distinguished from the driving video signals S (1) to S (m).

  The video signals D (1) to D (m) are applied to the video signal lines SL (1) to SL (M) to charge the pixel capacities of the pixel forming portions P (n, m) in the display unit 500. This is a voltage signal obtained by subtracting a predetermined offset voltage from the voltage of the driving video signals S (1) to S (m) for the purpose. In this way, the source driver 300 only needs to generate a voltage signal from which the offset voltage has been subtracted, so that the withstand voltage design is made lower than the conventional configuration that generates the drive video signal itself (designed on the assumption of a low withstand voltage). Manufacturing cost can be reduced. Hereinafter, the reason why the offset voltage can be subtracted will be described with reference to FIG.

  FIG. 4 is a diagram showing the relationship between the voltage applied to the liquid crystal used in the display device and the luminance. As shown in FIG. 4, this liquid crystal is a normally white liquid crystal having the highest luminance (specifically, light transmittance) when no voltage is applied (center of the figure). Here, when a predetermined positive offset voltage VoP or a predetermined negative offset voltage VoN is applied to the liquid crystal, the luminance of the liquid crystal hardly changes. That is, the positive offset voltage VoP and the negative offset voltage VoN are predetermined voltages (maximum values in the drawing) within a range where the light transmittance hardly changes when applied to the liquid crystal layer from zero.

On the other hand, a voltage obtained by adding a predetermined positive video signal voltage VsP (the maximum value is shown in the figure) to the positive offset voltage VoP is applied, or a predetermined negative video signal voltage is added to the negative offset voltage VoN. When a voltage plus VsN (the maximum value is shown in the figure) is applied, the luminance of the liquid crystal changes. Therefore, the source driver 300 generates a video signal from which the positive offset voltage VoP or the negative offset voltage VoN has been subtracted, and the positive offset voltage generated by the first and second offset signal generation circuits 601 and 602 as will be described later. If the driving video signal is generated by adding VoP or the negative offset voltage VoN to the video signal, the state in which the light transmittance of the liquid crystal layer sufficiently changes according to the change of the output voltage from the source driver 300 is maintained. Meanwhile, the withstand voltage design of the source driver 300 can be lowered.

  Since the withstand voltage design of the source driver 300 has to be increased as the absolute values of the positive offset voltage VoP and the negative offset voltage VoN become smaller, these offset voltages hardly change the light transmittance of the liquid crystal layer as described above. The maximum value of the voltages within the range is very suitable. However, if these offset voltages are within a voltage range where the voltage is larger than zero and the light transmittance of the liquid crystal layer hardly changes, it is preferable because the withstand voltage design of the source driver 300 can be kept low.

  Note that the source driver 300 sequentially holds the digital image signal DV indicating the voltage to be applied to each of the video signal lines SL (1) to SL (M) at the timing when the pulse of the source clock signal SCK is generated. The held digital image signal DV is converted into an analog voltage at the timing when the pulse of the latch strobe signal LS is generated. The converted analog voltage is added with a predetermined offset voltage by liquid crystal signal generation circuits 701 to 704, which will be described later, and applied to all the video signal lines SL (1) to SL (M) all at once. That is, in the present embodiment, the line sequential driving method is adopted as the driving method of the video signal lines SL (1) to SL (M).

  The gate driver 400 applies an active scanning signal to each of the scanning signal lines GL (1) to GL (N) based on the gate start pulse signal GSP and the gate clock signal GCK output from the display control circuit 100.

  As described above, the driving video signal is applied to the video signal lines SL (1) to SL (M) and the scanning signal is applied to the scanning signal lines GL (1) to GL (N). The image is displayed on the display unit 500. The common electrode Ecom is supplied with a predetermined voltage by a power supply circuit (not shown) and is held at the common electrode potential Vcom.

  Next, the configuration and operation of the liquid crystal signal generation circuits 701 to 704 will be described in detail. Note that the liquid crystal signal generation circuit 703 has the same configuration as the liquid crystal signal generation circuit 701, and the liquid crystal signal generation circuits 702 and 704 receive the second offset signal OS2 from the second offset signal generation circuit 602, except for the liquid crystal signal. Since the configuration is the same as that of the generation circuit 701, the liquid crystal signal generation circuit 701 will be described in detail below, and the description of the liquid crystal signal generation circuits 702 to 704 is omitted.

<1.2 Configuration and Operation of Liquid Crystal Signal Generation Circuit>
FIG. 5 is a circuit diagram showing a configuration of the liquid crystal signal generation circuit 701 in the present embodiment. The liquid crystal signal generation circuit 701 is a circuit for adding and outputting the voltage of the first offset signal OS1 from the first offset signal generation circuit 601 and the video signal D (1) from the source driver 300. The first switch 710a, the second switch 710b, the third switch 710c, the fourth switch 710d, and the driving video signal S (1) that is sufficiently larger than the parasitic capacitance of the video signal line SL (1) are output. And a capacitor 715 having a sufficient capacity to do this. Note that the capacitance Csl (1) shown in the figure indicates the capacitance between the video signal line SL (1) and the common electrode Ecom.

  The first switch 710a makes its both ends conductive or interrupted by the first switch control signal SWa from the display control circuit 100, and the second switch 710b makes its both ends conductive by the second switch control signal SWb. The third switch 710c makes its both ends conductive or cuts off by the third switch control signal SWc, and the fourth switch 710d has its both ends made by the fourth switch control signal SWd. Is turned on or off. A so-called charge pump operation is performed by these switches and the capacitor 715. Hereinafter, the operation of the liquid crystal signal generation circuit 701 including this operation and related circuits will be described in detail with reference to FIG.

  FIG. 6 is a diagram simply showing waveforms of various signals including the switch control signal. In FIG. 6, the potential change of each signal during one horizontal period consisting of four periods T1 to T4 and the next one horizontal period consisting of four periods T5 to T8 follows (ignoring various impedances, etc.). It is shown simply).

  First, in the period T1, the potential of the first switch control signal SWa is an ON potential ON for turning on the first switch 710a (conducting both ends). Similarly, the potential of the third switch control signal SWc is also the ON potential ON. The potentials of the second and fourth switch control signals SWb and SWd are off potentials OFF for turning off the switches (cutting off the conduction at both ends). Further, in this period T1, the potential Vc between the first switch 710a and the capacitor 715 (hereinafter referred to as a capacitance potential) Vc shown in FIG. 5 is electrically connected to the first switch 710a and the third switch 710c. The video signal D (1) has the same potential, that is, a positive video signal potential Vsig_P that is higher than the midpoint potential V_center of the positive polarity applied voltage and the negative polarity applied voltage by the positive video signal voltage VsP. At this time, the first offset signal OS1 is a negative offset signal potential VoffN that is lower than the midpoint potential V_center by a positive offset voltage VoP.

  Next, in the period T2, the potentials of the first and third switch control signals SWa and SWc are changed from the ON potential ON to the OFF potential OFF, and the potentials of the second and fourth switch control signals SWb and SWd remain OFF. And conduction in all switches is interrupted. In this state, the first offset signal OS1 changes only from the negative offset signal potential VoffN to the midpoint potential V_center by a positive offset voltage VoP. Accordingly, the capacitance potential Vc is also positive from the potential V_center in accordance with this potential change. Only the positive offset voltage VoP is changed from the positive video signal potential Vsig_P which is higher by the video signal voltage VsP. Therefore, the capacitance potential Vc is higher by a voltage obtained by adding the positive video signal voltage VsP and the positive offset voltage VoP from the midpoint potential V_center.

  Subsequently, in the period T3, the potentials of the first and second switch control signals SWa and SWb are changed from the OFF potential OFF to the ON potential ON, and the potentials of the third and fourth switch control signals SWc and SWd remain OFF. Therefore, the capacitor 715 and the video signal line SL (1) are brought into conduction through the first and second switches 710a and 710b, and the potential of the video signal line SL (1) becomes equal to the capacitance potential Vc. That is, since the capacitor 715 has a sufficient capacity to output the driving video signal S (1) that is sufficiently larger than the parasitic capacitance of the video signal line SL (1), the liquid crystal signal generation circuit 701 causes the video signal line to be output. A driving video signal S (1) having a voltage obtained by adding a positive video signal voltage VsP and a positive offset voltage VoP is applied to SL (1).

  The voltage applied as the video signal for driving is applied to the corresponding pixel formation portion P (via the TFT 10 that is turned on by application of the scanning signal G (1) activated by the gate driver 400 in this period T3. 1, 1) is applied to the pixel electrode Epix and held in the pixel capacitance of the pixel formation portion. In this way, the holding voltage in the pixel capacitor is applied to the liquid crystal and the light transmittance in the display unit 500 is controlled, so that an image is displayed.

  Next, in the period T4, the potentials of the first and second switch control signals SWa and SWb remain on, and the third switch control signal SWc remains off, and the fourth switch control signal SWd Since the potential is changed from the OFF potential OFF to the ON potential ON, the capacitor 715 and the video signal line SL (1) are connected to the common electrode Ecom, and these potentials become a midpoint potential V_center substantially equal to the potential of the common electrode. . With this operation, it is possible to prevent the source driver 300 from being applied with a voltage exceeding the maximum withstand voltage value.

  In order to prevent the source driver 300 from being applied with a voltage higher than the maximum withstand voltage value, the potential of the video signal line may be set to be equal to or lower than the maximum withstand voltage value. The configuration is not limited as long as it is a well-known means, and for example, it can be realized by setting these potentials to the ground potential GND by connection potential setting means for grounding the capacitor 715 and the video signal line SL (1). However, in this case, the source driver 300 must apply a voltage to the capacitor 715 from the ground potential GND, and a driving load is applied. Therefore, the above configuration with the midpoint potential V_center is preferable from the viewpoint of reducing power consumption and the like.

  Subsequently, since the operations in the periods T5 to T8 are the same as those in the periods T1 to T4, a detailed description thereof will be omitted. However, since the display device adopts the dot inversion driving method, the driving video signal S (1 ) (With reference to the midpoint potential V_center) needs to be inverted. Therefore, by changing the potential of the first offset signal OS1 in the negative direction in the period T6, the capacitance potential Vc is also changed to the midpoint The negative video signal potential Vsig_N that is lower than the potential V_center by the negative video signal voltage VsN further changes by the negative offset voltage VoN. That is, in the period T6, the capacitor potential Vc is lower by a voltage obtained by adding the negative video signal voltage VsN and the negative offset voltage VoN to the midpoint potential V_center. As described above, this potential becomes the potential of the video signal line SL (1) in the period T7.

  As shown in FIG. 6, the common electrode potential Vcom is strictly set to a potential lower than the midpoint potential V_center by a predetermined compensation voltage α. This compensation voltage α is for compensating for a voltage that changes due to the wiring capacitance or the parasitic capacitance of the TFT 10 when the TFT 10 is turned off from the voltage written in the liquid crystal layer when the TFT 10 is turned on.

  The operation of the liquid crystal signal generation circuit 701 as described above is the same in other liquid crystal signal generation circuits that receive the first offset signal OS1 from the first offset signal generation circuit 601, for example, the liquid crystal signal generation circuit 703. In this regard, the operation of the liquid crystal signal generation circuit that receives the second offset signal OS2 from the second offset signal generation circuit 602, for example, the liquid crystal signal generation circuits 702 and 704 is not the same as the above operation. However, since this operation may be performed so that the polarities of adjacent video signal lines are inverted in order to realize the dot inversion driving method, this operation is eventually performed from the period T1 to T4 in the liquid crystal signal generation circuit 701 described above. Each signal in a certain horizontal period and the operation based thereon can be realized by replacing each signal and the operation based thereon in the subsequent horizontal period consisting of periods T5 to T8. Therefore, detailed description of this operation is omitted.

<1.3 Effect>
As described above, in the liquid crystal display device according to the first embodiment, the first and second offset signal generation circuits 601, 601, 704, 704, 704, 704, 704, 704, 704, 704, 704, 704, 704,. By adding (combining) the voltage of the offset signal from 602 to the voltage of the output signal from the source driver 300, the withstand voltage design of the source driver 300 can be lowered with a simple configuration.

<2. Second Embodiment>
<2.1 Overall configuration and operation of liquid crystal display device>
FIG. 7 is a block diagram showing the overall configuration of an active matrix liquid crystal display device according to the second embodiment of the present invention. The liquid crystal display device includes a source driver 300, a gate driver 400, and a display unit 500 similar to those of the liquid crystal display device according to the first embodiment shown in FIG. 1 described above, and the first embodiment. Unlike the case, the first offset signal generation circuit 621 that outputs a first offset signal OS1 having a predetermined positive polarity offset voltage and the second offset signal OS2 having a predetermined negative polarity offset voltage are provided. The second offset signal generation circuit 622 to output, the (M) liquid crystal signal generation circuits 721 to 724 having a configuration different from that of the first embodiment, and these are controlled to be different from those of the first embodiment. And a display control circuit 100. Therefore, the same components are denoted by the same reference numerals and description thereof is omitted. Next, the configuration and operation of the liquid crystal signal generation circuits 721 to 724 in the present embodiment will be described in detail.

<2.2 Configuration and operation of liquid crystal signal generation circuit>
FIG. 8 is a circuit diagram showing a configuration of the liquid crystal signal generation circuit 721 in the present embodiment. When the liquid crystal signal generation circuit 721 outputs the positive drive video signal S (1), the voltage of the first offset signal OS1 from the first offset signal generation circuit 621 and the video from the source driver 300 are displayed. When adding and outputting the signal D (1) and outputting the negative drive video signal S (1), the voltage of the second offset signal OS2 from the second offset signal generation circuit 622 and the source This is a circuit for adding and outputting the video signal D (1) from the driver 300. In order to realize such an operation, the liquid crystal signal generation circuit 721 uses the same components as those for the liquid crystal signal generation circuit 701 in the first embodiment shown in FIG. The first positive polarity switch 720a, the second positive polarity switch 720b, the third positive polarity switch 720c, the positive polarity capacitive element 725, and the negative polarity signal output are configured to have one set each. The first negative polarity switch 727a, the second negative polarity switch 727b, the third negative polarity switch 727c, and the negative capacitance element 726, and the fourth switch 720 similar to the first embodiment are included. Other components are the same as those in FIG.

  The first positive polarity switch 720a, the second positive polarity switch 720b, the third positive polarity switch 720c, the first negative polarity switch 727a, the second negative polarity switch 727b, the third negative polarity switch 727c, and the fourth switch 720 are: First positive polarity switch control signal SWpa, second positive polarity switch control signal SWpb, third positive polarity switch control signal SWpc, first negative polarity switch control signal SWna, second negative polarity switch from the corresponding display control circuit 100, respectively. The control signal SWnb, the third negative switch control signal SWnc, and the fourth switch control signal SWd2 make the both ends conductive or cut off. A so-called charge pump operation is performed independently so that these switches and the positive capacitive element 725 and the negative capacitive element 726 do not interfere with each other. Hereinafter, the operations of the liquid crystal signal generation circuit 721 including this operation and related circuits will be described in detail with reference to FIG.

  FIG. 9 is a diagram simply showing waveforms of various signals including the switch control signal. In FIG. 9, a certain horizontal period composed of two periods T21 and T22, a subsequent one horizontal period composed of two periods T23 and T24, and four horizontal periods from the subsequent periods T25 to T24. The change in potential of each signal at is simply shown.

  Here, the first positive switch control signal SWpa, the second positive switch control signal SWpb, the third positive switch control signal SWpc, and the fourth switch control signal SWd2 shown in FIG. The cycle of the first switch control signal SWa, the second switch control signal SWb, the third switch control signal SWc, and the fourth switch control signal SWd shown in FIG. It can be seen that the same control as in the first embodiment is performed in the two horizontal periods.

  Similarly, the signal waveforms of the first negative switch control signal SWna, the second negative switch control signal SWnb, the third negative switch control signal SWnc, and the fourth switch control signal SWd2 are also shown in FIG. The cycle is exactly twice the signal waveform of the 1 switch control signal SWa, the second switch control signal SWb, the third switch control signal SWc, and the fourth switch control signal SWd, and the corresponding switches are continued in two horizontal periods. The first positive polarity switch control signal SWpa, the second positive polarity switch control signal SWpb, the third positive polarity switch control signal SWpc, and the fourth switch control signal SWd2 are understood to be controlled in the same manner as in the first embodiment. Since each signal is delayed (or advanced) by exactly one horizontal period, control of the corresponding switch Just be one horizontal period delay (or willing) carried out it. Thus, during the period when one of the positive capacitive element 725 and the negative capacitive element 726 is performing the charge pump operation, the other is connected exclusively to the video signal line SL (1). Will be. Hereinafter, this operation will be described.

  First, in the periods T21 and T22, the first positive polarity switch 720a, the second positive polarity switch 720b, the third positive polarity switch 720c, the first negative polarity switch 727a, the second negative polarity switch 727b, the third negative polarity switch 727c, As a result of the operation of the fourth switch 720, the positive capacitive potential Vcp in the positive capacitive element 725 is changed from the midpoint potential V_center to the positive video signal voltage VsP and the positive as in the periods T1 and T2 shown in FIG. The potential becomes higher by the voltage obtained by adding the offset voltage VoP. This is as described above for the so-called charge pump operation. The above operation is exactly the same in the periods T25 and T26.

  Further, in the period T21 of the same periods T21 and T22, the operation of the first negative polarity switch 727a, the second negative polarity switch 727b, the third negative polarity switch 727c, and the fourth switch 720 is performed in a previous period (not shown). The negative capacitive element 726 charged to the voltage obtained by adding the negative video signal voltage VsN and the negative offset voltage VoN and the video signal line SL (1) are brought into conduction (as in periods T23 and T24 described later). The potential of the video signal line SL (1) becomes equal to the negative capacitance potential Vcn. That is, the driving video signal S (1) having the added voltage is applied to the video signal line SL (1) by the liquid crystal signal generation circuit 721. The voltage applied as the video signal for driving is applied to the corresponding pixel formation portion P (via the TFT 10 that is turned on by the application of the scanning signal G (1) activated in the period T21 by the gate driver 400. 1, 1) is applied to the pixel electrode Epix and held in the pixel capacitance of the pixel formation portion. After that, in the period T22, the negative capacitive element 726 and the video signal line SL (1) are connected to the common electrode Ecom by the operation of each switch, and these potentials become the midpoint potential V_center that is substantially equal to the potential of the common electrode. . With this operation, it is possible to prevent the source driver 300 from being applied with a voltage exceeding the maximum withstand voltage value. The above operation is exactly the same in the periods T25 and T26.

  Next, in the period T23 of the periods T23 and T24, the first positive polarity switch 720a, the second positive polarity switch 720b, the third positive polarity switch 720c, the first negative polarity switch 727a, the second negative polarity switch 727b, The positive polarity capacitive element 725 and the video signal charged to the voltage obtained by adding the positive video signal voltage VsP and the positive offset voltage VoP in the periods T21 and T22 by the operation of the three negative switch 727c and the fourth switch 720. The line SL (1) is brought into conduction, and the potential of the video signal line SL (1) becomes equal to the positive capacitance potential Vcp. That is, the driving video signal S (1) having the added voltage is applied to the video signal line SL (1) by the liquid crystal signal generation circuit 721. After that, in the period T24, the positive capacitive element 725 and the video signal line SL (1) are connected to the common electrode Ecom by the operation of each switch, and these potentials become a midpoint potential V_center that is substantially equal to the potential of the common electrode. . With this operation, it is possible to prevent the source driver 300 from being applied with a voltage exceeding the maximum withstand voltage value as described above. The above operation is exactly the same in the periods T27 and T28.

  Further, in the same period T23, T24, the negative capacitance potential Vcn in the negative capacitance element 726 is obtained by the operations of the first negative polarity switch 727a, the second negative polarity switch 727b, the third negative polarity switch 727c, and the fourth switch 720. As in the periods T5 and T6 shown in FIG. 6, the potential is lower by the voltage obtained by adding the negative video signal voltage VsN and the negative offset voltage VoN to the midpoint potential V_center. This is as described above for the so-called charge pump operation. The above operation is exactly the same in the periods T27 and T28.

  Here, the operation of each of the switches as described above does not interfere with each other because the second positive polarity switch 720b and the second negative polarity switch 727bc are not simultaneously turned on, and the third positive polarity switch 720c and the third negative polarity switch are not simultaneously turned on. This is because the circuit for generating a positive polarity signal and the circuit for generating a negative polarity signal are always electrically disconnected since 727c is not turned on at the same time.

<2.3 Effects>
As described above, in the liquid crystal display device according to the second embodiment, the first and second offset signal generation circuits 621 are performed by the liquid crystal signal generation circuits 721 to 724 without changing the configuration of the pixel formation unit, for example. , 622 is added (synthesized) to the voltage of the output signal from the source driver 300, and the withstand voltage design of the source driver 300 can be lowered with a simple configuration.

  In the liquid crystal display device according to the second embodiment, the liquid crystal signal generation circuits 721 to 724 are provided with the positive capacitive element 725 and the negative capacitive element 726, and one of them performs the charge pump operation. Since the corresponding switch is appropriately controlled so that the other is connected to the video signal line, the video signal line for driving is supplied to the video signal line during a period twice as long as one horizontal period compared to the case of the first embodiment. Can be applied. Therefore, a sufficient video signal application time (pixel value writing time) can be secured in each pixel formation portion even in a high-definition display device.

<3. Third Embodiment>
<3.1 Overall Configuration and Operation of Liquid Crystal Display Device>
The overall configuration of the active matrix type liquid crystal display device according to the third embodiment of the present invention is the same as that of the liquid crystal display device according to the second embodiment shown in FIG. Unit 500, first and second offset signal generating circuits 621 and 622, (M) liquid crystal signal generating circuits 731 to 734 having a configuration different from that of the first embodiment, and a display control circuit for controlling them. 100. Therefore, the same components are denoted by the same reference numerals, and the block diagram and description thereof are omitted. Next, the configuration and operation of the liquid crystal signal generation circuits 731 to 734 in the present embodiment will be described in detail.

<3.2 Configuration and operation of liquid crystal signal generation circuit>
FIG. 10 is a circuit diagram showing a configuration of the liquid crystal signal generation circuit 731 in the present embodiment. This liquid crystal signal generation circuit 721 is replaced with the positive polarity diode 738a and the negative polarity in place of the third positive polarity switch 720c and the third negative polarity switch 727c among the components included in the liquid crystal signal generation circuit 721 shown in FIG. The diode 738b is provided, which eliminates the third positive polarity switch control signal SWpc and the third negative polarity switch control signal SWnc for controlling the third positive polarity switch 720c and the third negative polarity switch 727c. Yes. Note that as the positive diode 738a and the negative diode 738b, it is preferable to use a Schottky diode having a small forward voltage drop and a high switching speed.

  The positive polarity diode 738a and the negative polarity diode 738b are turned on when a predetermined forward voltage is applied, and thus operate in the same manner as the third positive polarity switch 720c and the third negative polarity switch 727c. However, since no control signal is required for these diodes, the liquid crystal signal generation circuit 731 in this embodiment can be made simpler than the configuration of the second embodiment.

  The various signal waveforms related to the operation of the liquid crystal signal generation circuit 731 are the various signal waveforms shown in FIG. 9 except that the third positive polarity switch control signal SWpc and the third negative polarity switch control signal SWnc are omitted. Since it is the same as the waveform, the description is omitted. However, strictly speaking, it is necessary to consider the forward voltage drop in the positive polarity diode 738a and the negative polarity diode 738b, but the value is small and may be ignored.

  Note that the first offset signal generation circuit 621 always provides the positive polarity offset signal OS1 and the second offset signal generation circuit 622 always provides the negative polarity offset signal OS2, so that the positive polarity diode 738a and the negative polarity diode 738b are supplied. On the other hand, no voltage is applied in the reverse direction, and the second positive polarity switch 720b and the second negative polarity switch 727bc are not turned on at the same time. Therefore, a positive polarity signal generation circuit and a negative polarity signal generation circuit Are always electrically disconnected. Therefore, there is no problem in that the charge pump operation is performed independently so that the positive capacitive element 725 and the negative capacitive element 726 do not interfere with each other.

<3.3 Effects>
As described above, in the liquid crystal display device according to the third embodiment, the first and second offset signal generation circuits 621 are performed by the liquid crystal signal generation circuits 731 to 734 without changing the configuration of the pixel formation portion, for example. , 622 is combined (added) to the voltage of the output signal from the source driver 300, the withstand voltage design of the source driver 300 can be lowered with a simple configuration.

  Further, in the liquid crystal display device according to the third embodiment, as in the case of the second embodiment, the liquid crystal signal generation circuits 731 to 734 are provided with the positive capacitive element 725 and the negative capacitive element 726, one of which is provided. Since the corresponding switch is appropriately controlled so that the other is connected to the video signal line during the period of performing the charge pump operation, the period is twice as long as one horizontal period compared to the case of the first embodiment. The driving video signal can be applied to the video signal line. Therefore, a sufficient video signal application time (pixel value writing time) can be secured in each pixel formation portion even in a high-definition display device.

  Further, in the liquid crystal display device in the third embodiment, the third positive polarity switch 720c and the third negative polarity switch 727c included in the liquid crystal signal generation circuit 721 in the second embodiment are omitted. Since the third positive polarity switch control signal SWpc and the third negative polarity switch control signal SWnc can be omitted, the control can be simplified.

<4. Fourth Embodiment>
The third embodiment includes the first and second offset signal generation circuits 621 and 622 as in the case of the second embodiment. However, as in the case of the first embodiment, the negative capacitive element 726 is provided. Can be omitted. Hereinafter, a liquid crystal display device according to a fourth embodiment as a modification of the third embodiment will be described. However, the overall configuration of the liquid crystal display device is shown in FIG. 1 described above except for the configuration of the liquid crystal signal generation circuits 741 to 744 provided in place of the liquid crystal signal generation circuits 701 to 704 in the first embodiment. Since it is the same as that of the configuration in the first embodiment, the same number is assigned to the same component and its description is omitted. Therefore, the configuration of the liquid crystal signal generation circuit will be described with reference to FIG.

  FIG. 11 is a circuit diagram showing a configuration of a liquid crystal signal generation circuit 741 according to the fourth embodiment. As shown in FIG. 11, the liquid crystal signal generation circuit 741 has a configuration in which the negative capacitive element 726 is omitted from the liquid crystal signal generation circuit 731 in the third embodiment shown in FIG. The operation is similar to the operation in the first embodiment based on the signals shown in FIG. That is, the first positive switch control signal SWpa and the second positive switch control signal SWpb in the present embodiment are the same as the first switch control signal SWa and the second switch control signal SWb shown in FIG. Although the signal waveform is the same, the OFF potential is OFF in the periods T5 to T8. In the periods T5 to T8, the first negative switch control signal SWna and the second negative switch control signal SWnb in the present embodiment are the first switch control signal SWa and the first switch control signal SWa shown in FIG. The signal waveform is the same as that of the second switch control signal SWb, and the OFF potential is OFF during the periods T1 to T4.

  By controlling the corresponding switches based on such signals, the liquid crystal signal generation circuit in the present embodiment has a simpler configuration than that in the third embodiment, and is the same as that in the first embodiment. A driving video signal can be output.

<5. Modification>

  In each of the above-described embodiments, the periods T1 to T8 are described as having the same length in the embodiment. However, the periods T1 to T8 do not have to be particularly equal in length, for example, the periods T1 and T5 in the first embodiment, It is preferable that the periods T3 and T7 are sufficiently long periods. That is, in the periods T3 and T7, a sufficient period for applying the potential charged in the capacitor 715 to the video signal line is necessary. In the periods T1 and T5, the voltage from the source driver 300 is applied to the capacitor 715. Sufficient time for charging is required. In particular, when the driving capability (charging capability) of the source driver 300 is not large in terms of cost and the like, the periods T1 and T5 (or a period obtained by adding the periods T2 and T6) are compared with the periods T3 and T7. It is preferable that the period is sufficiently long. By setting the period in this manner, the charge necessary for the capacitor 715 is charged, so that the shortage of the video signal voltage due to the shortage of the charging time can be avoided.

  In each of the above embodiments, the first and second offset signal generation circuits and the respective liquid crystal signal generation circuits are provided outside the source driver 300, but part or all of them are built in the source driver 300. It may be a configuration. That is, the first and second offset signal generation circuits, the respective liquid crystal signal generation circuits, and the source driver 300 can be collectively referred to as video signal line drive circuits.

  In each of the above embodiments, the liquid crystal signal generation circuit includes a capacitive element, and the offset voltage is added (synthesized) to the voltage of the video signal from the source driver 300 by a so-called charge pump method. The present invention can be applied to any circuit configuration. In addition, other known booster circuits may be employed instead of the charge pump circuit.

  In each of the above embodiments, the liquid crystal display device adopting the one-dot inversion driving method in which the polarity is inverted for each adjacent one-pixel forming unit has been described as an example. An n-dot inversion driving method in which the polarity is inverted every n pixel forming units (n is a natural number of 2 or more) may be employed. In addition, when it is necessary to lower the withstand voltage design of the source driver, a line inversion driving method that inverts the positive / negative polarity of every one frame while inverting the positive / negative polarity of the applied voltage every one or more horizontal scanning lines. An adopted liquid crystal display device may be used.

  In each of the above embodiments, the active matrix type liquid crystal display device has been described as an example. However, the display device is an active matrix type voltage control display device that requires a low withstand voltage design of the source driver. If so, the present invention can be applied to devices other than liquid crystal display devices.

1 is a block diagram showing an overall configuration of an active matrix liquid crystal display device according to a first embodiment of the present invention according to the first embodiment of the present invention. FIG. It is a figure which shows typically the structure of the display part in the said embodiment. It is a circuit diagram which shows the equivalent circuit of the pixel formation part in the said embodiment. It is a figure which shows the relationship between the applied voltage with respect to the liquid crystal used for the display apparatus in the said embodiment, and a brightness | luminance. It is a circuit diagram which shows the structure of the liquid crystal signal generation circuit in the said embodiment. It is a figure which shows simply the waveform of various signals including the switch control signal in the said embodiment. It is a block diagram which shows the whole structure of the active matrix type liquid crystal display device which concerns on the 2nd Embodiment of this invention. It is a circuit diagram which shows the structure of the liquid crystal signal generation circuit in the said embodiment. It is a figure which shows simply the waveform of various signals including the switch control signal in the said embodiment. It is a circuit diagram which shows the structure of the liquid crystal signal generation circuit in the 3rd Embodiment of this invention. It is a circuit diagram which shows the structure of the liquid crystal signal generation circuit in the 4th Embodiment of this invention. It is a figure which shows simply the voltage change of a certain data line at the time of employ | adopting the conventional dot inversion drive system. It is a figure which shows the polarity of the voltage applied to each pixel formation part by the conventional dot inversion drive system.

Explanation of symbols

10 ... TFT (switching element)
DESCRIPTION OF SYMBOLS 100 ... Display control circuit 200 ... Common electrode drive circuit 300 ... Source driver 400 ... Gate driver 500 ... Display part 601,621 ... 1st offset signal generation circuit 602,622 ... 2nd offset signal generation circuit 701-704,721 ~ 724
731 to 734, 741 to 744 ... Liquid crystal signal generation circuit 710a to 710d ... Switch 715 ... Capacitance 720a to 720d ... Positive polarity switch 725 ... Positive polarity capacitance 726 ... Negative polarity capacitance 727a to 727d ... Negative polarity switch 738a ... Positive polarity diode 738b ... Negative polarity diode DAT ... Display data signal DV ... Digital image signal Clc ... Liquid crystal capacitance Cs ... Parasitic capacitance Ecom ... Common electrode Epix ... Pixel electrode GL (n) ... Scanning signal line (n = 1 to N)
SL (m): Data signal line (m = 1 to M)
P (n, m): Pixel formation portion (n = 1 to N, m = 1 to M)
OS1 ... first offset signal OS2 ... second offset signal

Claims (10)

Pixel electrodes provided in a plurality of pixel formation portions arranged in a matrix corresponding to intersections of a plurality of video signal lines and a plurality of scanning signal lines in a display portion for displaying an image, and the pixels A common electrode provided in correspondence with the pixel electrode for applying a voltage between the electrode, a common electrode driving circuit for applying a predetermined voltage to the common electrode, and an image signal representing the image, A video signal line driving circuit for applying a voltage to the plurality of video signal lines according to a signal, a scanning signal line driving circuit for selectively driving the plurality of scanning signal lines, the video signal line driving circuit, and the scanning An active matrix display device comprising a display control circuit for controlling a signal line driving circuit,
The video signal line driving circuit includes:
A voltage signal whose polarity is reversed every predetermined period between positive and negative voltages which are predetermined two kinds of voltages applied to the pixel electrode with reference to the potential of the common electrode. A source driver that outputs a voltage signal obtained by subtracting a predetermined offset voltage from a voltage corresponding to the image signal;
An offset voltage generation circuit for generating the offset voltage;
A voltage corresponding to the image signal is generated by adding the offset voltage generated by the offset voltage generation circuit to a voltage signal output from the source driver, and the generated voltage is used as the plurality of videos. An active matrix display device comprising: a plurality of signal generation circuits applied to signal lines.   The offset voltage generation circuit generates, as the offset voltage, a predetermined voltage within a range in which light transmittance hardly changes when applied from zero to a liquid crystal layer provided between the pixel electrode and the common electrode. The active matrix display device according to claim 1, wherein: The signal generation circuit includes:
One of the two electrodes is connected to the source driver, the other electrode is connected to the offset voltage generation circuit, and the source is changed by changing the potential of the other electrode by the offset voltage. A capacity charged with an addition voltage obtained by adding the offset voltage to the voltage output from the driver;
The source driver and the capacitor are connected or disconnected so that the added voltage is charged with respect to the capacitor, and the corresponding video signal line and the capacitor are connected so that the added voltage charged to the capacitor is applied. 2. The active matrix display device according to claim 1, further comprising switching means for connecting or disconnecting.   4. The active matrix display device according to claim 3, wherein the capacitance has a capacitance value larger than a parasitic capacitance value parasitic on a corresponding video signal line.   The switching means has a time for connecting the source driver and the capacitor so that the added voltage is charged with respect to the capacitor, and a corresponding video signal line so that the added voltage charged in the capacitor is applied. 4. The active matrix display device according to claim 3, wherein a time for connecting the capacitor and the capacitor is longer. The capacity is
One of the two electrodes is connected to the source driver, the other electrode is connected to the offset voltage generation circuit, and the potential of the other electrode is set to a positive offset voltage of the offset voltage. By changing only the positive polarity capacitance charged with the positive addition voltage obtained by adding the positive polarity offset voltage to the voltage output from the source driver,
One of the two electrodes is connected to the source driver, the other electrode is connected to the offset voltage generation circuit, and the potential of the other electrode is set to the negative offset voltage of the offset voltage. A negative capacity capacitor charged with a negative addition voltage obtained by adding the negative offset voltage to the voltage output from the source driver,
The switching means is
The source driver and the positive capacitor are connected or disconnected so that the positive additive voltage is charged with respect to the positive capacitor, and the negative additive voltage is charged to the negative capacitor. Positive polarity switching means for connecting or disconnecting the corresponding video signal line and the positive capacitance so that the positive addition voltage charged in the positive capacitance is applied;
The source driver and the negative capacity capacitor are connected or disconnected so that the negative capacity voltage is charged with respect to the negative capacity, and the negative capacity voltage is charged when the positive capacity voltage is charged to the local capacity. 4. The negative polarity switching means for connecting or disconnecting a corresponding video signal line and the negative capacitance so that the negative addition voltage charged in the negative capacitance is applied. Active matrix display device.   The signal generation circuit may connect a potential of the video signal line to a predetermined voltage less than a maximum withstand voltage of the source driver before connecting the corresponding video signal line and the capacitor so that the addition voltage is applied by the switching unit. 4. The active matrix display device according to claim 3, further comprising connection potential setting means for setting the potential.   The active matrix according to claim 7, wherein the connection potential setting means sets the potential of the video signal line to the potential of the common electrode by connecting the video signal line and the common electrode. Type display device. In the source driver, the polarities of voltages applied to adjacent video signal lines by n (n is a natural number) are opposite to each other, and the polarity is reversed every m (m is a natural number) horizontal periods. Output voltage signal,
9. The common electrode driving circuit according to claim 1, wherein the common electrode driving circuit applies a fixed predetermined voltage in the vicinity of a midpoint voltage of the positive and negative voltages to the common electrode. 2. An active matrix display device according to item 1. Pixel electrodes provided in a plurality of pixel formation portions arranged in a matrix corresponding to intersections of a plurality of video signal lines and a plurality of scanning signal lines in a display portion for displaying an image, and the pixels A display method of an active matrix display device comprising a common electrode provided corresponding to the pixel electrode for applying a voltage between the electrode and the electrode,
A common electrode driving step of applying a predetermined voltage to the common electrode;
A video signal line driving step of receiving an image signal representing the image and applying a voltage to the plurality of video signal lines according to the image signal;
A scanning signal line driving step for selectively driving the plurality of scanning signal lines,
The video signal line driving step includes:
A voltage signal whose polarity is reversed every predetermined period between positive and negative voltages which are predetermined two kinds of voltages applied to the pixel electrode with reference to the potential of the common electrode. A source driving step of outputting a voltage signal obtained by subtracting a predetermined offset voltage from a voltage corresponding to the image signal;
An offset voltage generating step for generating the offset voltage;
A voltage corresponding to the image signal is generated by adding the offset voltage generated in the offset voltage generation step to the voltage signal output in the source driving step, and the generated voltage is set to the plurality of voltages. And a signal generating step applied to the video signal line.

Images