JP2000163025A - Liquid crystal display device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To quickly erase the after-image of a display screen at the time of turning the power off and also to prevent a liquid cystal display panel from being degraded owing to residual voltages. SOLUTION: When a power switch SW is turned off, a power control circuit 11 turns a flag signal PwACT being supplied to a sequence control circuit 10 into a Low. When the flag signal PwACT becomes the Low, the sequence control circuit 10 turns outputs of a signal driver 4 into high impedances while keeping the active state of a scanning driver 5. When the outputs of the driver 4 are made to become high impedances, electric charges of pixel electrodes of an LCD 7 are discharged in a so enough short time that eyes of a human being can not confirm it. Thereafter, the control circuit 10 turns a flag signal OFF Ready into a High. When the flag signal OFF Ready becomes the High, the control circuit 11 turns a power control signal PCS into a Low to turn a power 12 off.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device using a TFT or the like, and more particularly, to a reflection type liquid crystal display device using no backlight.

[0002]

2. Description of the Related Art FIG. 8 is a block diagram showing the structure of a conventional TFT liquid crystal display. FIG. 9 is a circuit diagram showing a circuit configuration of the liquid crystal display panel. First, the liquid crystal display panel (LCD) 7 will be described with reference to FIG. L
The CD 7 is of an active matrix type, and is shown in FIG.
As shown in FIG. 3, m lines (for example, 234)
Scan lines (gate lines) X 1 to X 234, n (for example, 280) signal lines (source lines) Y 1 to Y 280 arranged in the column direction, Counter electrode CO to which common voltage Vcom is applied
M and m auxiliary capacitance lines CS arranged in parallel with the scanning lines X1 to X234 and connected to the common electrode COM.
And a thin film transistor (TFT) having a gate connected to the corresponding scan line X1 to X234 and a source connected to the corresponding signal line Y1 to Y280, and a pixel capacitor CLC and an auxiliary capacitor CCS connected to the drain of the TFT. Become. The signal lines Y1 to Y280 are connected to an electrostatic protection resistor RCS.
Is connected to the auxiliary capacitance line CS via the line.

[0003] Next, in FIG.
Generates a luminance signal of each color of RGB, a horizontal synchronizing signal H, and a vertical synchronizing signal V from a composite video signal, outputs a luminance signal of each color of RGB to an inverting amplifier 3, and outputs a horizontal synchronizing signal H, a vertical synchronizing signal V, and a composite synchronizing signal. Signal CSY
Is output to the controller 2. The controller 2 supplies a horizontal control signal to a signal driver, a vertical control signal to a scan driver, and a polarity inversion signal FRP to the inversion amplifiers 3 and 6 according to the horizontal synchronization signal H, the vertical synchronization signal V, and the composite synchronization signal CSY. I do. The inverting amplifier 3 is provided with a polarity inversion signal FR supplied from the controller 2.
In accordance with P, the signal levels of the luminance signals of the respective RGB colors are amplified at a positive or negative amplification rate and output.

The signal driver 4 supplies the RGB luminance signals 19 supplied from the inverting amplifier 3 to the signal lines Y1 to Y280 of the LCD 7 in accordance with the horizontal control signal.
Further, the scanning driver 5 sequentially applies gate pulses to the scanning lines X1 to X234 of the LCD 7 according to the vertical control signal from the controller 2. In accordance with the polarity inversion signal FRP supplied from the controller 2, the amplifier 6 includes a counter electrode COM of the pixel capacitance CLC and an auxiliary capacitance line CS
Invert the polarity of the common voltage Vcom applied to. LCD
Reference numeral 7 denotes a structure in which a pixel is charged with a source potential during a gate selection period, and is held during a non-selection period.

[0005]

In the liquid crystal display device according to the prior art, when the power supply of the device is turned off, the driver output becomes high impedance. Further, the gate selection pulse becomes inactive, and the pixel keeps the previous potential. The pixel potential is
Peripheral wiring (gate, source, auxiliary capacitance wiring CS), T
The FT and the LCD are gradually discharged by a leak current through a high resistance path, and finally have the same potential as the counter electrode COM (= auxiliary capacitance wiring CS).

[0006] However, when the pixel potential is changed to the counter electrode COM.
Since it takes a considerable time (about several seconds) until the potential becomes substantially the same as above, the behavior is such that the immediately preceding display screen gradually disappears. This time, for the human eye,
Since this is a relatively long time, in other words, a sufficiently visible time, when the power is turned off, the immediately preceding display screen is held and gradually disappears. In a transmissive LCD using a backlight, the backlight is turned off first, so that this afterimage cannot be seen. In a reflective LCD, however, the display is always visible, so that an unsightly screen is displayed and the residual voltage causes the liquid crystal to be displayed. There is a problem that the display panel is deteriorated.

Accordingly, the present invention is capable of quickly eliminating the afterimage of the display screen when the power is turned off, and
It is an object of the present invention to provide a liquid crystal display device capable of preventing deterioration of a liquid crystal display panel due to a residual voltage.

[0008]

In order to achieve the above object, a liquid crystal display device according to the present invention comprises a plurality of scanning lines and a plurality of signal lines formed so as to be orthogonal to the plurality of scanning lines. A switching element disposed near each intersection between the plurality of scanning lines and the plurality of signal lines; a pixel electrode and an auxiliary capacitor connected to the switching element; and a resistance element connected to the plurality of signal lines. A liquid crystal panel comprising an auxiliary capacitance line connected and connected to each other, a common electrode facing the liquid crystal panel, a scanning drive circuit for transmitting a scanning drive signal to the plurality of scanning lines and sequentially performing horizontal scanning, and each of the plurality of signal lines And a signal-side drive circuit for transmitting a display data signal corresponding to the video signal, wherein it is detected that the power switch of the liquid crystal display device is turned off. Detecting means, applied voltage attenuating means for setting the voltage applied to the liquid crystal panel to zero when the power switch is turned off by the detecting means, and applying the voltage to the liquid crystal panel by the applied voltage attenuating means. And a power supply control means for turning off the power supply when the applied voltage becomes zero.

In a preferred embodiment, for example, in the liquid crystal display device according to the first aspect, the applied voltage attenuating means changes the potential of the plurality of signal lines to the potential of the common electrode. You may make it approach.

In a preferred aspect, in the liquid crystal display device according to the second aspect, the applied voltage attenuating means operates the signal side driving circuit while operating the scanning side driving circuit. The output of the circuit may be set to high impedance.

In a preferred embodiment, in the liquid crystal display device according to the first aspect, the applied voltage attenuating means includes a display screen when the applied voltage to the liquid crystal panel is zero. May be supplied to the signal side drive circuit.

According to another aspect of the present invention, there is provided a liquid crystal display device comprising: a plurality of scanning lines; a plurality of signal lines formed so as to be orthogonal to the plurality of scanning lines; A switching element disposed near each intersection of the scanning line and the plurality of signal lines,
A liquid crystal panel including a pixel electrode and an auxiliary capacitance connected to the switching element, an auxiliary capacitance wiring connected to the plurality of signal lines via a resistance element, and a common electrode facing the plurality of signal lines; A liquid crystal display device comprising: a scanning side driving circuit for transmitting a scanning driving signal to sequentially perform horizontal scanning; and a signal side driving circuit for transmitting a display data signal corresponding to a video signal to each of the plurality of signal lines. Detecting means for detecting that the power switch of the liquid crystal display device has been turned off; and detecting that the power switch has been turned off by the detecting means, the signal-side drive circuit remains operating while the scanning-side drive circuit is operated. Drive circuit control means for setting the output of the circuit to high impedance; and the output of the signal side drive circuit to high impedance by the drive circuit control means. When the state has passed a predetermined time, the liquid crystal display device characterized by comprising a power supply control means for turning off the power.

In a preferred embodiment, in the liquid crystal display device according to the fifth aspect, the power supply control means includes a high impedance state of the signal side drive circuit based on a vertical synchronization signal. May be determined.

According to another aspect of the present invention, there is provided a liquid crystal display device comprising: a plurality of scanning lines; a plurality of signal lines formed so as to be orthogonal to the plurality of scanning lines; A switching element disposed near each intersection of the scanning line and the plurality of signal lines,
A liquid crystal panel including a pixel electrode and an auxiliary capacitance connected to the switching element, an auxiliary capacitance wiring connected to the plurality of signal lines via a resistance element, and a common electrode facing the plurality of signal lines; A liquid crystal display device comprising: a scanning side driving circuit for transmitting a scanning driving signal to sequentially perform horizontal scanning; and a signal side driving circuit for transmitting a display data signal corresponding to a video signal to each of the plurality of signal lines. Detecting means for detecting that a power switch of the liquid crystal display device is turned off; display data signal generating means for generating a display data signal corresponding to a display screen when a voltage applied to the liquid crystal panel is zero; When the detection means detects that the power switch has been turned off, the display data signal generation means generates the display data signal instead of the normal display data signal. Switching means for selectively supplying a display data signal to the signal-side drive circuit, and a power supply after the display data signal generated by the display data signal generation means is supplied to the signal-side drive circuit by the switch means. And power supply control means for turning off the power.

[0015]

Embodiments of the present invention will be described below with reference to the drawings. A. First embodiment A-1. Configuration of First Embodiment FIG. 1 is a block diagram showing a configuration of a liquid crystal display according to a first embodiment of the present invention. Note that the same reference numerals are given to portions corresponding to FIG. In the figure, a sequence control circuit 10 is inserted between a controller 2 and drivers 4 and 5 to supply a horizontal control signal from the controller 2 to a signal driver 4 and supply a vertical control signal to a scanning driver 5. Further, when the flag signal PwACT, which is supplied from the power supply control circuit 11 described later and indicates the on / off state of the power switch SW, becomes Low, the sequence control circuit 10 changes the flag signal OFF Ready at the timing based on the vertical synchronization signal. Hi
gh. The detailed configuration of the sequence control circuit 10 will be described later.

The horizontal control signal includes a clear signal CLR,
An output enable signal OE is included. The vertical control signals include a gate start signal GSRT, a gate pulse clock signal GPCK, and a gate output enable signal G.
Contains OE.

The signal driver 4 includes a sequence control circuit 4
The luminance signal 19 of each color of RGB supplied from the inverting amplifier 3 is supplied to the signal lines Y1 to Y280 of the LCD 7 in accordance with the horizontal control signal from. The scan driver 5 sequentially applies gate pulses to the scan lines X1 to X234 of the LCD 7 according to a vertical control signal from the sequence control circuit 4.

Here, the configuration of the signal driver 4 related to the operation of the first embodiment will be briefly described. FIG.
2 is a block diagram showing a schematic configuration of the signal driver 4. FIG. In the figure, a signal driver 4 includes a circuit power supply voltage VDDC, an output enable signal OE, and an output of VDDC.
A control signal CLR for precharging to a potential, an RGB luminance signal 19, a sampling start signal SRT, and a clock signal CK are supplied.

The signal driver 4 includes a sequence control circuit 4
Is shifted by the shift register 4a, and in accordance with this, the RGB luminance signals 19 supplied from the inverting amplifier 3 are held by the sample hold circuit 4b and output via the buffer 4c. In the display period, the output enable signal OE
Is High, the control signal CLR is Low, and the held luminance signal is directly applied to the signal line Y of the LCD 7.
1 to Y280. On the other hand, when the output enable signal OE and the clear signal CLR are Low (in the case of positive logic), the switch groups 4d and 4e are opened, so that the output of the signal driver 4 becomes high impedance.

When the power switch SW is turned on, the power supply control circuit 11 sets the flag signal PwACT to be supplied to the sequence control circuit 10 to High, and when the power switch SW is turned off, supplies the signal to the sequence control circuit 10. The flag signal PwACT to be activated is set to Low. When the power supply control circuit 11 receives the flag signal OFF Ready from the sequence control circuit 10,
When the off sequence by the sequence control circuit 10 is completed, the current control signal PCS supplied to the power
ow. The power switch SW is used to turn on the power to the device,
A switch for turning off the power, which is operated by the user. The power supply 12 turns on / off power supply to each unit of the device according to a power control signal PCS from the power control circuit 11.

A-2. Next, FIG. 3 is a circuit diagram showing a configuration of the sequence control circuit. FIG. 4 is a timing chart for explaining the operation of the sequence control circuit. In the figure, the sequence control circuit 10 includes D-FFs 13a to D-FFs.
FF 13e, AND circuits 14, 15, OR circuit 16, N
It comprises an OT circuit 17 and AND circuits 18 (plural). The D-FFs 13a to 13e are cascade-connected, and each output the state of the flag signal PwACT in synchronization with the vertical synchronization signal. That is, the power switch SW is turned off and the flag signal PwACT is set to Low.
Then, the output of the D-FF 13a becomes Low at the first vertical synchronization signal supplied thereafter, the output of the D-FF 13b becomes Low at the second vertical synchronization signal, and D-FF at the third vertical synchronization signal. The output of the FF 13c is Low, and similarly, the output of the D-FF 13d is L
ow, the output of the D-FF 13e is L in the fifth vertical synchronization signal.
ow.

The AND circuit 14 has one input terminal to which the clear signal CLR is input and the other input terminal having the D-FF 13a.
And the control signal CLR and the D-FF
The logical AND with the output of 13a is taken and output as a control signal CLRout. That is, the AND circuit 14 has a D-FF
While the output of 13a is High, that is, while the power switch SW is on, the control signal CLR is output as it is as the control signal CLRout. On the other hand, when the power switch SW is turned off and the flag signal PwACT becomes Low, the first vertical synchronization is performed. When the output of the D-FF 13a becomes Low by the signal, the control signal CLRout is set to Low.

Next, the AND circuit 15 has one input terminal to which the output enable signal OE is input, and the other input terminal having D
Connected to the output terminal of the FF 13a, and ANDs the output enable signal OE with the output of the D-FF 13a;
Output as an output enable signal OEout. That is, the AND circuit 15 outputs the output enable signal OE as it is as the output enable signal OEout while the power switch SW is on and the flag signal PwACT is High, while the power switch SW is turned off and the flag signal PwACT is Low. Then, when the output of the D-FF 13a becomes Low in the first vertical synchronization signal, the output enable signal OEout is set to Low.

Next, the OR circuit 16 has one input terminal D.
-Is connected to the output terminal of the FF 13a, and the other input terminal is D-
The D-FF 13a is connected to the output terminal of the FF 13e.
Is ORed with the output of the D-FF 13e,
It is supplied to one input terminal of the T circuit 17 and the AND circuit 18 (plurality). That is, while the power switch SW is on, the output of the OR circuit 16 is High, while the power switch SW is turned off and the flag signal PwA
CT becomes Low, and D-FF1 is output at the first vertical synchronization signal.
When the output of the D-FF 13e becomes Low in the fifth vertical synchronizing signal after the output of 3a becomes Low, that is, when the time of four fields has elapsed since the flag signal PwACT became Low. , Its output is Low.

The NOT circuit 17 has an input terminal connected to the output terminal of the OR circuit 16, inverts the output of the OR circuit 16, and outputs the inverted signal as a flag signal OFF Ready. That is, the NOT circuit 17 sets the flag signal OFFReady to Low while the power switch SW is on, while turning off the power switch SW and setting the flag signal PwA
When the CT becomes Low and the time corresponding to four fields has elapsed, the flag signal OFF Ready is set to High.

Next, the AND circuit 18 (plural) has one input terminal connected to the output terminal of the OR circuit 16 and the other input terminal connected to another control signal (GOE, GPCK, GSR).
T, Vcom) is input, and when the output of the OR circuit 16 is High, another signal is output as it is, and when the output of the OR circuit 16 becomes Low, the other signal is set to Low. That is, while the power switch SW is on, the AND circuits 18 (plural) output other signals as they are, while the power switch SW is turned off and the flag signal PwA
When CT becomes low and four fields have elapsed, another signal is made low.

A-3. Operation of First Embodiment Next, the operation of the above-described first embodiment will be described.
When the power switch SW is turned off, the power control circuit 11
Sets the flag signal PwACT supplied to the sequence control circuit 10 to Low. In the sequence control circuit 10, when the flag signal PwACT becomes Low, the output of the D-FF 13a supplied to one of the input terminals of the AND circuits 14 and 15 becomes Low with the first vertical synchronization signal, so that the control signal CLRout And the output enable signal OEout becomes Low. When the control signal CLRout and the output enable signal OEout become Low, the output of the signal driver 4 becomes high impedance. On the other hand, the other control signals (GOE, GPCK, GSRT, Vcom) are output as they are from the sequence control circuit 10, and the flag signal OFF Ready remains Low, so that the scanning driver 5 maintains the active state. This state continues until the vertical synchronization signal has passed for four fields.

In this period, the signal lines Y1 to Y280
Will approach the potential of the auxiliary capacitance line CS. That is, since the scanning driver 5 is in the active state, the potential of the auxiliary capacitance line CS is written to the pixel, and the electrostatic protection resistance R
After a time corresponding to a time constant (τ = RCS × CLC) between CS and the pixel capacitance CLC, for example, a time of about 1 ms, the signal lines Y1 to Y280 have the same potential as the potential of the auxiliary capacitance wiring CS. At this time, the voltage applied to the liquid crystal becomes zero, and the afterimage on the display screen is erased. This time is short enough that human eyes cannot see it.

When the fifth vertical synchronizing signal is supplied after the lapse of four fields, the output of the D-FF 13e becomes L
The output becomes low, and the output of the OR circuit 16 becomes low. As a result, one input terminal of the AND circuit 18 (plural) is set to Lo.
w and other control signals (GOE, GPCK, GS
RT, Vcom) goes low, and the flag signal OFF Ready goes high. When the flag signal OFF Ready becomes High, the power supply control circuit 11 outputs the current control signal P supplied to the power supply 12.
CS is set to Low, and the power is turned off.

As described above, in the first embodiment described above,
Time during which the scan driver 5 maintains the active state;
That is, the time T during which the vertical synchronizing signal elapses for four fields
Is sufficiently longer than the time when the signal line is at the same potential as the potential of the auxiliary capacitance line CS, so that each pixel of the liquid crystal panel is surely reset to the state where the applied voltage before the power is turned on is zero. Therefore, the afterimage of the display screen when the power is turned off can be quickly erased, and the deterioration of the liquid crystal display panel due to the residual voltage can be prevented.

B. Second Embodiment Next, a second embodiment of the present invention will be described. In the above-described first embodiment, the pixel potential is volatilized by using the elements inside the LCD 7 to prevent the screen hold phenomenon at the time of power-off. In the second embodiment, the same sequence is used by using the same sequence. By making the video itself supplied to the driver 4 white (in the case of normally white), the LCD 7
Has a white screen on the entire surface to prevent the afterimage phenomenon when the power is turned off. In the case of normally black, the entire surface of the LCD 7 may be set to a black screen.

B-1. Configuration of Second Embodiment FIG. 5 is a block diagram illustrating a configuration of a liquid crystal display device according to a second embodiment of the present invention. Note that the same reference numerals are given to portions corresponding to FIG. In the figure, when a flag signal PwACT, which is supplied from the power supply control circuit 11 and indicates the on / off state of the power supply switch SW, becomes Low, the sequence control circuit 20 generates a flag signal at a first timing based on the vertical synchronization signal. Vwhit
After e is set to High, the flag signal OFF Ready is set to High at the second timing. Further, the signal switching circuit 21 determines that the flag signal Vwhite is High.
Then, white display data (in the case of normally white) is supplied to the signal driver 4 via the inverting amplifier 3 instead of the luminance signal 19 of the RGB signal output from the RGB decoder 1.

B-2. Configuration of Sequence Control Circuit FIG. 6 is a circuit diagram showing a configuration of the sequence control circuit according to the second embodiment. FIG. 7 is a timing chart for explaining the operation of the sequence control circuit.
In the figure, a sequence control circuit 20 includes a D-FF 22
a to D-FF 22c, a NOT circuit 23, and a NOR circuit 24. D-FF22a to D-FF2
2c are cascade-connected, and each output the state of the flag signal PwACT in synchronization with the vertical synchronization signal. That is, when the power switch SW is turned off and the flag signal PwACT becomes Low, the output of the D-FF 22a becomes Lo with the first vertical synchronization signal supplied thereafter.
w, the output of the D-FF 22b becomes Low by the second vertical synchronizing signal, and the D-FF 22c by the third vertical synchronizing signal.
Is Low.

The NOT circuit 23 has a D-FF input terminal.
The output terminal of the D-FF 22a is connected to the output terminal of the D-FF 22a to output the flag signal Vwhite. That is, when the power switch is on, the NOT circuit 23 sets the flag signal Vwhite to Low, and turns off the power switch SW and sets the flag signal PwACT to L.
low, and when the output of the D-FF 22a becomes low in the first vertical synchronizing signal, the flag signal Vwhite is set to High.
h.

The NOR circuit 24 has one input terminal connected to the output terminal of the D-FF 22a, the other input terminal connected to the output terminal of the D-FF 22c, and the DF
The logical sum of the output of the F22a and the output of the D-FF 22c is inverted to output a flag signal OFF Ready. That is, when the power switch is on, the NOR circuit 24 sets the flag signal OFF Ready to Low, while the power switch SW is turned off and the flag signal PwA
CT becomes Low, and D-FF2 is output at the first vertical synchronization signal.
At the time when the output of the D-FF 22c becomes Low with the third vertical synchronization signal after the output of 2a becomes Low, that is, at the time when the time of two fields has elapsed since the flag signal PwACT became Low. , Flag signal OFF
Ready is set to High.

B-3. Operation of Second Embodiment Next, the operation of the above-described second embodiment will be described.
When the power switch SW is turned off, the power control circuit 11
Sets the flag signal PwACT supplied to the sequence control circuit 20 to Low. In the sequence control circuit 20, when the flag signal PwACT becomes Low, the output of the D-FF 22a supplied to one input terminal of the NOT circuit becomes Low in the first vertical synchronizing signal, so that the flag signal Vwhite becomes High. Become.

When the flag signal Vwhite becomes High, the signal switching circuit 21 outputs the R signal from the RGB decoder 1.
Instead of the GB luminance signal 19, white display data (in the case of normally white) is supplied to the signal driver 4 via the inverting amplifier 3. As a result, the LCD 7 quickly becomes a white screen on the entire surface, and can prevent an afterimage when the power is turned off. When two fields of the vertical synchronizing signal have elapsed, the flag signal OFF which is the output of the NOR circuit 24 is turned off.
Ready becomes High. Flag signal OFF Re
When ady becomes High, the current control circuit 11 sets the current control signal PCS supplied to the power supply 12 to Low and turns off the power supply.

As described above, in the second embodiment described above,
When the power switch is turned off, the video signal is replaced with a white screen, and then the power is turned off. This allows the afterimage of the display screen when the power is turned off to be quickly erased, and the liquid crystal display panel due to the residual voltage. Degradation can be prevented.

[0039]

According to the present invention, when the detecting means detects that the power switch is turned off, the voltage applied to the liquid crystal panel is reduced to zero by the applied voltage attenuating means. Since the power is turned off by the power control means, the afterimage of the display screen when the power is turned off can be quickly erased, and the liquid crystal display panel can be prevented from being deteriorated due to the residual voltage. Can be

According to the second aspect of the present invention, the potential of the plurality of signal lines is made closer to the potential of the common electrode by the applied voltage attenuating means. Since the state is reset to the state before turning on, the afterimage of the display screen when the power is turned off can be quickly erased, and the advantage that the deterioration of the liquid crystal display panel due to the residual voltage can be prevented can be obtained.

According to the third aspect of the present invention, the output of the signal side driving circuit is set to high impedance by the applied voltage attenuating means while the scanning side driving circuit is operated. Since the potential of the signal line becomes the same as the potential of the auxiliary capacitance line CS in a time corresponding to the time constant of the electrostatic protection resistor and the pixel capacitance, the afterimage of the display screen when the power is turned off can be quickly erased. In addition to this, there is obtained an advantage that deterioration of the liquid crystal display panel due to residual voltage can be prevented.

According to the fourth aspect of the present invention, the display voltage signal corresponding to the display screen when the applied voltage to the liquid crystal panel is zero is transmitted to the signal side driving circuit by the applied voltage attenuating means. To supply
The display panel instantly displays an all-white screen (normally white) or an all-black screen (normally black), so that afterimages on the display screen when the power is turned off can be quickly erased and the residual voltage The advantage that deterioration of the liquid crystal display panel due to the above can be prevented can be obtained.

According to the fifth aspect of the present invention, when the detection means detects that the power switch has been turned off, the drive circuit control means keeps the scanning-side drive circuit in operation while keeping the signal on. The output of the side drive circuit is set to high impedance, and when the high impedance state has passed for a predetermined time, the power supply is turned off by the power supply control means. Since the potential of the auxiliary capacitance line CS becomes equal to the potential of the storage capacitor wiring CS in a time corresponding to the constant, the afterimage of the display screen when the power is turned off can be quickly erased, and the deterioration of the liquid crystal display panel due to the residual voltage can be prevented. The advantage that it can be obtained.

According to the present invention, the elapsed time of the high-impedance state of the signal side drive circuit is determined based on the vertical synchronizing signal. In this case, the afterimage of the display screen can be quickly erased, and the liquid crystal display panel can be prevented from being deteriorated due to the residual voltage.

According to the seventh aspect of the present invention, when the detection means detects that the power switch has been turned off, the switching means applies the voltage to the liquid crystal panel generated by the display data signal generation means. The display data signal corresponding to the display screen when the voltage is zero, instead of a normal display data signal, is selectively supplied to the signal-side drive circuit, and then the power is turned off by the power control unit. Therefore, there is an advantage that the afterimage of the display screen when the power is turned off can be quickly erased, and the deterioration of the liquid crystal display panel due to the residual voltage can be prevented.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration of a liquid crystal display device according to a first embodiment of the present invention.

FIG. 2 is a block diagram illustrating a schematic configuration of a signal driver.

FIG. 3 is a circuit diagram showing a configuration of a sequence control circuit.

FIG. 4 is a timing chart for explaining the operation of the first embodiment.

FIG. 5 is a block diagram illustrating a configuration of a liquid crystal display device according to a second embodiment of the present invention.

FIG. 6 is a circuit diagram illustrating a configuration of a sequence control circuit according to a second embodiment.

FIG. 7 is a timing chart for explaining the operation of the second embodiment.

FIG. 8 is a block diagram illustrating a configuration of a conventional liquid crystal display device.

FIG. 9 is a circuit diagram showing a circuit configuration of a liquid crystal display panel.

[Explanation of symbols]

REFERENCE SIGNS LIST 1 RGB decoder 2 controller 3 inverting amplifier 4 signal driver (signal-side drive circuit) 5 scan driver (scan-side drive circuit) 6 amplifier 7 LCD 10 sequence control circuit (applied voltage attenuation means, drive circuit control means) 11 power supply control circuit ( Detection means, power control means) 12 power supply 20 sequence control circuit (display data signal generation means) 21 signal switching circuit (switching means) SW power switch

 ──────────────────────────────────────────────────続 き Continued on the front page F-term (reference)

Claims (7)

[Claims] 1. A plurality of scanning lines, a plurality of signal lines formed so as to be orthogonal to the plurality of scanning lines, and a plurality of signal lines arranged near each intersection of the plurality of scanning lines and the plurality of signal lines. A liquid crystal panel comprising: a switching element; a pixel electrode and an auxiliary capacitance connected to the switching element; an auxiliary capacitance wiring connected to the plurality of signal lines via a resistance element; A liquid crystal display comprising: a scanning side driving circuit for transmitting a scanning driving signal to a scanning line to sequentially perform horizontal scanning; and a signal side driving circuit for transmitting a display data signal corresponding to a video signal to each of the plurality of signal lines. In the device, detecting means for detecting that a power switch of the liquid crystal display device is turned off, and detecting that the power switch is turned off by the detecting means An applied voltage attenuating means for setting the voltage applied to the liquid crystal panel to zero; and a power supply controlling means for turning off the power after the voltage applied to the liquid crystal panel is reduced to zero by the applied voltage attenuating means. A liquid crystal display device comprising: 2. The liquid crystal display device according to claim 1, wherein the applied voltage attenuating unit brings the potentials of the plurality of signal lines closer to the potential of the common electrode. 3. The liquid crystal display device according to claim 2, wherein said applied voltage attenuating means sets the output of said signal side driving circuit to high impedance while operating said scanning side driving circuit. 4. The signal-side driving circuit according to claim 1, wherein the applied voltage attenuating unit supplies a display data signal corresponding to a display screen when the applied voltage to the liquid crystal panel is zero. 2. The liquid crystal display device according to 1. 5. A plurality of scanning lines, a plurality of signal lines formed so as to be orthogonal to the plurality of scanning lines, and a plurality of signal lines arranged near each intersection of the plurality of scanning lines and the plurality of signal lines. A liquid crystal panel comprising: a switching element; a pixel electrode and an auxiliary capacitance connected to the switching element; an auxiliary capacitance wiring connected to the plurality of signal lines via a resistance element; A liquid crystal display comprising: a scanning side driving circuit for transmitting a scanning driving signal to a scanning line to sequentially perform horizontal scanning; and a signal side driving circuit for transmitting a display data signal corresponding to a video signal to each of the plurality of signal lines. In the device, detecting means for detecting that a power switch of the liquid crystal display device is turned off, and detecting that the power switch is turned off by the detecting means While it is operating the said scanning-side drive circuit,
Drive circuit control means for setting the output of the signal side drive circuit to high impedance; and power supply control for turning off the power supply when a state in which the output of the signal side drive circuit is set to high impedance by the drive circuit control means has passed for a predetermined time. And a liquid crystal display device. 6. The liquid crystal display device according to claim 5, wherein the power control unit determines an elapsed time of a high impedance state of the signal side driving circuit based on a vertical synchronization signal. 7. A plurality of scanning lines, a plurality of signal lines formed so as to be orthogonal to the plurality of scanning lines, and arranged near each intersection of the plurality of scanning lines and the plurality of signal lines. A liquid crystal panel comprising: a switching element; a pixel electrode and an auxiliary capacitance connected to the switching element; an auxiliary capacitance wiring connected to the plurality of signal lines via a resistance element; A liquid crystal display comprising: a scanning side driving circuit for transmitting a scanning driving signal to a scanning line to sequentially perform horizontal scanning; and a signal side driving circuit for transmitting a display data signal corresponding to a video signal to each of the plurality of signal lines. A detecting means for detecting that a power switch of the liquid crystal display device is turned off; and a display screen corresponding to a display screen when a voltage applied to the liquid crystal panel is zero. A display data signal generating unit for generating a display data signal; and a display generated by the display data signal generating unit instead of a normal display data signal when the detection unit detects that a power switch is turned off. Switching means for selectively supplying a data signal to the signal-side drive circuit; and after the display data signal generated by the display data signal generation means is supplied to the signal-side drive circuit by the switch means, power is turned off. A liquid crystal display device comprising: a power supply control unit.