JP2003295840A - Liquid crystal display device and its drive control method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a liquid crystal display device capable of avoiding the generation of an after image caused by a residual voltage in each display pixel and suppressing the generation of a display unevenness right after the completion of an after image processing period and the degradation of liquid crystal satisfactorily even when the interrupting operation is performed while the device is being driver for display of image information, and to provide its drive control method. <P>SOLUTION: In the liquid crystal display device which is provided with a liquid crystal display panel 10 in which a plurality of liquid crystal pixels are arranged in a matrix shape and a signal driver 20A for displaying a desired picture information on the display panel 10 by applying liquid crystal application voltage corresponding to a video signal to respective liquid crystal pixels and a scanning driver 30, when the OFF operation of a power source switch SW is detected, a minute signal voltage (for example, a white display voltage) is written in respective display pixels by fixing a signal voltage to be supplied to a signal line Ld and a common signal voltage Vcom to be supplied to a common electrode on specific low levels. <P>COPYRIGHT: (C)2004,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device provided with a liquid crystal display panel including display pixels to which thin film transistors (TFTs) and the like are applied, and in particular, a light source such as a backlight is provided near the liquid crystal display panel. The present invention relates to a reflective liquid crystal display device and a drive control method thereof.

[0002]

2. Description of the Related Art In recent years, as a monitor or display of information equipment such as computers and televisions and video equipment, a conventional display device having a conventional cathode ray tube (CRT) has been replaced with a thin, lightweight, and space-saving type. Liquid crystal display device (Liquid Cry) with various features such as space and power saving
The stal display (LCD) is becoming popular. In addition, even in mobile phones, personal digital assistants (PDAs), digital still cameras, and other imaging devices that have become extremely popular in recent years, the above-mentioned liquid crystal display is used as a display unit for displaying images and character information. The device is applied.

In particular, in the field of portable information equipment and electronic equipment, in order to prolong the driving time by the battery, good image display is achieved without using a light source such as a backlight which consumes a relatively large amount of power. It is known that a reflection type liquid crystal display device capable of performing the above is applied.

A conventional liquid crystal display device will be briefly described below. FIG. 5 is a block diagram showing a configuration of a conventional TFT type liquid crystal display device, and FIG. 6 is a main part circuit diagram showing a circuit configuration of a liquid crystal display panel. Here, a liquid crystal display device including an active matrix liquid crystal display panel is shown. As shown in FIG. 5, the liquid crystal display device is roughly classified into a liquid crystal display panel 10, a signal driver (source driver) 20, and a scanning driver (gate driver) 30.
, RGB decoder 40, inverting amplifier 50, LCD
A controller 60 and a common signal drive amplifier (for convenience of illustration, referred to as “drive amplifier” in the figure) 70 are included.

The liquid crystal display panel 10 is, as shown in FIG. 6, between signal lines (data lines) Ld arranged in the column direction and scanning lines (arranged in the row direction) between the transparent substrates facing each other. Gate line Lg, a plurality of pixel electrodes arranged in the vicinity of the intersections of the signal lines Ld and the scanning lines Lg arranged in a matrix, and a single common electrode arranged so as to face each pixel electrode. (Not shown; common signal drive amplifier 70 described later causes common signal voltage Vco
m is supplied), a liquid crystal capacitance (pixel capacitance) Clc made of liquid crystal filled and held between the pixel electrode and the common electrode, and the liquid crystal capacitance Clc are arranged in parallel, and the other end side is the capacitance wiring Lc.
Via a predetermined voltage Vcs (for example, common signal voltage Vco
m), a storage capacitance (auxiliary capacitance) Ccs for holding the signal voltage applied to the liquid crystal capacitance Clc, a gate connected to the scan line Lg, a source connected to the pixel electrode, and a signal line Ld. A thin film transistor (hereinafter, referred to as a “pixel transistor”) TFT having a drain connected to, and an electrostatic protection resistance Rcs connected between the capacitance line Lc (predetermined voltage Vcs) and each signal line Ld. , Are provided. Here, a display pixel is configured by the liquid crystal capacitance Clc and the storage capacitance Ccs arranged near each intersection of the signal lines Ld and the scanning lines Lg arranged in a matrix.

In such a structure, as is well known, in the reflection type liquid crystal display panel, a backlight (light source) is provided on the back side of the liquid crystal display panel 10 as in the case of a transmission type liquid crystal display panel. ) Is not provided, as described later, in order to make the image information displayed by controlling the alignment state of the liquid crystal molecules in each display pixel good, the rear side of the liquid crystal display panel 10 has a viewing side. A reflection plate or a reflection film (not shown) made of a metal film or the like is provided so as to reflect the light incident from.

The signal driver 20 includes the above-mentioned signal lines L.
d is connected to the RGB decoder 40 based on a horizontal control signal output from an LCD controller 60 described later.
The brightness signals of R (red), G (green), and B (blue) colors supplied from are stored in units of one row, and display signal voltages corresponding to the brightness signals are sequentially supplied to each signal line Ld. Further, the scan driver 30 is connected to each of the scan lines Lg,
Based on the vertical control signal output from the LCD controller 60, a scanning signal (gate pulse) is sequentially applied to each scanning line Lg to bring it into a selected state, and the signal line Ld
A display signal voltage corresponding to the luminance signal supplied from the signal driver 20 via the signal line Ld is applied to the display pixel (pixel electrode) at the position intersecting with.

The RGB decoder 40 extracts, for example, a horizontal synchronizing signal H, a vertical synchronizing signal V and a composite synchronizing signal CSY from a video signal (composite video signal) supplied from the outside of the liquid crystal display device, and causes the LCD controller 60 to do so. In addition to supplying, pedestal clamp, chroma processing, etc. are executed to extract each color signal (RGB signal) of R, G, B included in the video signal and output to the inverting amplifier 50. The inversion amplifier 50 inverts the polarity of the RGB signal extracted by the RGB decoder 40 based on the polarity inversion signal (field / line inversion signal) FRP or the like supplied from the LCD controller 60 to generate an RGB inversion signal. Then, the luminance signal is output to the signal driver 20.

The LCD controller 60 has a horizontal synchronizing signal H and a vertical synchronizing signal V supplied from the RGB decoder 40.
The polarity reversal signal FRP and the like are generated based on the composite sync signal CSY and output to the inverting amplifier 60 and the common signal drive amplifier 70, and the horizontal control signal (signal line output enable signal, clear signal, etc.) and By generating vertical control signals (gate start signal, gate clock, gate line output enable signal, etc.) and supplying them to the signal driver 20 and the scan driver 30, respectively, each display pixel (pixel electrode) at a predetermined timing. A display signal voltage corresponding to the luminance signal is applied to the liquid crystal display panel 10 to control display of predetermined image information based on the video signal on the liquid crystal display panel 10.

The common signal drive amplifier 70 has the above-mentioned L level.
Polarity inversion signal FR output from the CD controller 60
Based on P, drive control is performed so that the polarity of the common signal voltage Vcom applied to the common electrode commonly provided to each display pixel is inverted with respect to the display signal voltage applied to the pixel electrode of each display pixel. To do.

In the liquid crystal display device having such a configuration, a scanning signal is sequentially applied to each row (scanning line Lg) to bring it into a selected state, and the display signal voltage supplied to the signal line Ld is supplied via the pixel transistor TFT. By applying to each pixel electrode, the potential difference (pixel potential) between the display signal voltage corresponding to the luminance signal and the common signal voltage Vcom applied to the common electrode is charged in the liquid crystal capacitance Clc of each display pixel, and the potential difference is applied. The orientation state of the liquid crystal molecules in each display pixel is controlled according to. As a result, desired image information is displayed on the liquid crystal display panel 10.

In the liquid crystal display device as described above, when the power source of the device is turned off (off) in a display driving state of image information, the signal driver 20 outputs the signal line Ld.
The supply of the display signal voltage to the display circuit is cut off to enter the high impedance state, and the scan signal applied from the scan driver 30 to the scan line Lg enters the inactive state (low level). Is in a state of holding the potential immediately before the power supply of the apparatus is shut off. The potential (residual voltage) held in the display pixel is applied to the peripheral wiring (scanning line Lg, signal line Ld, capacitance wiring L).
c)) or a leak current is generated through the pixel transistor TFT, etc., and is gradually discharged over time, and finally the common electrode (common signal voltage Vcom).
It becomes the same potential as.

Here, until the residual voltage becomes a potential substantially equal to the common signal voltage Vcom due to the leakage current,
In some cases, it takes a relatively long time of several seconds, so the display image gradually disappears (or immediately before) when the power to the device is shut off (or the afterimage changes).
Will be recognized by the human eye. Such a change in the display state of the liquid crystal display panel causes a change in the liquid crystal display device including the transmissive liquid crystal display panel and the backlight.
It is hardly visible by controlling the backlight to be turned off almost at the same time as the power-off operation of the device, but in the reflective liquid crystal display device, the change in the above display state is visually recognized with the passage of time. Therefore, there is a problem in that the user feels unsightly or feels uncomfortable.
Further, every time the power source of the device is turned off, a direct current voltage component based on the residual voltage is applied to the liquid crystal molecules of each display pixel, which causes a problem that the liquid crystal is likely to be deteriorated.

Therefore, as a method for solving the problem of the residual voltage which occurs when the power supply of the apparatus is cut off, a technique described in, for example, Japanese Patent Laid-Open No. 2000-163025 is known in the past. ing. Specifically, for example, in Japanese Unexamined Patent Publication No. 2000-163025, the output of the signal driver 20 is controlled to a high impedance state while maintaining the scan driver 30 in an active state at the time of a power-off operation of the apparatus, By setting the potential of the line Ld to the same potential as the potential Vcs (common signal voltage Vcom) of the capacitance line Lc in a sufficiently short time (for example, about 1 ms) according to the time constant of the electrostatic protection resistance Rcs and the liquid crystal capacitance Clc. , A configuration in which the applied voltage in each display pixel is reset to zero to suppress the influence of the residual voltage (that is, the occurrence of an afterimage on the display screen, deterioration of the liquid crystal, etc.).

Further, in the above publication, in a liquid crystal display panel which does not include the above-mentioned static electricity protection resistor Rcs, a white display voltage is supplied as a video signal and displayed on the liquid crystal display panel at the time of power-off operation of the device. There is also described a configuration in which the influence of the above-mentioned residual voltage is suppressed by rapidly switching the image information to the white display screen and then controlling the signal driver and the scan driver in the inactive state.

As described above, in the prior art, as a method of suppressing the influence of the residual voltage when the power source of the apparatus is cut off, (1) the output of the signal driver is output during a predetermined period (afterimage processing period) after the power source of the apparatus is cut off. Pixel potential (residual voltage) by keeping the high impedance state and driving the scan driver for several fields to put the display pixel in the selected state
Is approximated to the common voltage Vcom (2) The potential of the signal line is approximated to the common signal voltage Vcom with a predetermined time constant (3) A white display voltage is supplied from the signal driver as a display signal voltage to each display pixel There has been known a method of suppressing the pixel potential in each display pixel by writing white display data to the display pixel.

[0017]

However, the afterimage processing method as described above has the following problems. That is, (a) When the operation control for continuing the line inversion drive is performed in the afterimage processing period after the power source of the apparatus is cut off, the polarity of the common signal Vcom is inverted every line by the polarity inversion signal FRP. Therefore, immediately after the afterimage processing period ends, the pixel potential (accumulated charge) is increased for each scanning line due to the deviation (center deviation) of the common signal voltage Vcom from the center voltage. Amount), which may cause a difference in discharge time. Therefore, there is a problem that such a difference in discharge time may cause a striped pattern or the like on the display screen, which may be visually recognized as display unevenness.

(A) Further, as described above, since the supply of the common voltage Vcom is controlled so as to perform the line inversion drive, the voltage level of the common signal voltage Vcom becomes high immediately after the afterimage processing period ends. It is uncertain (uncertain) whether it will be high or low level. If the afterimage processing period ends at the timing when the common signal voltage Vcom becomes high level, the high level common signal voltage V
From com to a predetermined low voltage level Vss (eg ground potential;
Bias resistance of common signal drive amplifier and AC / DC (AC / DC)
There is a problem that the time constant defined by the coupling capacitance is required and that the liquid crystal may be deteriorated by the residual voltage (DC voltage component) applied to each display pixel at this time. It was

Therefore, in view of the above-mentioned problems, the present invention eliminates the residual image caused by the residual voltage in each display pixel even when the device power-off operation is performed in the image information display drive state. An object of the present invention is to provide a liquid crystal display device and a drive control method therefor capable of satisfactorily suppressing the occurrence of display unevenness and the deterioration of liquid crystal immediately after the end of the afterimage processing period while avoiding the occurrence.

[0020]

A liquid crystal display device according to claim 1, wherein a plurality of scanning lines and a plurality of signal lines arranged orthogonal to each other are provided in the vicinity of respective intersections of the scanning lines and the signal lines. A liquid crystal display panel having a plurality of display pixels composed of pixel electrodes arranged in a matrix through a connected switch element and a common electrode provided so as to face the pixel electrodes, and the plurality of scanning lines. Scanning side drive means for sequentially applying a scanning drive signal to the display pixels to scan the display pixels, signal side drive means for applying a display signal voltage based on a predetermined video signal to each of the plurality of signal lines, and the common electrode. A common signal drive means for supplying a predetermined common signal voltage to the liquid crystal display device, and a power cutoff detection means for detecting that the device power supply of the liquid crystal display device has been cut off. A display pixel control for controlling a fixed voltage to be applied between the signal line and the common electrode for a predetermined period when the power cutoff detecting unit detects a power-off operation of the device. Means and a power supply control means for cutting off the supply of drive power to the liquid crystal display device after the lapse of the predetermined period.

A liquid crystal display device according to a second aspect is the first aspect.
In the liquid crystal display device described above, the display pixel control unit controls at least setting so as to apply a signal voltage having a constant signal level from the signal side driving unit to the pixel electrode of the display pixel via the signal line. It is characterized by doing.

A liquid crystal display device according to a third aspect is the second aspect.
In the liquid crystal display device described above, the display pixel control unit is set and controlled so that a signal voltage having a constant signal level is applied from the common signal driving unit to the common electrode. The liquid crystal display device according to claim 4 is the liquid crystal display device according to claim 2 or 3, wherein the display pixel control means is applied to a signal voltage applied to a pixel electrode of the display pixel and the common electrode. It is characterized in that the signal voltages are set and controlled so as to approximate each other.

The liquid crystal display device according to claim 5 is the liquid crystal display device according to claim 4.
In the liquid crystal display device described above, the display pixel control means, a signal voltage applied to a pixel electrode of the display pixel,
The signal voltage applied to the common electrode is set and controlled to a specific low signal level. Further, the liquid crystal display device according to claim 6 is the liquid crystal display device according to claim 5, wherein the display pixel control means applies at least a signal voltage applied to a pixel electrode of the display pixel to the liquid crystal display panel. It is characterized in that the setting is controlled to a signal level when driving white display.

According to a seventh aspect of the present invention, there is provided a drive control method for a liquid crystal display device, wherein a scanning line and a signal line are provided in the vicinity of respective intersections of a plurality of scanning lines and a plurality of signal lines arranged orthogonal to each other. Via the connected switch element,
In a display driving method of a liquid crystal display device, which displays desired image information on a liquid crystal display panel having a plurality of display pixels composed of pixel electrodes arranged in a matrix and a common electrode provided so as to face the pixel electrodes. Detecting a power-off operation of the device power source in the liquid crystal display device for a predetermined period,
A first signal voltage having a specific low signal level is fixedly applied to each of the plurality of signal lines, and a specific low signal level is applied to the common electrode;
It is characterized in that a second signal voltage, which is close to the signal voltage of, is fixedly applied. The drive control method for a liquid crystal display device according to claim 8, wherein in the liquid crystal display device according to claim 7, the first signal voltage is set to a signal level for white display driving of the liquid crystal display panel. And is applied to the pixel electrode without inverting and driving the signal polarity of the signal voltage.

That is, the liquid crystal display device and the drive control method thereof according to the present invention, in the liquid crystal display device provided with the reflection type liquid crystal display panel, when the operation of cutting off (turning off) the device power supply of the liquid crystal display device is detected. Pixel electrodes forming each display pixel from the signal side driving means through the signal line during a predetermined period (afterimage processing period) after the power source is cut off until the driving power is actually cut off from the power source. On the other hand, the first signal voltage having a specific low signal level (for example, a predetermined low level for performing white display drive or 0V) is fixedly applied without performing the signal polarity inversion drive. A second signal having a specific low signal level (low-level common signal voltage) from the common signal driving means to the common electrode and approximating the first signal voltage
The signal voltage of is fixedly applied.

As a result, a predetermined voltage (for example, white) is applied to the display pixels (between the pixel electrode and the common electrode) of all lines forming the liquid crystal display panel during the afterimage processing period set after the power-off operation of the device. 1 for driving display
(V or 0V) is uniformly written, the pixel potential (accumulated charge amount) for each scanning line is made uniform, and immediately after the end of the afterimage processing period (immediately after the drive power is cut off).
It is possible to suppress the occurrence of display unevenness such as a striped pattern on the display screen.

Further, since the signal voltage applied to the common electrode is always fixed at the low level during the afterimage processing period, the common signal voltage Vcom at the end of the afterimage processing period.
The discharge operation does not occur, it is possible to suppress the change in display state (occurrence of afterimage), and the high residual voltage (DC voltage component) is not applied to each display pixel. Deterioration can be suppressed.

[0028]

BEST MODE FOR CARRYING OUT THE INVENTION A liquid crystal display device and a drive control method thereof according to the present invention will be specifically described below with reference to embodiments. First, an embodiment of a liquid crystal display device according to the present invention will be described with reference to the drawings. Here, a configuration including an active matrix type liquid crystal display panel as a liquid crystal display device will be described, and the same components as those of the above-described conventional technique (FIGS. 5 and 6) will be denoted by the same reference numerals and description thereof will be omitted. To simplify.

FIG. 1 is a block diagram showing an embodiment of a liquid crystal display device according to the present invention. Here, the same components as those of the above-described conventional technique are designated by the same reference numerals, and the description thereof will be simplified or omitted. As shown in FIG. 1, the liquid crystal drive device according to the present embodiment is roughly classified into the related art (see FIG.
Liquid crystal display panel 10 having a configuration equivalent to that of the above), a scan driver (scan side driving means) 30, an RGB decoder 40, an inverting amplifier 50, and an LCD controller 60.
And a common signal drive amplifier (common signal drive means) 70
In addition, a signal driver (signal side driving means) 20A having a configuration unique to this embodiment, a power supply control circuit (power cutoff detection means, power supply control means) 80, a sequence control circuit (display pixel control means) 90, And a power supply 100.

Here, in the liquid crystal display device according to this embodiment, the LCD controller 60 and the signal driver 2 are used.
0, the scan driver 30, the inverting amplifier 50, and the common signal drive amplifier 70 are provided so as to interpose a sequence control circuit 90, and the sequence control circuit 90 provides a predetermined timing based on the vertical synchronizing signal V. Then, the horizontal control signal output from the LCD controller 60 is supplied to the signal driver 20, the vertical control signal is supplied to the scanning driver 30, and the polarity inversion signal FRP is supplied to the inverting amplifier 50 and the common signal drive amplifier 70. At the same time, the power cutoff detection signal P from the power control circuit 80
Based on wACT, a power cutoff signal OFFready is output to control the supply state of drive power to each component of the liquid crystal display device.

The above-mentioned components will be described in detail below. 2 is a block diagram showing a schematic configuration of a signal driver applied to the liquid crystal display device according to the present embodiment, and FIG. 3 is a configuration of a sequence control circuit applied to the liquid crystal display device according to the present embodiment. It is a circuit block diagram which shows an example. The liquid crystal display panel 10 has the above-mentioned conventional technology (FIG. 6).
Similarly, a plurality of pixel electrodes arranged in the vicinity of each intersection of the signal lines Ld and the scanning lines Lg arranged in a matrix (column direction and row direction) between opposing transparent substrates (not shown). And for holding a display pixel (liquid crystal capacitance) composed of a single common electrode facing each pixel electrode, a liquid crystal filled between the pixel electrode and the common electrode, and a display signal voltage applied to the display pixel. Storage capacity (auxiliary capacity)
A signal line Ld, a scanning line Lg, and a pixel transistor (switch element) connected to each display pixel,
It is configured with.

The signal driver 20 applied to this embodiment
2, the shift register 21 that sequentially shifts the sampling start signal SRT in a predetermined direction based on the shift clock CK, and the shift register 2
Based on the shift output (sampling pulse) output from 1, the luminance signals (RGB inversion signals) of the RGB colors supplied via the RGB decoder 40 and the inversion amplifier 50 are fetched and held for each row (sampling / sampling / Hold), a sample / hold circuit 22 and a buffer circuit 23 that output the display signal voltage Vsig corresponding to the luminance signal to each signal line Ld at a predetermined timing, and a signal line output enable signal (hereinafter, simply referred to as “output The switch circuit 24 controls the output state of the display signal voltage Vsig to each signal line Ld based on OE, and the power supply 100 to each signal line Ld based on the clear signal CLR. Power supply voltage VDDC or a specific low level supplied from the sequence control circuit 90 (Low signal level; eg V
L = 1V or Vss = 0V) (first voltage)
Switch circuit 25 for controlling the application of any one of the

Here, the sampling start signal SR
T, the shift clock CK, the signal line output enable signal OE, and the clear signal CLR are generated by the LCD controller 60 based on the horizontal synchronizing signal H supplied from the RGB decoder 40, and the sequence control circuit 9
It is supplied to the signal driver 20 as a horizontal control signal via 0. The signal voltage supplied to each signal line Ld via the switch circuit 25 will be described later in detail.
In the display drive state in which the power switch SW is turned on and drive power is being supplied to each component of the liquid crystal display device, power is supplied at a predetermined timing based on the signal level of the clear signal CLR output from the LCD controller 60. The voltage VDDC is set to be applied to each signal line Ld, and on the other hand, during the predetermined period (afterimage processing period) until the supply of drive power is cut off after the power switch SW is turned off, The clear signal CLR is always at a high level, and is set so that a signal voltage (VL = 1V or Vss = 0V) having a specific low level is applied to each signal line Ld.

Further, the scan driver 30 is a vertical control signal (gate line output enable signal GOE, gate clock GPCK, generated by the LCD controller 60 and supplied through the sequence control circuit 90).
Based on the gate start signal GSRT, etc.), scanning signals (gate pulse; scanning drive signal) are sequentially applied to each scanning line Lg to set each scanning line Lg to the selected state.

RGB decoder 40 and inverting amplifier 50
Is a horizontal sync signal H, a vertical sync signal V, a composite sync signal CS
Y is extracted and supplied to the LCD controller 60, and R, G, and B color signals (RG
The B signal) is extracted, inverted by the inverting amplifier 50 based on the polarity inversion signal FRP supplied from the LCD controller 60, and output to the signal driver 20 as a luminance signal (RGB inversion signal).

The LCD controller 60 has a horizontal synchronizing signal H and a vertical synchronizing signal V supplied from the RGB decoder 40.
And a polarity inversion signal FRP or the like based on the composite sync signal CSY, and outputs the polarity inversion signal FRP to the inversion amplifier 60 and the common signal drive amplifier 70 via the sequence control circuit 90. And the signal driver 20 and the scan driver 3 at a predetermined timing via the sequence control circuit 90.
Supply to 0.

The power control circuit 80 has at least a function of detecting that the power switch SW of the liquid crystal display device is turned on / off (device power is turned on / off).
When the power switch SW is turned on, a flag signal (power cutoff detection signal) P supplied to the sequence control circuit 90.
When wACT is set to a high level (a flag is set) and the power switch SW is turned off, the flag signal PwAC
Control for switching T to low level (lowering the flag) is performed.

In the sequence control circuit 90, the power supply control circuit 80 executes a series of drive control operations, which will be described later, based on the flag signal PwACT and the vertical synchronizing signal V, and then the flag signal (power cutoff signal). OFFre
When ady is supplied, the power supply control signal PCS supplied to the power supply 100 is controlled to be switched from high level to low level to control each component of the liquid crystal display device (the signal driver 20, the scan driver 30, the RGB decoder 40, the LCD. Control is performed to cut off the supply of drive power to the controller 60 or the like).

Here, the power switch SW is a switch for supplying (turning on the power supply of) the drive power to each component of the liquid crystal display device and shutting it off, and the user of the liquid crystal display device arbitrarily selects it. It is turned on and off. Also,
The power supply 100 switches the supply state of drive power to each component of the liquid crystal display device based on the power supply control signal PCS supplied from the power supply control circuit 80.

The sequence control circuit 90 mainly supplies the power interruption detection signal PwACT output from the power control circuit 80.
The horizontal control signal output from the LCD controller 60 and supplied to the signal driver 20, the vertical control signal supplied to the scan driver 30, and the inverting amplifier 50 and the common signal drive amplifier 70 based on the signal level of It has a function of controlling the supply state of the polarity inversion signal FRP to be supplied.

Specifically, the sequence control circuit 90
For example, as shown in FIG. 3, the vertical synchronization signal V is used as a clock input, and the flip-flop circuits 91a to 91e are connected in series and are configured to define an operation timing (processing period) in a drive control operation described later. Flip-flop group 91 and AND logic gates 92a to 92
c, an inverter 92d, and an OR logic gate 92e, a group of logic gates 92 for controlling the supply state of some horizontal control signals (output enable signal OE, clear signal CLR) and polarity inversion signal FRP, and an OR logic gate. The power source 10 is composed of an inverter 93a and an inverter 93b.
A group of logic gates 93 for controlling the supply state of drive power at 0, and vertical control signals (gate line output enable signal GOE, gate clock GPCK, gate start signal GSRT) other than the horizontal control signal and the polarity inversion signal FRP. AND logic gate 94 for controlling the supply state of (in some embodiments, a plurality of logic gate groups may be provided in parallel).

Here, the flip-flop group 91 includes a power shutoff detection signal PwAC output from the power control circuit 80.
T is the input of the first-stage flip-flop circuit 91a,
The power cutoff detection signal PwA is synchronized with the rising timing of the vertical synchronization signal V supplied from the LCD controller 60 to each of the flip-flop circuits 91a to 91e.
The signal level of CT is sequentially shifted.

In the logic gate group 92, the AND logic gate 92a uses the shift output output from the first-stage flip-flop circuit 91a as one input and the output enable signal OE supplied from the LCD controller 60 as the other input. , And outputs an output enable signal OEout based on a logical product (AND logic) of both inputs to the signal driver 20. AND logic gate 92b
Outputs the logical product output of both inputs to the OR logic gate 92e of the next stage by using the shift output output from the flip-flop circuit 91a as one input and the clear signal CLR supplied from the LCD controller 60 as the other input. To do.

The OR logic gate 92e has the logical product output of the AND logic gate 92b as one input and the inverted signal of the shift output output from the flip-flop circuit 91a (the inverted output of the inverter 92d) as the other input. Clear signal C based on the logical sum (OR logic) of both inputs
LRout is output to the signal driver 20. Furthermore, A
The ND logic gate 92c receives the shift output output from the first-stage flip-flop circuit 91a as one input and
Polarity inversion signal FR supplied from the CD controller 60
The polarity inversion signal FRPout based on the logical product of both inputs is output to the inverting amplifier 50 and the common signal drive amplifier 70 with P as the other input.

In the logic gate group 93, the OR logic gate 93a has the shift output output from the first stage flip-flop circuit 91a as one input and the shift output output from the final stage flip-flop circuit 91e as the other input. As an output, the output based on the logical sum of both inputs is output to the inverter 93b, and the inverter 93b inverts the output of the OR logic gate 93a to generate the power cutoff signal O.
It is output to the power supply control circuit 80 as FFready.

The AND logic gate 94 (or AN
The D logic gate group) receives the output of the OR logic gate 93a as one input, and is supplied from the LCD controller 60 except for the horizontal control signal (output enable signal OE, clear signal CLR) and the polarity inversion signal FRP. A horizontal control signal and a vertical control signal (gate enable signal GOE, gate clock GPCK, gate start signal GSRT, etc.) that are generated are used as the other inputs, and signals based on the logical product of both inputs are output to the signal driver 20 and the scan driver 30. To do.

That is, in the sequence control circuit 90 according to this embodiment, when the power switch SW is turned off and the power cutoff detection signal PwACT output from the power control circuit 80 becomes low level, the vertical synchronizing signal V of the vertical sync signal V is output. Based on the timing, each flip-flop circuit 91a
Low-level shift signals are sequentially transferred between ~ 91e,
The operation timing (processing period) in the drive control operation described later is defined according to the number of stages of each flip-flop circuit.

As a result, the signal level of the shift output output from the first-stage flip-flop circuit 91a becomes low level in synchronization with the timing of the vertical synchronizing signal immediately after the power switch SW is turned off, and each AND logic gate. Since it is input to one input terminal of the inverters 92a to 92c and to the input terminal of the inverter 92d, LC
Through the sequence control circuit 90, regardless of the signal levels of the output enable signal OE, the clear signal CLR, and the polarity inversion signal FRP that are output from the D controller 60 and are input to the other input ends of the AND logic gates 92a to 92c. Output enable signal OEout supplied to the signal driver 20 and the inverting amplifier 50
Also, the polarity inversion signal FRPout supplied to the common signal drive amplifier 70 is fixed at a low level, and the clear signal CLRout is fixed at a high level.

Further, based on the timing of the vertical synchronizing signal V, OR is performed when the signal levels of the shift outputs output from the first-stage flip-flop circuit 91a and the final-stage flip-flop circuit 91e both become low levels. Since the inputs to the respective input terminals of the logic gate 93a are both at the low level, the power cutoff signal OFFready supplied to the power supply control circuit 80 is inverted by the inverter 93b to become the high level, and the drive power from the power supply 100 is supplied. The supply is cut off.

At this time, the AND logic gate 94 (or
Since the signal level input to one input terminal of the AND logic gate group) becomes a low level, the LCD controller other than the horizontal control signal (the output enable signal OE, the clear signal CLR) and the polarity inversion signal FRP is used. Sequence control regardless of the signal levels of the horizontal control signal and the vertical control signal (gate enable signal GOE, gate clock GPCK, gate start signal GSRT, etc.) that are supplied from 60 and input to the other input terminal of the AND logic gate 94. Signal driver 20 via circuit 90
The signals (gate line output enable signal GOE, gate clock GPCK, gate start signal GSRT, etc.) supplied to the scan driver 30 are at a low level.

On the other hand, in the sequence control circuit 90, when the power switch SW is turned on and the power cutoff detection signal PwACT output from the power control circuit 80 becomes high level, the sequence control circuit 90 determines the timing based on the timing of the vertical synchronizing signal V. The high-level shift signal is sequentially transferred between the flip-flop circuits 91a to 91e. As a result, the signal level of the shift output output from the first-stage flip-flop circuit 91a becomes high level in synchronization with the timing of the vertical synchronization signal immediately after the power switch SW is turned on, and the AND logic gates 92a to 92c. Is input to one input terminal of the inverter 92d as well as to the input terminal of the inverter 92d,
Based on the signal levels of the output enable signal OE, the clear signal CLR, and the polarity inversion signal FRP input to the other input ends of the AND logic gates 92a to 92c, the signal driver 20 is passed through the sequence control circuit 90.
To the output enable signal OEout and the clear signal CLRout, and the polarity inversion signal FR supplied to the inverting amplifier 50 and the common signal drive amplifier 70.
The signal level of Pout is fixed.

That is, when the signal levels of the output enable signal OE or the clear signal CLR and the polarity inversion signal FRP output from the LCD controller 60 are low levels, the signal driver 20 and the inverting amplifier 50,
For the common signal drive amplifier 70, a low level output enable signal OEout or a clear signal CLRo
ut and the polarity inversion signal FRPout are output respectively, and when the signal levels of the output enable signal OE or the clear signal CLR and the polarity inversion signal FRP output from the LCD controller 60 are high levels, the signal driver 2
0, inverting amplifier 50, common signal drive amplifier 70, high level output enable signal OEout
Alternatively, the clear signal CLRout and the polarity inversion signal FRPout are output.

Based on the timing of the vertical synchronizing signal V, at least the first stage flip-flop circuit 91a
Of the shift outputs output from the flip-flop circuit 91e at the final stage and the signal level of one of the shift outputs becomes the high level, the input to any one of the input terminals of the OR logic gate 93a becomes high. Since the power supply cutoff signal OFFready is supplied to the power supply control circuit 80, the power supply cutoff signal OFFready is inverted by the inverter 93b and becomes a low level, and the drive power supply from the power supply 100 is controlled to continue.

At this time, the AND logic gate 94
(Or, the signal level input to one input terminal of the AND logic gate group) becomes high level, so that the output enable signal output from the LCD controller 60 and input to the other input terminal of the AND logic gate 94. O
E, horizontal control signals other than the clear signal CLR and vertical control signals (gate line output enable signal GO
E, gate clock GPCK, gate start signal GS
The signal level of each signal supplied to the signal driver 20 and the scan driver 30 is determined based on the signal level of (RT, etc.).

Next, the drive control operation (particularly, the control operation when the power switch is turned off) in the liquid crystal display device having the above-described structure will be described with reference to the drawings. FIG. 4 is a timing chart showing the drive control operation in the liquid crystal display device according to the present embodiment. Here, description will be given with reference to each configuration of the above-described liquid crystal display device as appropriate.

As shown in FIG. 4, first, in a display drive state in which desired image information based on a video signal is displayed on the liquid crystal display panel 10, a user or the like turns on the power switch S.
When W is turned off, the power supply control circuit 80 switches the flag signal (power supply cutoff detection signal) PwACT supplied to the sequence control circuit 90 to a low level.

In the sequence control circuit 90, when the low level power cutoff detection signal PwACT is input,
Immediately after that, at the rising timing of the vertical synchronizing signal V,
Since the signal level of the shift output output from the flip-flop circuit 91a and input to one input terminal of the AND logic gates 92a to 92c becomes low level, the clear signal CLR and the output enable signal OE supplied from the LCD controller 60. Also, regardless of the signal level of the polarity inversion signal FRP, the low level output enable signal O
Eout and the high level clear signal CLRout are output to the signal driver 20, and the low level polarity inversion signal FRPout is output to the inverting amplifier 50 and the common signal drive amplifier 70.

In the signal driver 20, the output enable signal OEout (OE in FIG. 2) supplied via the sequence control circuit 90 becomes low level and the clear signal CLRout (CL in FIG. 2).
R) becomes high level, the switch circuit 24
Is turned off and the switch circuit 25 is turned on. At this time, the signal voltage supplied to the switch circuit 25 is switched and controlled from the power supply voltage VDDC to a specific low-level signal voltage by turning off the power switch SW. As a result, the sample and hold circuit 2
The supply of the display signal voltage Vsig or the power supply voltage VDDC from 2 to each signal line Ld is cut off, and a specific low level signal voltage (VL or Vss) is fixedly supplied without line inversion driving. . Here, in the present embodiment, the specific low level signal voltage is set to, for example, VL = 1V or Vss = 0V.

On the other hand, at this timing, since the shift output from the final stage flip-flop circuit 91e is in the high level state and is input to the one input terminal of the OR logic gate 93a, the OR logic gate 93a is input. 93a
Irrespective of the signal level of the signal voltage input to the other input terminal (shift output from the first-stage flip-flop circuit 91a), a high-level signal is output from the inverter 93b.
And an AND logic gate 94.

As a result, the sequence control circuit 90 sends the power supply control circuit 80 a low-level power cutoff signal OFFre.
When ady is output, a horizontal control signal other than the output enable signal OE and the clear signal CLR supplied from the LCD controller 60, and a vertical control signal (gate line output enable signal GOE, gate clock GPCK, gate start signal) GSRT
Are output to the signal driver 20 and the scan driver 30 at the same signal level, and at least the scan driver 30 maintains an active state.

A state in which a specific low-level signal voltage is fixedly applied to each signal line Ld by the signal driver 20 and line scanning by the scanning driver 30 is continued and held is based on the vertical synchronizing signal V. It is continued for an appropriate field period (corresponding to the afterimage processing period). That is, the sequence control circuit 90 shown in FIG.
, The low-level power cutoff detection signal PwACT input to the first-stage flip-flop circuit 91a is sequentially shifted, and the scan driver 3 is operated for four field periods until the final-stage flip-flop circuit 91e outputs the same.
The scanning line Lg is sequentially scanned by 0, and a specific low-level signal voltage supplied from the signal driver 20 is written in each display pixel via each signal line Ld.

Here, in the liquid crystal display device according to the present embodiment, the polarity inversion signal FRPout is set to the low level by the sequence control circuit 90 at the rising timing of the vertical synchronizing signal V immediately after the power switch SW is turned off. The common signal voltage Vcom supplied to the common electrode of the liquid crystal display panel 10 is fixed to a specific low level (Vss = 0V).

Therefore, after the rising timing of the vertical synchronizing signal V immediately after the power switch SW is turned off, for example, each signal line Ld is held for a predetermined period corresponding to the number of stages of the flip-flop circuits constituting the sequence control circuit 90. Has a specific low level (VL = 1V, or
Since the signal voltage of Vss = 0V) is applied and the common signal voltage Vcom of a specific low level (Vss = 0V) is also applied to the common electrode, the potential difference applied to the liquid crystal of each display pixel. Will be set to a minute voltage of approximately 1 V or less. It should be noted that when the above-mentioned specific low-level signal voltage is set and controlled to VL = 1V, the potential difference (approximately 1V) applied to the liquid crystal of each display pixel is applied when white display driving is performed in the liquid crystal display panel. It corresponds to the voltage (white display voltage).

Then, after the lapse of the predetermined period, a vertical control signal (gate line output enable signal GOEout, gate clock GP to the scan driver 30 is outputted.
CKout and gate start signal GSRTout) are cut off and controlled to an inactive state, and a high-level power supply cutoff signal OFFready is output from the sequence control circuit 90 to the power supply control circuit 80 to supply the power supply 100.
The supply of drive power from each device to each component of the liquid crystal display device is cut off.

According to such a series of drive control operations,
In the afterimage processing period after the power switch SW is turned off, immediately after the start of the period, the common signal voltage Vcom is fixed to the low level, and the white display is driven via the signal line without line inversion driving. By applying a fixed low level (VL = 1V) or 0V signal voltage, a uniform minute voltage (white display voltage) is written in the display pixels of all scanning lines. The afterimage on the display screen can be quickly erased by suppressing the difference in the writing voltage between them.

Here, in the present embodiment, for example, the signal voltage VL = 1V is written to all lines during the afterimage processing period, but the signal voltage is an extremely low voltage and the application time is also. Since it is extremely short (for example, about 4 field periods), it is possible to favorably suppress the deterioration of the liquid crystal due to the application of the signal voltage (DC voltage component). In the drive control operation, the common signal voltage Vcom is controlled so as to be fixed at a low level without fail, so that the screen display changes before and after the afterimage processing period ends (that is, before and after the power-off operation of the apparatus). It is also possible to prevent the occurrence of display unevenness.

The sequence control circuit shown in each of the above-described embodiments is merely an example of a circuit configuration applicable to the present invention, and the present invention is not limited to this. That is, based on the power cutoff detection signal PwACT output from the power supply control circuit, the signal voltage supplied to the signal line and the common signal voltage supplied to the common electrode are fixed to a specific low level, and both signals are fixed. Any other circuit configuration can be used as long as the application timing and signal level of the horizontal control signal, the vertical control signal, the polarity inversion signal, etc. can be controlled so that the potential difference (pixel potential) is minimized. May be.

[0068]

According to the liquid crystal display device and the drive control method thereof according to the present invention, in a liquid crystal display device having a reflection type liquid crystal display panel, an operation for cutting off (turning off) the device power supply of the liquid crystal display device is detected. In such a case, each display pixel is configured through the signal line from the signal side driving means during a predetermined period (afterimage processing period) after the power source is shut off and the drive power is actually shut off from the power source. A first signal voltage having a specific low signal level (for example, a predetermined low level for driving white display or 0 V) is fixedly applied to the pixel electrode without performing inversion driving of the signal polarity. In addition, the second signal having a specific low signal level (low level common signal voltage) from the common signal driving means to the common electrode and being close to the first signal voltage.
Since the signal voltage of is fixedly applied, the display pixels of all lines (between the pixel electrode and the common electrode) that configure the liquid crystal display panel are set in the afterimage processing period set after the device power-off operation. On the other hand, a predetermined voltage (for example, 1 V or 0 V for driving white display) can be written uniformly.

Therefore, the pixel potential (accumulated charge amount) for each scanning line is made uniform, and display unevenness such as a striped pattern is displayed on the display screen immediately after the end of the afterimage processing period (immediately after the drive power is cut off). It is possible to suppress the occurrence. Further, since the signal voltage applied to the common electrode is always fixed to the low level during the afterimage processing period, the discharge operation of the common signal voltage Vcom does not occur at the end of the afterimage processing period. A change (occurrence of an afterimage) can be suppressed, and since a high residual voltage (DC voltage component) is not applied to each display pixel, deterioration of the liquid crystal can be suppressed.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of a liquid crystal display device according to the present invention.

FIG. 2 is a block diagram showing a schematic configuration of a signal driver applied to the liquid crystal display device according to the present embodiment.

FIG. 3 is a circuit configuration diagram showing a configuration example of a sequence control circuit applied to the liquid crystal display device according to the present embodiment.

FIG. 4 is a timing chart showing a drive control operation in the liquid crystal display device according to the present embodiment.

FIG. 5 is a block diagram showing a schematic configuration of a TFT type liquid crystal display device in the related art.

FIG. 6 is a main part circuit diagram showing a circuit configuration of a liquid crystal display panel in a conventional technique.

[Explanation of symbols]

10 Liquid crystal display panel 20A signal driver 30 scan driver 40 RGB decoder 50 inverting amplifier 60 LCD controller 70 Common signal drive amplifier 80 power control circuit 90 Sequence control circuit

─────────────────────────────────────────────────── ─── Continuation of front page (51) Int.Cl. ⁷ Identification code FI theme code (reference) G09G 3/20 670 G09G 3/20 670K F term (reference) 2H093 NA16 NC01 NC13 NC16 NC18 NC23 NC25 NC26 NC34 NC49 NC58 NC59 NC90 ND10 ND12 ND39 ND42 ND47 5C006 AC21 AC25 AF64 AF67 AF68 BB16 BC16 BF38 FA22 FA34 5C080 AA10 BB05 DD05 DD14 DD18 FF11 JJ02 JJ03 JJ04

Claims (8)

[Claims] 1. A switch element connected to the scanning line and the signal line, in the vicinity of each intersection of the plurality of scanning lines and the plurality of signal lines arranged orthogonal to each other,
A liquid crystal display panel having a plurality of display pixels composed of pixel electrodes arranged in a matrix and a common electrode provided so as to face the pixel electrodes, and a scan drive signal is sequentially applied to the plurality of scan lines. A scanning side driving means for scanning the display pixels, a signal side driving means for applying a display signal voltage based on a predetermined video signal to each of the plurality of signal lines, and a predetermined common signal voltage for the common electrode. In a liquid crystal display device comprising a common signal drive means, a power cutoff detection means for detecting that the device power supply of the liquid crystal display device has been cut off, and a cutoff operation of the device power supply is detected by the power cutoff detection means. Display pixel control means for controlling so that a predetermined voltage is fixedly applied between the signal line and the common electrode for a predetermined period. After a while, the liquid crystal display device characterized by comprising a power supply control means for interrupting the supply of driving power to the liquid crystal display device. 2. The display pixel control means at least,
2. The liquid crystal display device according to claim 1, wherein setting control is performed so that a signal voltage having a constant signal level is applied from the signal side driving means to the pixel electrode of the display pixel via the signal line. 3. The liquid crystal display according to claim 2, wherein the display pixel control means performs setting control so that a signal voltage having a constant signal level is applied from the common signal drive means to the common electrode. apparatus. 4. The display pixel control means sets and controls the signal voltage applied to the pixel electrode of the display pixel and the signal voltage applied to the common electrode so as to approximate each other. The liquid crystal display device according to claim 2 or 3. 5. The display pixel control means sets and controls the signal voltage applied to the pixel electrode of the display pixel and the signal voltage applied to the common electrode at specific low signal levels. The liquid crystal display device according to claim 4. 6. The display pixel control means comprises at least:
6. The liquid crystal display device according to claim 5, wherein the signal voltage applied to the pixel electrode of the display pixel is set and controlled to a signal level for driving white display on the liquid crystal display panel. 7. A switch element connected to the scanning line and the signal line, in the vicinity of each intersection of the plurality of scanning lines and the plurality of signal lines arranged orthogonal to each other,
In a display driving method of a liquid crystal display device, which displays desired image information on a liquid crystal display panel having a plurality of display pixels composed of pixel electrodes arranged in a matrix and a common electrode provided so as to face the pixel electrodes. Detecting a device power-off operation in the liquid crystal display device, fixedly applying a first signal voltage having a specific low signal level to each of the plurality of signal lines for a predetermined period, and performing the common operation. A drive control method for an image reading apparatus, characterized in that a second signal voltage that has a specific low signal level and that is close to the first signal voltage is fixedly applied to the electrodes. 8. The first signal voltage is set to a signal level for driving the liquid crystal display panel to display white, and is applied to the pixel electrode without inverting the signal polarity of the signal voltage. 8. The drive control method for a liquid crystal display device according to claim 7, wherein.