JP2005274868A - Liquid crystal display device and driving device for liquid crystal display device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a liquid crystal display device and its driving method that can speedily erase an afterimage on a display screen, and suppress sticking due to a residual voltage and deterioration of liquid crystal in setting the liquid crystal display device in a power-saving state. <P>SOLUTION: In the liquid crystal display device 1 equipped with an active matrix type liquid crystal display panel 10 having display pixels formed nearby intersections of a plurality of scanning lines and a plurality of signal lines crossing each other, a signal driver 80 supplies a display signal voltage corresponding to a luminance signal inputted from an inverting amplifier 50 to the respective signal lines of the liquid crystal display panel 10 when a power-saving control signal Psav has a low level and a voltage Vl having a prescribed low signal level to the respective signal lines of the liquid crystal display panel 10 when the power-saving control signal Psav has a high level. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a liquid crystal display device for driving a liquid crystal display panel in which display pixels are formed in a matrix, and a driving method thereof.

  2. Description of the Related Art Conventionally, a liquid crystal display device including an active matrix liquid crystal display panel in which display pixels are formed in the vicinity of intersections between a plurality of scanning lines and a plurality of signal lines orthogonal to each other is known.

  FIG. 4 is a block diagram showing an example of a schematic configuration of a liquid crystal display device in the prior art, and FIG. 5 is a diagram showing an example of a circuit configuration of a liquid crystal display panel in the prior art. As shown in FIG. 4, the liquid crystal display device 1a includes a liquid crystal display panel 10, an RGB decoder 20, an LCD controller 30, an inverting amplifier 50, a drive amplifier 60, a scan driver 70, and a signal driver 80a. It is prepared for.

  As shown in FIG. 5, the liquid crystal display panel 10 includes a scanning line (gate line) Lg arranged in the row direction, a signal line (source line) Ld arranged in the column direction, each scanning line Lg, and each scanning line Lg. Filled and held between the pixel electrode arranged near the intersection with the signal line Ld, the common electrode arranged opposite to each pixel electrode, to which the common voltage Vcom is applied, and the pixel electrode and the common electrode A liquid crystal capacitor (pixel capacitor) Clc made of liquid crystal, a storage capacitor (auxiliary capacitor) Cs for holding a signal voltage applied to the liquid crystal capacitor Clc, and a predetermined voltage Vcs ( For example, a thin film transistor having a capacitor line Lc to which a common voltage Vcom) is applied, a gate connected to the scan line Lg, a source connected to the signal line Ld, and a drain connected to the liquid crystal capacitor Clc. And TFT, and it is configured to include a, and the electrostatic protection resistor Rcs which is connected between the capacitor wiring Lc (predetermined voltage Vcs) and the signal line Ld.

  The RGB decoder 20 extracts a horizontal synchronization signal H, a vertical synchronization signal V, and a composite synchronization signal CSY from a video signal (composite video signal) supplied from the outside of the liquid crystal display device 1a, and outputs the extracted signal to the LCD controller 30. RGB color signals (RGB signals) included in the video signal are extracted and output to the inverting amplifier 50.

  The LCD controller 30 controls the liquid crystal display panel 10 to display predetermined image information based on the video signal based on the horizontal synchronization signal H, the vertical synchronization signal V, and the composite synchronization signal CSY input from the RGB decoder 20. I do. Specifically, the LCD controller 30 generates a polarity inversion signal FRP and outputs it to the inverting amplifier 50 and the driving amplifier 60, and also outputs a horizontal control signal (signal line output enable signal, clear signal, etc.) and a vertical control signal ( A gate start signal, a gate clock, a gate line output enable signal, etc.), and outputs the generated horizontal control signal to the signal driver 80a and the vertical control signal to the scan driver 70, respectively.

The inversion amplifier 50 receives the polarity inversion signal FRP output from the LCD controller 30 and periodically inverts the polarity of the RGB signal input from the RGB decoder 20 based on the polarity inversion signal FRP, for example, every horizontal scanning period. Thus, an RGB inversion signal (luminance signal) is generated and output to the signal driver 80a.
The drive amplifier 60 receives the polarity inversion signal FRP output from the LCD controller 30, and based on the polarity inversion signal FRP, changes the polarity of the common voltage Vcom applied to the common electrode and the capacitor wiring Lc, for example, every horizontal scanning period. Invert.

The scan driver 70 includes a shift register, a gate circuit, and the like, and sequentially applies a scan signal (gate pulse) to each scan line Lg based on a vertical control signal input from the LCD controller 30.
The signal driver 80a is configured by a shift register, a sample hold circuit, a buffer circuit, and the like, and sequentially samples the luminance signal input from the inverting amplifier 50 based on the horizontal control signal input from the LCD controller 30, and corresponds to the signal driver A display signal voltage is applied simultaneously to each signal line Ld every horizontal scanning period.

  Then, the scanning line Lg and the signal line Ld of the liquid crystal display panel 10 are sequentially selected and driven by the scanning driver 70 and the signal driver 80a, and the display signal voltage applied to each signal line Ld is a thin film transistor of the liquid crystal display panel 10. The voltage is applied to each pixel electrode via the TFT. As a result, the charge due to the potential difference (pixel potential) between the display signal voltage and the common voltage Vcom applied to the common electrode is charged (held) in the liquid crystal capacitance Clc of each display pixel, and the alignment state of the liquid crystal molecules in each display pixel Is controlled, and a video (image) is displayed on the liquid crystal display panel 10.

  By the way, in a conventional liquid crystal display device, for example, in a standby state of an apparatus, or in response to a user operation, only a necessary minimum part is set in an operating state, and a display is set in a non-displaying state. A device having a function of shifting to a power saving state for reducing power is known, and is disclosed in, for example, Patent Document 1 and the like. For example, FIG. 4 shows an example of the configuration of a liquid crystal display device having a power save function in the prior art, and the power save control signal Psav is a signal for setting / releasing the liquid crystal display device 1a to the power save state. For example, the liquid crystal display device 1a is set to a power saving state at a high level and is released from a power saving state at a low level. Specifically, the output state of the buffer circuit constituting the signal driver 80a is controlled based on the state of the power save control signal Psav, and the power save state of the liquid crystal display device 1a is set / released.

FIG. 6 is a diagram illustrating an example of a configuration of a main part of a buffer circuit of a signal driver of a liquid crystal display device having a power saving function in the prior art. Here, the buffer circuit 82a in the signal driver 80a is a part that applies the display signal voltage simultaneously to the signal lines Ld of the liquid crystal display panel 10 for each horizontal scanning period. As shown in FIG. 6, in the signal driver 80a, a power save control signal Psav is applied to the buffer circuit 82a. When the power save control signal Psav is at a low level, the buffer circuit 82a is set in a normal driving state. 82a supplies a display signal voltage corresponding to the luminance signal input from the inverting amplifier 50 to each signal line Ld. Further, when the power save control signal Psav is switched from the low level to the high level, the buffer circuit 82a is set to the high impedance state as the power save state, and the display signal from the signal driver 80a to the signal line Ld. The voltage supply is cut off.
JP 2003-233351 A

By the way, when the liquid crystal display device 1a is set to the power saving state, the supply of the display signal voltage from the signal driver 80a to the signal line Ld is cut off as described above. For this reason, the liquid crystal capacitance Clc of each display pixel is in a state of holding the previous potential at the time of transition to the power saving state. The charge (residual voltage) held in the liquid crystal capacitance Clc of the display pixel is generated via the electrostatic protection resistor Rcs, peripheral wiring (scanning line Lg, signal line Ld, capacitive wiring Lc, etc.), transistor TFT, and the like. The leakage current is gradually discharged, and eventually the electric charge disappears, and the potential of the pixel electrode becomes the same potential as the common voltage Vcom.

  Here, until the residual voltage becomes substantially equal to the common voltage Vcom due to the leakage current (afterimage period), a relatively long time of about several seconds may be required in some cases, and the image gradually disappears. This causes a so-called afterimage, resulting in an unsightly display screen. Furthermore, there is a problem that the residual voltage applied to the liquid crystal capacitance Clc during this period may cause image sticking or deterioration of the liquid crystal.

  Further, when the liquid crystal display device 1a is set to the power saving state, for example, the periodic inversion operation by the drive amplifier 60 of the common voltage Vcom applied to the common electrode and the capacitor wiring Lc is stopped. However, since the voltage level of the common voltage Vcom at the time when the power saving state is set is indefinite, the high level common voltage Vcom is set when the power saving state is set at the timing when the common voltage Vcom becomes high level. It takes a relatively long time to discharge the electric charge to a predetermined low voltage level (for example, ground potential: 0 V) and stabilize it, and the liquid crystal display is applied by the residual voltage applied to each pixel electrode during this time. There was a problem that there was a possibility of deteriorating.

  Accordingly, the present invention provides a liquid crystal display capable of quickly erasing an afterimage on a display screen when setting the liquid crystal display device in a power saving state, and suppressing the occurrence of image sticking and the deterioration of the liquid crystal due to the residual voltage. An object is to provide an apparatus and a driving method thereof.

  In order to solve the above problems, the liquid crystal display device according to the first aspect of the present invention includes a plurality of scanning lines, a plurality of signal lines, and a matrix in the vicinity of each intersection of the plurality of scanning lines and the plurality of signal lines. A liquid crystal display panel having a plurality of pixel electrodes arranged in a row, a common electrode facing each pixel electrode, and a liquid crystal filled between the pixel electrodes and the common electrode, and a predetermined number of the signal lines A liquid crystal display device for driving the liquid crystal display panel by applying a display signal voltage based on the video signal and applying a predetermined common voltage to the common electrode, wherein the liquid crystal display device is set in a power saving state. A power saving control signal input means, and when a power saving control signal is input to the input means, at least a predetermined low signal is supplied to the pixel electrode via the signal line It is characterized in that it comprises a power saving state control means comprises means for controlling to fixedly applying a first signal voltage having a bell, a.

  According to the eighth aspect of the present invention, there is provided a driving method for a liquid crystal display device, which is arranged in a matrix in the vicinity of a plurality of scanning lines and a plurality of signal lines and intersections of the plurality of scanning lines and the plurality of signal lines. A liquid crystal display panel having a plurality of pixel electrodes, a common electrode opposed to each pixel electrode, and a liquid crystal filled between the pixel electrodes and the common electrode, and a predetermined video signal on the plurality of signal lines A liquid crystal display device driving method for driving a liquid crystal display panel by applying a display signal voltage based on the above and applying a predetermined common voltage to the common electrode, wherein the liquid crystal display device is set in a power saving state. In this case, a power save control signal is input to the liquid crystal display device, and the pixel electrode has a predetermined low signal level via the signal line in accordance with the input power save control signal. It is characterized by applying a first signal voltage that fixedly.

  According to the first or eighth aspect of the present invention, when a power save control signal is input to the liquid crystal display device in order to set the liquid crystal display device to the power save state, each pixel electrode is connected via the signal line. The first signal voltage having a predetermined low signal level can be fixedly applied. As a result, the voltage applied to each pixel electrode is fixed to the first signal voltage having a predetermined low signal level at the time of shifting to the power saving state, thereby shortening the time taken to erase the afterimage on the display screen. be able to. Thereby, the occurrence of image sticking due to the residual voltage and the deterioration of the liquid crystal display panel can be suppressed.

  The liquid crystal display device according to claim 2 is the liquid crystal display device according to claim 1, wherein the liquid crystal display device includes signal driving means for applying the display signal voltage to the plurality of signal lines, and the power saving device. The state control means is provided in at least a buffer circuit section that outputs the display signal voltage in the signal driving means to the signal line, and is connected to the power save control signal and the first signal voltage, and the power save control It is characterized by comprising switch means for switching to supply the first signal voltage to the signal line when a signal is inputted.

  According to the second aspect of the present invention, the switch for switching to supply the first signal voltage to the signal line when the power save control signal is inputted to the buffer circuit portion of the signal driving means in the liquid crystal display device. Means can be provided to apply the first signal voltage to the signal line when the power save control signal is input.

  In the liquid crystal display device according to claim 3, in the liquid crystal display device according to claim 1 or 2, the power save state control unit is further configured to input the power save control signal to the input unit. Control means for controlling to apply a second signal voltage having a predetermined low signal level to the common electrode in a fixed manner is provided.

  The liquid crystal display device according to claim 4 is the liquid crystal display device according to claim 3, wherein the liquid crystal display device generates a common voltage and applies the common voltage to the common electrode, and a predetermined period. And a means for controlling the polarity of the common voltage generated by the common electrode driving means in response to a polarity inversion control signal that is controlled to be inverted by the power save state control means. In this case, there is provided means for fixedly setting the polarity inversion control signal to a predetermined low signal level, thereby setting the common voltage to the second signal voltage.

  According to the third or fourth aspect of the present invention, the power saving control signal is provided with the control means for applying the second signal voltage to the common electrode when the power saving control signal is input. In this case, the potential of the common electrode can be set to the second signal voltage.

  The liquid crystal display device according to claim 5 is the liquid crystal display device according to claim 3, wherein the first signal voltage and the second signal voltage have the same potential.

  A liquid crystal display device according to a sixth aspect is the liquid crystal display device according to the third aspect, wherein the first signal voltage and the second signal voltage have a ground potential.

  The liquid crystal display device according to claim 7 is the liquid crystal display device according to claim 3, wherein the first signal voltage and the second signal voltage are the first signal voltage and the second signal voltage. Is a voltage having a value smaller than a threshold voltage of the liquid crystal of the liquid crystal display panel.

  The liquid crystal display device drive method according to claim 10 is the liquid crystal display device drive method according to claim 9, wherein the first signal voltage and the second signal voltage have the same potential. Features.

  The liquid crystal display device driving method according to claim 11 is the liquid crystal display device driving method according to claim 9, wherein the first signal voltage and the second signal voltage have a ground potential. And

  The liquid crystal display device driving method according to claim 12 is the liquid crystal display device driving method according to claim 9, wherein the first signal voltage and the second signal voltage are the first signal voltage and the first signal voltage. The voltage difference between the second signal voltage and the second signal voltage is smaller than a threshold voltage of the liquid crystal of the liquid crystal display panel.

  According to the invention described in any one of claims 5 to 7 or claims 10 to 12, the first signal voltage applied to the signal line and the common electrode when the liquid crystal display device is set in the power saving state. The value of the applied second signal voltage is set to the same potential or the ground potential, or a voltage at which the potential difference between the two voltages is smaller than the threshold voltage of the liquid crystal, thereby shortening the time taken to erase the afterimage on the display screen, Generation of image sticking due to residual voltage and deterioration of the liquid crystal display panel can be suppressed.

  According to the first or fourth aspect of the present invention, when a power save control signal is input to the liquid crystal display device in order to set the liquid crystal display device to the power save state, each pixel electrode is connected via the signal line. The first signal voltage having a predetermined low signal level can be fixedly applied. As a result, the voltage applied to each pixel electrode is fixed to the first signal voltage having a predetermined low signal level at the time of shifting to the power saving state, thereby shortening the time taken to erase the afterimage on the display screen. be able to. Thereby, the occurrence of image sticking due to the residual voltage and the deterioration of the liquid crystal display panel can be suppressed.

According to the second aspect of the present invention, the switch means for switching to supply the first signal voltage to the signal line when the power save control signal is input to the buffer circuit portion of the signal driving means in the liquid crystal display device. The first signal voltage can be applied to the signal line when the power save control signal is input.
According to the third or fourth aspect of the present invention, the power saving control signal is provided by the control means for applying the second signal voltage fixedly to the common electrode when the power saving control signal is input. In this case, the potential of the common electrode can be set to the second signal voltage.

  According to the invention described in any one of claims 5 to 7 or claims 10 to 12, when the liquid crystal display device is set to a power saving state, the first signal voltage applied to the signal line and the common electrode are applied. The second signal voltage value is set to the same potential, the ground potential, or a voltage at which the potential difference between the two voltages is smaller than the threshold voltage of the liquid crystal, thereby shortening the time required to erase the afterimage on the display screen and Generation of image sticking due to voltage and deterioration of the liquid crystal display panel can be suppressed.

  Hereinafter, an embodiment of a liquid crystal display device to which the present invention is applied will be described in detail with reference to FIGS.

  FIG. 1 is a block diagram showing an embodiment of the overall configuration of a display device according to the present invention, and FIG. 2 is a configuration example of a main part of a buffer circuit unit in a signal driver applied to the display device according to the present embodiment. FIG. 3 is a diagram illustrating an example of a circuit configuration of an FRP control circuit applied to the display device according to the present embodiment. In FIG. 1, the same reference numerals are given to components that function in the same way as the liquid crystal display device 1a described with reference to FIG. 4 as the prior art, and the description thereof will be simplified or omitted below. As shown in FIG. 1, the liquid crystal display device 1 according to the present embodiment includes a liquid crystal display panel 10, an RGB decoder 20, an LCD controller 30, an FRP control circuit 40, an inverting amplifier 50, a drive amplifier 60, The scanning driver 70 and the signal driver 80 are provided.

  That is, the signal driver 80 in the liquid crystal display device 1 according to the present embodiment is configured by a shift register, a sample hold circuit, a buffer circuit, a control circuit, and the like, similarly to the signal driver 80a in the prior art shown in FIG. Based on the horizontal control signal input from the LCD controller 30, the luminance signal input from the inverting amplifier 50 is sequentially sampled, and the corresponding display signal voltage is applied to each signal line Ld of the liquid crystal display panel 10 every horizontal scanning period. As shown in FIG. 1, the power save control signal Psav and the voltage Vl are supplied to the buffer circuit unit that applies the display signal voltage to each signal line Ld, and the output state of the buffer circuit is changed. , And a configuration controlled based on the state of the power save control signal Psav. Here, the power save control signal Psav is a signal for setting / releasing the liquid crystal display device 1 to the power save state as in the prior art. For example, the liquid crystal display device 1 is set to the power save state at a high level. However, the power save state is canceled at a low level.

  FIG. 2 is a diagram illustrating a configuration example of a main part of a buffer circuit unit in a signal driver applied to the display device according to the present embodiment. That is, as shown in FIG. 2, the buffer circuit unit of the signal driver 80 in this embodiment is connected to the buffer circuit 82 to which the power save control signal Psav is supplied and the output terminal of the buffer circuit 82 to be connected to the power save control signal. And a control circuit 84 to which Psav is supplied. Here, the buffer circuit 82 is set to a normal driving state when the power save control signal Psav is at a low level, and the display signal corresponding to the luminance signal input from the inverting amplifier 50, as in the conventional technique. Output voltage. Further, when the power save control signal Psav is set to the high level and set to the power save state, the buffer circuit 82 is set to the high impedance state as the power save state, and the signal driver 80 The output of the display signal voltage is cut off.

  On the other hand, the control circuit 84 is ON / OFF controlled by the power save control signal Psav, one end is connected to the output end of the buffer circuit 82, and the other end is a voltage Vl (first signal voltage) having a predetermined low signal level. The switch 84a connected to the is provided. Here, the voltage Vl is set to a constant potential having a ground potential (0 V), for example. When the power save control signal Psav is at a low level, the control circuit 84 sets the switch 84a to the off state, and outputs the display signal voltage output from the buffer circuit 82 as it is, thereby displaying the liquid crystal display. The signal is supplied to each signal line Ld of the panel 10. When the power save control signal Psav is set to the high level and set to the power save state, the switch 84a is controlled to be turned on and connected to the voltage Vl. At this time, the buffer circuit 82 is set to the high level. Since the impedance state is set, the output of the signal driver 80 is fixedly set to the voltage Vl having a predetermined low signal level.

  Thus, when the power save control signal Psav is switched from the low level to the high level, the output of the signal driver 80 is fixedly set to the voltage Vl having a predetermined low signal level, and each signal of the liquid crystal display panel 10 is set. The voltage is supplied to the line Ld, and is fixedly applied to each pixel electrode of the liquid crystal display panel 10 at a voltage Vl (first signal voltage) having a predetermined low signal level.

  Further, in the liquid crystal display device 1 of the present embodiment, as shown in FIG. 1, the FRP control circuit 40 is interposed between the LCD controller 30 and the drive amplifier 60, and the FRP control circuit 40 is generated by the LCD controller 30. The polarity inversion signal FRP and the power save control signal Psav are supplied, and the output polarity inversion signal FRPout is output. The drive amplifier 60 receives the output polarity inversion signal FRPout output from the FRP control circuit 40, and the common voltage Vcom applied to the common electrode and the capacitor wiring of the liquid crystal display panel 10 based on the output polarity inversion signal FRPout. The polarity is controlled to be inverted.

  As shown in FIG. 3, the FRP control circuit 40 is applied with a power save control signal Psav, for example, and outputs an inverted signal of the power save control signal Psav, and an polarity output from the LCD controller 30. An AND circuit 40b that receives the inverted signal FRP and the inverted signal of the power save control signal Psav output from the inverter circuit 40a and outputs the output polarity inverted signal FRPout is provided. The output of the FRP control circuit 40 (output polarity inversion signal FRPout) is controlled based on the state of the power save control signal Psav. Specifically, when the power save control signal Psav is at a low level, the FRP control circuit 40 has a high signal level that is output from the inverter circuit 40a and applied to one input terminal of the AND circuit 40b. The polarity inversion signal FRP output from the LCD controller 30 and applied to the other input terminal of the AND circuit 40b is output as the output polarity inversion signal FRPout and output to the drive amplifier 60. In this case, the output polarity inversion signal FRPout becomes the same signal as the polarity inversion signal FRP, and the normal driving state is obtained.

  On the other hand, when the power save control signal Psav is set to the high level and set to the power save state, the signal level output from the inverter circuit 40a and applied to one input terminal of the AND circuit 40b is the low level. Therefore, the output level of the AND circuit 40b is set to the low level, the output polarity inversion signal FRPout is set to the low level, and the output polarity inversion signal FRPout set to the low level is input to the drive amplifier 60, thereby The common voltage Vcom is set to a constant voltage (low level: second signal voltage) having a predetermined low signal level. Here, the constant voltage set to the common voltage Vcom is set to the ground potential (0 V), for example.

  Thereby, when the power save control signal Psav is switched from the low level to the high level, the signal level of the output polarity inversion signal FRPout output from the FRP control circuit 40 is set to the low level and set to the low level. When the output polarity inversion signal FRPout is input to the drive amplifier 60, the common voltage Vcom supplied to the common electrode of the liquid crystal display panel 10 is fixed to a voltage (second signal voltage) having a predetermined low signal level. Set to

  According to the liquid crystal display device 1 in the present embodiment described above, when the power save control signal Psav is switched to the high level and the liquid crystal display device 1 is set to the power save state, it is applied to each pixel electrode of the liquid crystal display panel 10. Can be fixedly set to a voltage Vl (first signal voltage) having a predetermined low signal level, and the common voltage Vcom supplied to the common electrode of the liquid crystal display panel 10 can be set to a predetermined low voltage. A voltage having a signal level (second signal voltage) is fixedly set. Here, the first signal voltage and the second signal voltage are both set to the ground potential, for example. As a result, the potential difference applied to each liquid crystal capacitance of the liquid crystal display panel 10 consisting of the potential difference between the first signal voltage and the second signal voltage is set to a very small voltage, and the afterimage of the display screen can be quickly displayed. It can be erased, and the application of the residual voltage to each pixel electrode can be suppressed, and the burn-in and the deterioration of the liquid crystal due to the residual voltage can be suppressed.

  In the above-described embodiment, the first signal voltage and the second signal voltage are both set to the ground potential (0 V). However, the present invention is not limited to this, and both are set to the same potential. Anything is acceptable. Furthermore, the potential difference between the first signal voltage and the second signal voltage is not limited to the same potential, but the liquid crystal threshold voltage of the liquid crystal display panel 10 (the transmittance of the liquid crystal display panel 10 is applied to the liquid crystal Clc). The voltage may be smaller than the voltage of about 1 V).

1 is a block diagram illustrating an embodiment of an overall configuration of a display device according to the present invention. It is a figure which shows the principal part structural example of the buffer circuit part in the signal driver applied to the display apparatus concerning this embodiment. It is a figure which shows an example of the circuit structure of the FRP control circuit applied to the display apparatus concerning this embodiment. It is a block diagram which shows an example of schematic structure of the liquid crystal display device in a prior art. It is a figure which shows an example of the circuit structure of the liquid crystal display panel in a prior art. It is a figure which shows an example of a principal part structure of the buffer circuit in the signal driver of the liquid crystal display device in a prior art.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Liquid crystal display device 10 Liquid crystal display panel 20 RGB decoder 30 LCD controller 40 FRP control circuit 50 Inverting amplifier 60 Drive amplifier 70 Scan driver 80 Signal driver

Claims (12)

A plurality of scanning lines and a plurality of signal lines; a plurality of pixel electrodes arranged in a matrix in the vicinity of intersections of the plurality of scanning lines and the plurality of signal lines; a common electrode facing each pixel electrode; A liquid crystal display panel having a pixel electrode and a liquid crystal filled between the common electrodes, applying a display signal voltage based on a predetermined video signal to the plurality of signal lines, and applying a predetermined common voltage to the common electrode. A liquid crystal display device for applying and driving the liquid crystal display panel,
A power save control signal input means for setting the liquid crystal display device in a power save state, and when a power save control signal is input to the input means, at least a predetermined value is applied to the pixel electrode via the signal line. And a means for controlling to apply a first signal voltage having a low signal level in a fixed manner, and a power saving state control means. The liquid crystal display device includes signal driving means for applying the display signal voltage to the plurality of signal lines,
The power save state control means is provided at least in a buffer circuit unit that outputs the display signal voltage in the signal driving means to the signal line, and the power save control signal and the first signal voltage are connected, and 2. The liquid crystal display device according to claim 1, further comprising switch means for switching to supply the first signal voltage to the signal line when a power save control signal is input.   The power save state control means may further apply a second signal voltage having a predetermined low signal level to the common electrode when the power save control signal is input to the input means. The liquid crystal display device according to claim 1, further comprising control means for controlling. The liquid crystal display device generates the common voltage and applies the common electrode to the common electrode, and the common electrode driving means generates the common electrode according to a polarity inversion control signal that is inverted at a predetermined cycle. Means for controlling the polarity of the common voltage,
When the power save control signal is input, the power save state control means fixedly sets the polarity inversion control signal to a predetermined low signal level, whereby the common voltage is set to the second signal voltage. The liquid crystal display device according to claim 3, further comprising a setting unit.   The liquid crystal display device according to claim 3, wherein the first signal voltage and the second signal voltage have the same potential.   The liquid crystal display device according to claim 3, wherein the first signal voltage and the second signal voltage have a ground potential.   The first signal voltage and the second signal voltage are voltages at which a potential difference between the first signal voltage and the second signal voltage is smaller than a threshold voltage of the liquid crystal of the liquid crystal display panel. The liquid crystal display device according to claim 3, wherein the liquid crystal display device is provided. A plurality of scanning lines and a plurality of signal lines; a plurality of pixel electrodes arranged in a matrix in the vicinity of intersections of the plurality of scanning lines and the plurality of signal lines; a common electrode facing each pixel electrode; A liquid crystal display panel having a pixel electrode and a liquid crystal filled between the common electrodes, applying a display signal voltage based on a predetermined video signal to the plurality of signal lines, and applying a predetermined common voltage to the common electrode. A liquid crystal display device driving method for applying and driving the liquid crystal display panel,
When setting the liquid crystal display device to a power save state, a power save control signal is input to the liquid crystal display device,
Driving a liquid crystal display device, wherein a first signal voltage having a predetermined low signal level is fixedly applied to the pixel electrode through the signal line in accordance with the input power save control signal. Method.   9. The method of driving a liquid crystal display device according to claim 8, further comprising applying a second signal voltage having a predetermined signal level to the common electrode in accordance with the input power save control signal.   The method of driving a liquid crystal display device according to claim 9, wherein the first signal voltage and the second signal voltage have the same potential.   10. The method of driving a liquid crystal display device according to claim 9, wherein the first signal voltage and the second signal voltage have a ground potential.   The first signal voltage and the second signal voltage are voltages at which a potential difference between the first signal voltage and the second signal voltage is smaller than a threshold voltage of the liquid crystal of the liquid crystal display panel. The method for driving a liquid crystal display device according to claim 9, wherein:

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