JP2008103028A - 半導体記憶装置 - Google Patents
半導体記憶装置 Download PDFInfo
- Publication number
- JP2008103028A JP2008103028A JP2006285015A JP2006285015A JP2008103028A JP 2008103028 A JP2008103028 A JP 2008103028A JP 2006285015 A JP2006285015 A JP 2006285015A JP 2006285015 A JP2006285015 A JP 2006285015A JP 2008103028 A JP2008103028 A JP 2008103028A
- Authority
- JP
- Japan
- Prior art keywords
- storage node
- voltage
- semiconductor memory
- memory device
- transistor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
Images
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
- G11C11/413—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
- G11C11/417—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction for memory cells of the field-effect type
- G11C11/419—Read-write [R-W] circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
- G11C11/412—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger using field-effect transistors only
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Static Random-Access Memory (AREA)
- Dram (AREA)
Priority Applications (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2006285015A JP2008103028A (ja) | 2006-10-19 | 2006-10-19 | 半導体記憶装置 |
| US11/826,246 US7589991B2 (en) | 2006-10-19 | 2007-07-13 | Semiconductor memory device |
| CNA2007101419953A CN101165806A (zh) | 2006-10-19 | 2007-08-17 | 半导体存储器件 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2006285015A JP2008103028A (ja) | 2006-10-19 | 2006-10-19 | 半導体記憶装置 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JP2008103028A true JP2008103028A (ja) | 2008-05-01 |
| JP2008103028A5 JP2008103028A5 (enExample) | 2009-11-12 |
Family
ID=39317727
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2006285015A Withdrawn JP2008103028A (ja) | 2006-10-19 | 2006-10-19 | 半導体記憶装置 |
Country Status (3)
| Country | Link |
|---|---|
| US (1) | US7589991B2 (enExample) |
| JP (1) | JP2008103028A (enExample) |
| CN (1) | CN101165806A (enExample) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2010245388A (ja) * | 2009-04-08 | 2010-10-28 | Fujitsu Semiconductor Ltd | 半導体メモリおよびシステム |
| JP2014026716A (ja) * | 2013-09-18 | 2014-02-06 | Fujitsu Semiconductor Ltd | 半導体メモリおよびシステム |
| US8665637B2 (en) | 2010-05-21 | 2014-03-04 | Panasonic Corporation | Semiconductor memory |
| JP2018195942A (ja) * | 2017-05-16 | 2018-12-06 | 富士通株式会社 | 記憶回路及び記憶回路の制御方法 |
Families Citing this family (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP4353393B2 (ja) | 2001-06-05 | 2009-10-28 | 株式会社ルネサステクノロジ | 半導体集積回路装置 |
| US7619947B2 (en) * | 2007-10-31 | 2009-11-17 | Texas Instruments Incorporated | Integrated circuit having a supply voltage controller capable of floating a variable supply voltage |
| CN101877243B (zh) * | 2010-04-22 | 2015-09-30 | 上海华虹宏力半导体制造有限公司 | 静态随机存取存储器 |
| CN101819815B (zh) * | 2010-04-29 | 2015-05-20 | 上海华虹宏力半导体制造有限公司 | 一种消除读取干扰的静态随机存储器 |
| US8462542B2 (en) * | 2010-06-24 | 2013-06-11 | Texas Instruments Incorporated | Bit-by-bit write assist for solid-state memory |
| US8305798B2 (en) * | 2010-07-13 | 2012-11-06 | Texas Instruments Incorporated | Memory cell with equalization write assist in solid-state memory |
| CN103137187B (zh) * | 2011-11-28 | 2015-12-09 | 上海华虹宏力半导体制造有限公司 | 一种sram的旁路结构 |
| KR20140092537A (ko) * | 2013-01-16 | 2014-07-24 | 삼성전자주식회사 | 메모리 셀 및 이를 포함하는 메모리 장치 |
| US9928886B2 (en) * | 2016-06-23 | 2018-03-27 | Chih-Cheng Hsiao | Low power memory device |
| KR102755896B1 (ko) * | 2023-04-14 | 2025-01-21 | 서울대학교산학협력단 | 랜덤 액세스 메모리 및 그 제조 방법 |
Family Cites Families (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1202530C (zh) * | 1998-04-01 | 2005-05-18 | 三菱电机株式会社 | 在低电源电压下高速动作的静态型半导体存储装置 |
| JP2001143476A (ja) | 1999-11-15 | 2001-05-25 | Mitsubishi Electric Corp | スタティック型半導体記憶装置 |
| JP2002042476A (ja) | 2000-07-25 | 2002-02-08 | Mitsubishi Electric Corp | スタティック型半導体記憶装置 |
| US6618289B2 (en) | 2001-10-29 | 2003-09-09 | Atmel Corporation | High voltage bit/column latch for Vcc operation |
| US20030190771A1 (en) * | 2002-03-07 | 2003-10-09 | 02Ic, Ltd. | Integrated ram and non-volatile memory cell method and structure |
| JP4162076B2 (ja) | 2002-05-30 | 2008-10-08 | 株式会社ルネサステクノロジ | 半導体記憶装置 |
| JP2004055099A (ja) * | 2002-07-24 | 2004-02-19 | Renesas Technology Corp | 差動増幅回路およびそれを用いた半導体記憶装置 |
| US6992916B2 (en) * | 2003-06-13 | 2006-01-31 | Taiwan Semiconductor Manufacturing Co., Ltd. | SRAM cell design with high resistor CMOS gate structure for soft error rate improvement |
| JP2006012968A (ja) * | 2004-06-23 | 2006-01-12 | Nec Electronics Corp | 半導体集積回路装置及びその設計方法 |
| US7161827B2 (en) * | 2005-01-12 | 2007-01-09 | Freescale Semiconductor, Inc. | SRAM having improved cell stability and method therefor |
| US7164596B1 (en) | 2005-07-28 | 2007-01-16 | Texas Instruments Incorporated | SRAM cell with column select line |
| US7289354B2 (en) * | 2005-07-28 | 2007-10-30 | Texas Instruments Incorporated | Memory array with a delayed wordline boost |
-
2006
- 2006-10-19 JP JP2006285015A patent/JP2008103028A/ja not_active Withdrawn
-
2007
- 2007-07-13 US US11/826,246 patent/US7589991B2/en not_active Expired - Fee Related
- 2007-08-17 CN CNA2007101419953A patent/CN101165806A/zh active Pending
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2010245388A (ja) * | 2009-04-08 | 2010-10-28 | Fujitsu Semiconductor Ltd | 半導体メモリおよびシステム |
| US8665637B2 (en) | 2010-05-21 | 2014-03-04 | Panasonic Corporation | Semiconductor memory |
| JP2014026716A (ja) * | 2013-09-18 | 2014-02-06 | Fujitsu Semiconductor Ltd | 半導体メモリおよびシステム |
| JP2018195942A (ja) * | 2017-05-16 | 2018-12-06 | 富士通株式会社 | 記憶回路及び記憶回路の制御方法 |
Also Published As
| Publication number | Publication date |
|---|---|
| US20080094879A1 (en) | 2008-04-24 |
| US7589991B2 (en) | 2009-09-15 |
| CN101165806A (zh) | 2008-04-23 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20090928 |
|
| A621 | Written request for application examination |
Free format text: JAPANESE INTERMEDIATE CODE: A621 Effective date: 20090928 |
|
| A761 | Written withdrawal of application |
Free format text: JAPANESE INTERMEDIATE CODE: A761 Effective date: 20111020 |