JP2007529894A - ダイ素子が積層された再構成可能なプロセッサモジュール - Google Patents

ダイ素子が積層された再構成可能なプロセッサモジュール Download PDF

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Publication number
JP2007529894A
JP2007529894A JP2007503893A JP2007503893A JP2007529894A JP 2007529894 A JP2007529894 A JP 2007529894A JP 2007503893 A JP2007503893 A JP 2007503893A JP 2007503893 A JP2007503893 A JP 2007503893A JP 2007529894 A JP2007529894 A JP 2007529894A
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integrated circuit
functional element
circuit functional
processor
memory
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JP2007503893A
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JP2007529894A5 (https=
Inventor
ハッペンタール、ジョン、エム
グージー、ジェームス、ディ
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アーバー・カンパニー・リミテッド・ライアビリティ・パートナーシップ
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First worldwide family litigation filed litigation Critical https://patents.darts-ip.com/?family=35064225&utm_source=google_patent&utm_medium=platform_link&utm_campaign=public_patent_search&patent=JP2007529894(A) "Global patent litigation dataset” by Darts-ip is licensed under a Creative Commons Attribution 4.0 International License.
Application filed by アーバー・カンパニー・リミテッド・ライアビリティ・パートナーシップ filed Critical アーバー・カンパニー・リミテッド・ライアビリティ・パートナーシップ
Publication of JP2007529894A publication Critical patent/JP2007529894A/ja
Publication of JP2007529894A5 publication Critical patent/JP2007529894A5/ja
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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/76—Architectures of general purpose stored program computers
    • G06F15/78—Architectures of general purpose stored program computers comprising a single central processing unit
    • G06F15/7867—Architectures of general purpose stored program computers comprising a single central processing unit with reconfigurable architecture
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/20—Interconnections within wafers or substrates, e.g. through-silicon vias [TSV]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/29—Bond pads specially adapted therefor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/59—Bond pads specially adapted therefor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/20—Configurations of stacked chips
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/721—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
    • H10W90/722—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between stacked chips
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/721—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
    • H10W90/724—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between a chip and a stacked insulating package substrate, interposer or RDL
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Stored Programmes (AREA)
JP2007503893A 2004-03-16 2004-12-14 ダイ素子が積層された再構成可能なプロセッサモジュール Pending JP2007529894A (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US10/802,067 US7126214B2 (en) 2001-12-05 2004-03-16 Reconfigurable processor module comprising hybrid stacked integrated circuit die elements
PCT/US2004/041791 WO2005094240A2 (en) 2004-03-16 2004-12-14 Reconfigurable processor module with stacked die elements

Publications (2)

Publication Number Publication Date
JP2007529894A true JP2007529894A (ja) 2007-10-25
JP2007529894A5 JP2007529894A5 (https=) 2008-01-31

Family

ID=35064225

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2007503893A Pending JP2007529894A (ja) 2004-03-16 2004-12-14 ダイ素子が積層された再構成可能なプロセッサモジュール

Country Status (4)

Country Link
US (2) US7126214B2 (https=)
EP (1) EP1726042A4 (https=)
JP (1) JP2007529894A (https=)
WO (1) WO2005094240A2 (https=)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2010080870A (ja) * 2008-09-29 2010-04-08 National Institute Of Advanced Industrial Science & Technology 再構成可能集積回路
JP2013546275A (ja) * 2010-11-17 2013-12-26 ザイリンクス インコーポレイテッド 通信用マルチチップモジュール
JP2015039155A (ja) * 2013-08-19 2015-02-26 富士通株式会社 制御方法、演算装置、および制御プログラム
JP2016529702A (ja) * 2013-07-16 2016-09-23 クゥアルコム・インコーポレイテッドＱｕａｌｃｏｍｍ Ｉｎｃｏｒｐｏｒａｔｅｄ モノリシック３次元（３ｄ）集積回路（ｉｃ）（３ｄｉｃ）技術を使用した完全システムオンチップ（ｓｏｃ）

Families Citing this family (345)

* Cited by examiner, † Cited by third party
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WO2005094240A3 (en) 2006-07-27
US7126214B2 (en) 2006-10-24
US20040177237A1 (en) 2004-09-09
US7282951B2 (en) 2007-10-16

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