JP2007529081A5 - - Google Patents

Download PDF

Info

Publication number
JP2007529081A5
JP2007529081A5 JP2006517820A JP2006517820A JP2007529081A5 JP 2007529081 A5 JP2007529081 A5 JP 2007529081A5 JP 2006517820 A JP2006517820 A JP 2006517820A JP 2006517820 A JP2006517820 A JP 2006517820A JP 2007529081 A5 JP2007529081 A5 JP 2007529081A5
Authority
JP
Japan
Prior art keywords
read
block
write
memory device
transistor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2006517820A
Other languages
English (en)
Japanese (ja)
Other versions
JP2007529081A (ja
Filing date
Publication date
Application filed filed Critical
Priority claimed from PCT/US2004/021162 external-priority patent/WO2005006340A2/en
Publication of JP2007529081A publication Critical patent/JP2007529081A/ja
Publication of JP2007529081A5 publication Critical patent/JP2007529081A5/ja
Pending legal-status Critical Current

Links

JP2006517820A 2003-07-01 2004-06-30 Ｓｒａｍセル構造及び回路 Pending JP2007529081A (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US48456503P 2003-07-01 2003-07-01
PCT/US2004/021162 WO2005006340A2 (en) 2003-07-01 2004-06-30 Sram cell structure and circuits

Publications (2)

Publication Number Publication Date
JP2007529081A JP2007529081A (ja) 2007-10-18
JP2007529081A5 true JP2007529081A5 (https=) 2008-08-21

Family

ID=34062054

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2006517820A Pending JP2007529081A (ja) 2003-07-01 2004-06-30 Ｓｒａｍセル構造及び回路

Country Status (8)

Country Link
US (2) US7102915B2 (https=)
EP (1) EP1642299A4 (https=)
JP (1) JP2007529081A (https=)
KR (1) KR20060040614A (https=)
CN (1) CN1816882A (https=)
CA (1) CA2529667A1 (https=)
TW (1) TWI278862B (https=)
WO (1) WO2005006340A2 (https=)

Families Citing this family (34)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4721776B2 (ja) * 2004-07-13 2011-07-13 ルネサスエレクトロニクス株式会社 半導体記憶装置
US7355905B2 (en) 2005-07-01 2008-04-08 P.A. Semi, Inc. Integrated circuit with separate supply voltage for memory that is different from logic circuit supply voltage
JP4965844B2 (ja) * 2005-10-20 2012-07-04 株式会社東芝 半導体メモリ装置
US7372721B2 (en) * 2005-10-26 2008-05-13 Manoj Sachdev Segmented column virtual ground scheme in a static random access memory (SRAM) circuit
US7411853B2 (en) * 2005-11-17 2008-08-12 Altera Corporation Volatile memory elements with elevated power supply levels for programmable logic device integrated circuits
JP2007172715A (ja) * 2005-12-20 2007-07-05 Fujitsu Ltd 半導体記憶装置およびその制御方法
JP2007199441A (ja) * 2006-01-27 2007-08-09 Hitachi Displays Ltd 画像表示装置
JP2007213699A (ja) * 2006-02-09 2007-08-23 Toshiba Corp 半導体記憶装置
DE102006012187B3 (de) * 2006-03-16 2007-10-11 Infineon Technologies Ag Vorrichtung und Verfahren zur Verringerung des Leckstroms von Speicherzellen im Energiesparmodus
US7898894B2 (en) * 2006-04-12 2011-03-01 International Business Machines Corporation Static random access memory (SRAM) cells
US7440312B2 (en) * 2006-10-02 2008-10-21 Analog Devices, Inc. Memory write timing system
US7925937B2 (en) * 2008-01-07 2011-04-12 Advanced Micro Devices, Inc. Apparatus for testing embedded memory read paths
TWI381380B (zh) * 2008-09-18 2013-01-01 Aicestar Technology Suzhou Corp 靜態隨機存取記憶體及其形成與控制方法
TWI419160B (zh) * 2009-01-07 2013-12-11 Univ Nat Chiao Tung 靜態隨機存取記憶體裝置
US9875788B2 (en) * 2010-03-25 2018-01-23 Qualcomm Incorporated Low-power 5T SRAM with improved stability and reduced bitcell size
US8797787B2 (en) * 2011-11-10 2014-08-05 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor manufacturing method
US9171634B2 (en) * 2013-03-14 2015-10-27 Arm Limited Memory device and method of controlling leakage current within such a memory device
US9208853B2 (en) * 2013-03-15 2015-12-08 Intel Corporation Dual-port static random access memory (SRAM)
KR102072407B1 (ko) 2013-05-03 2020-02-03 삼성전자 주식회사 메모리 장치 및 그 구동 방법
KR20150102526A (ko) 2014-02-28 2015-09-07 에스케이하이닉스 주식회사 전자 장치
KR20160050534A (ko) * 2014-10-30 2016-05-11 에스케이하이닉스 주식회사 누설 전류 감지부를 구비하는 반도체 집적 회로 장치 및 그 구동방법
US10163490B2 (en) * 2015-02-23 2018-12-25 Qualcomm Incorporated P-type field-effect transistor (PFET)-based sense amplifiers for reading PFET pass-gate memory bit cells, and related memory systems and methods
US10037400B2 (en) * 2016-06-02 2018-07-31 Marvell World Trade Ltd. Integrated circuit manufacturing process for aligning threshold voltages of transistors
US10062431B2 (en) 2016-11-07 2018-08-28 Ambiq Micro, Inc. SRAM with multiple power domains
US11094685B2 (en) 2016-11-29 2021-08-17 Taiwan Semiconductor Manufacturing Co., Ltd. Static random access memory device
US10148254B2 (en) * 2017-01-13 2018-12-04 Flashsilicon Incorporation Standby current reduction in digital circuitries
CN108062963A (zh) * 2017-11-23 2018-05-22 上海华力微电子有限公司 Sram读辅助电路
US10672775B2 (en) * 2018-05-25 2020-06-02 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device having strap cell
US12176025B2 (en) 2021-07-09 2024-12-24 Stmicroelectronics International N.V. Adaptive body bias management for an in-memory compute operation where simultaneous access is made to plural rows of a static random access memory (SRAM)
US11984151B2 (en) 2021-07-09 2024-05-14 Stmicroelectronics International N.V. Adaptive bit line overdrive control for an in-memory compute operation where simultaneous access is made to plural rows of a static random access memory (SRAM)
US12237007B2 (en) 2021-07-09 2025-02-25 Stmicroelectronics International N.V. Selective bit line clamping control for an in-memory compute operation where simultaneous access is made to plural rows of a static random access memory (SRAM)
US12087356B2 (en) 2021-07-09 2024-09-10 Stmicroelectronics International N.V. Serial word line actuation with linked source voltage supply modulation for an in-memory compute operation where simultaneous access is made to plural rows of a static random access memory (SRAM)
US12354644B2 (en) 2021-07-09 2025-07-08 Stmicroelectronics International N.V. Adaptive word line underdrive control for an in-memory compute operation where simultaneous access is made to plural rows of a static random access memory (SRAM)
CN114999547B (zh) * 2022-05-17 2026-03-20 长江存储科技有限责任公司 存储器装置及其操作方法、存储器系统

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR0184638B1 (ko) 1989-02-23 1999-04-15 엔.라이스 머레트 세그먼트 비트 라인 스태틱 랜덤 액세스 메모리 구조물
US5070482A (en) * 1989-04-06 1991-12-03 Sony Corporation Static random access memory
KR100392687B1 (ko) 1995-10-31 2003-11-28 마츠시타 덴끼 산교 가부시키가이샤 반도체 기억장치
US6091627A (en) * 1998-09-16 2000-07-18 Lucent Technologies, Inc. Message box memory cell for two-side asynchronous access
US6181608B1 (en) 1999-03-03 2001-01-30 Intel Corporation Dual Vt SRAM cell with bitline leakage control
US6661733B1 (en) * 2000-06-15 2003-12-09 Altera Corporation Dual-port SRAM in a programmable logic device
US6519204B2 (en) 2000-11-03 2003-02-11 Broadcom Corporation Very small swing high performance CMOS static memory (multi-port register file) with power reducing column multiplexing scheme
JP3983032B2 (ja) 2001-11-09 2007-09-26 沖電気工業株式会社 半導体記憶装置
KR100964266B1 (ko) * 2002-03-27 2010-06-16 더 리전트 오브 더 유니버시티 오브 캘리포니아 저전력 고성능의 메모리셀 및 관련방법
JP4278338B2 (ja) * 2002-04-01 2009-06-10 株式会社ルネサステクノロジ 半導体記憶装置
US6873565B1 (en) * 2003-10-10 2005-03-29 Hewlett-Packard Development Company, L.P. Dual-ported read SRAM cell with improved soft error immunity
US7009871B1 (en) * 2004-08-18 2006-03-07 Kabushiki Kaisha Toshiba Stable memory cell

Similar Documents

Publication Publication Date Title
JP2007529081A5 (https=)
JP5067650B2 (ja) 半導体記憶装置
EP2482285B1 (en) SRAM cell with improved read stability
US7639549B2 (en) Very small swing high performance asynchronous CMOS static memory (multi-port register file) with power reducing column multiplexing scheme
TWI485705B (zh) 具備列式讀取及／或寫入輔助電路之記憶體電路
JP5197651B2 (ja) センス増幅器回路、およびセンス増幅器回路を有するメモリ
US20120140552A1 (en) Write assist static random access memory cell
US7447088B2 (en) Semiconductor memory device having an open bit line structure, and method of testing the same
CN101740116A (zh) 8晶体管型低漏电静态随机存取内存单元
JP2007193928A (ja) 半導体記憶装置
US20050232058A1 (en) Semiconductor integrated circuit device having static random access memory mounted thereon
US7898894B2 (en) Static random access memory (SRAM) cells
US8588004B2 (en) Memory device having multi-port memory cell with expandable port configuration
US9947392B1 (en) Memory device sensing circuit
US7336553B2 (en) Enhanced sensing in a hierarchical memory architecture
US20080175083A1 (en) Memory cell access circuit
US8284591B2 (en) Semiconductor memory device and test method therefor
JP5590510B2 (ja) 半導体記憶装置
US8830782B2 (en) Memory circuits having a plurality of keepers
Ney et al. Analysis of resistive-open defects in SRAM sense amplifiers
KR100893581B1 (ko) 계층적 비트라인 구조를 갖는 메모리 장치
Barekar et al. On-chip weak resistive defect diagnosis with performance enhancement in 45 nm technology static random access memory
Jagadale et al. Performance comparison of SRAM cells in 45NM technology in the presence of a memory cell control circuit
KR20150122366A (ko) 반도체 메모리 장치
JP2011187126A (ja) 記憶回路