JP2007526652A5 - - Google Patents
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- Publication number
- JP2007526652A5 JP2007526652A5 JP2007501861A JP2007501861A JP2007526652A5 JP 2007526652 A5 JP2007526652 A5 JP 2007526652A5 JP 2007501861 A JP2007501861 A JP 2007501861A JP 2007501861 A JP2007501861 A JP 2007501861A JP 2007526652 A5 JP2007526652 A5 JP 2007526652A5
- Authority
- JP
- Japan
- Prior art keywords
- nitride
- forming
- stop layer
- layer
- semiconductor substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- TWXTWZIUMCFMSG-UHFFFAOYSA-N nitride(3-) Chemical compound [N-3] TWXTWZIUMCFMSG-UHFFFAOYSA-N 0.000 claims 16
- 238000005498 polishing Methods 0.000 claims 14
- 239000004065 semiconductor Substances 0.000 claims 9
- 239000000758 substrate Substances 0.000 claims 9
- 239000011810 insulating material Substances 0.000 claims 6
- 241001270131 Agaricus moelleri Species 0.000 claims 3
- 238000002955 isolation Methods 0.000 claims 3
- 238000005530 etching Methods 0.000 claims 2
- 238000004519 manufacturing process Methods 0.000 claims 2
- 239000012535 impurity Substances 0.000 claims 1
- 150000002500 ions Chemical class 0.000 claims 1
Claims (7)
- 半導体基板上に、４００Å以下の厚さで、窒化物研磨停止層を形成し、
前記窒化物研磨停止層中に開口部を形成すると共に、前記基板中にトレンチを形成し、
前記窒化物研磨停止層上に表土を形成する絶縁材料でトレンチを充てんし、
平坦な上面を形成すべく、前記窒化物研磨停止層上で停止するように研磨し、これにより、シャロートレンチ分離領域を形成し、
前記シャロートレンチ分離領域に隣接する前記半導体基板中のソース／ドレイン領域に不純物領域を形成するように、前記窒化物研磨停止層を貫通してイオンを注入する、半導体デバイスを製造する方法。 - ５０Åから１５０Åの厚さで、前記窒化物研磨停止層を形成する、請求項１記載の方法。
- 前記窒化物研磨停止層の２０Åのみを除去するとともに、前記平坦な上面を形成するように研磨する、請求項１記載の方法。
- 前記半導体基板の上面上にパッド酸化物層を形成し、
前記パッド酸化物層上に前記窒化物研磨停止層を形成する、請求項１記載の方法。 - さらに、前記窒化物研磨停止層を除去し、
前記窒化物研磨停止層を除去した後、前記半導体基板上にゲート酸化層を形成し、
前記ゲート酸化層上にゲート電極を形成する、請求項１記載の方法。 - さらに、前記窒化物研磨停止層を除去する前に、前記絶縁材料の上面が前記半導体基板の上面と実質的に同一平面となるように、前記トレンチを充てんする前記絶縁材料の上面の一部を除去するエッチングを行う、請求項５記載の方法。
- 半導体基板上に、４００Å以下の厚さで、窒化物研磨停止層を形成し、
前記窒化物研磨停止層中に開口部を形成すると共に、前記基板中にトレンチを形成し、
前記窒化物研磨停止層上に表土を形成する絶縁材料でトレンチを充てんし、
平坦な上面を形成すべく、前記窒化物研磨停止層上で停止するように研磨し、これにより、シャロートレンチ分離領域を形成し、その後、
前記絶縁材料の上面が前記半導体基板の上面と実質的に同一平面となるように、前記トレンチを充てんする前記絶縁材料の上面の一部を除去するエッチングを行い、その後、
前記窒化物研磨停止層を除去する、
半導体デバイスを製造する方法
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US10/791,759 US7091106B2 (en) | 2004-03-04 | 2004-03-04 | Method of reducing STI divot formation during semiconductor device fabrication |
| PCT/US2005/006177 WO2005093825A1 (en) | 2004-03-04 | 2005-02-26 | Method of reducing sti divot formation during semiconductor device fabrication |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JP2007526652A JP2007526652A (ja) | 2007-09-13 |
| JP2007526652A5 true JP2007526652A5 (ja) | 2009-11-26 |
Family
ID=34911706
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2007501861A Pending JP2007526652A (ja) | 2004-03-04 | 2005-02-26 | 半導体デバイス製造の間のｓｔｉディボット形成を減少する方法 |
Country Status (8)
| Country | Link |
|---|---|
| US (1) | US7091106B2 (ja) |
| JP (1) | JP2007526652A (ja) |
| KR (1) | KR20060129037A (ja) |
| CN (1) | CN1926679B (ja) |
| DE (1) | DE112005000512B4 (ja) |
| GB (1) | GB2426126B (ja) |
| TW (1) | TWI355678B (ja) |
| WO (1) | WO2005093825A1 (ja) |
Families Citing this family (20)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100568259B1 (ko) * | 2004-12-14 | 2006-04-07 | 삼성전자주식회사 | 트렌치 소자 분리형 반도체 장치 및 그 형성 방법 |
| US20080204580A1 (en) * | 2007-02-28 | 2008-08-28 | Micron Technology, Inc. | Method, apparatus and system providing imaging device with color filter array |
| US20090053834A1 (en) * | 2007-08-23 | 2009-02-26 | Vladimir Alexeevich Ukraintsev | Use of scatterometry for in-line detection of poly-si strings left in sti divot after gate etch |
| KR100880227B1 (ko) * | 2007-10-09 | 2009-01-28 | 주식회사 동부하이텍 | 플래시 메모리 소자의 제조방법 |
| US7745320B2 (en) * | 2008-05-21 | 2010-06-29 | Chartered Semiconductor Manufacturing, Ltd. | Method for reducing silicide defects in integrated circuits |
| WO2010125428A1 (en) * | 2009-04-30 | 2010-11-04 | X-Fab Semiconductor Foundries Ag | Manufacturing integrated circuit components having multiple gate oxidations |
| US8274114B2 (en) * | 2010-01-14 | 2012-09-25 | Broadcom Corporation | Semiconductor device having a modified shallow trench isolation (STI) region and a modified well region |
| US8283722B2 (en) | 2010-06-14 | 2012-10-09 | Broadcom Corporation | Semiconductor device having an enhanced well region |
| US9123807B2 (en) | 2010-12-28 | 2015-09-01 | Broadcom Corporation | Reduction of parasitic capacitance in a semiconductor device |
| US20120292735A1 (en) | 2011-05-20 | 2012-11-22 | GLOBALFOUNDRIES Singapore Pte.Ltd. | Corner transistor suppression |
| US9263556B2 (en) * | 2012-06-29 | 2016-02-16 | Taiwan Semiconductor Manufacturing Company, Ltd. | Silicide process using OD spacers |
| US8716102B2 (en) * | 2012-08-14 | 2014-05-06 | Globalfoundries Inc. | Methods of forming isolation structures for semiconductor devices by performing a dry chemical removal process |
| US8603895B1 (en) | 2012-09-11 | 2013-12-10 | Globalfoundries Inc. | Methods of forming isolation structures for semiconductor devices by performing a deposition-etch-deposition sequence |
| US9219059B2 (en) | 2012-09-26 | 2015-12-22 | International Business Machines Corporation | Semiconductor structure with integrated passive structures |
| JP6591347B2 (ja) | 2016-06-03 | 2019-10-16 | ルネサスエレクトロニクス株式会社 | 半導体装置の製造方法 |
| JP6629159B2 (ja) | 2016-09-16 | 2020-01-15 | ルネサスエレクトロニクス株式会社 | 半導体装置の製造方法 |
| CN111341724B (zh) * | 2018-12-19 | 2022-11-04 | 上海新微技术研发中心有限公司 | 浅沟槽隔离工艺及浅沟槽隔离结构 |
| KR20200145974A (ko) * | 2019-06-21 | 2020-12-31 | 삼성전자주식회사 | 반도체 소자 및 그 제조 방법 |
| US12002707B2 (en) | 2020-08-06 | 2024-06-04 | Changxin Memory Technologies, Inc. | Semiconductor structure and manufacturing method thereof |
| CN113611604A (zh) * | 2021-03-19 | 2021-11-05 | 联芯集成电路制造(厦门)有限公司 | 半导体元件的制作方法 |
Family Cites Families (20)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US98661A (en) * | 1870-01-11 | Ikank l | ||
| US5177028A (en) | 1991-10-22 | 1993-01-05 | Micron Technology, Inc. | Trench isolation method having a double polysilicon gate formed on mesas |
| US5234535A (en) * | 1992-12-10 | 1993-08-10 | International Business Machines Corporation | Method of producing a thin silicon-on-insulator layer |
| US5665633A (en) * | 1995-04-06 | 1997-09-09 | Motorola, Inc. | Process for forming a semiconductor device having field isolation |
| US5616513A (en) * | 1995-06-01 | 1997-04-01 | International Business Machines Corporation | Shallow trench isolation with self aligned PSG layer |
| JPH098135A (ja) * | 1995-06-26 | 1997-01-10 | Toshiba Corp | 半導体装置の製造方法 |
| JP3125719B2 (ja) * | 1997-07-28 | 2001-01-22 | 日本電気株式会社 | 半導体装置及びその製造方法 |
| JP3053009B2 (ja) * | 1997-09-29 | 2000-06-19 | 日本電気株式会社 | 半導体装置の製造方法 |
| US6555476B1 (en) | 1997-12-23 | 2003-04-29 | Texas Instruments Incorporated | Silicon carbide as a stop layer in chemical mechanical polishing for isolation dielectric |
| CN1219328C (zh) * | 1998-02-19 | 2005-09-14 | 国际商业机器公司 | 具有改善了注入剂的场效应晶体管及其制造方法 |
| JP3178416B2 (ja) * | 1998-05-22 | 2001-06-18 | 日本電気株式会社 | 半導体装置の製造方法 |
| US6599810B1 (en) * | 1998-11-05 | 2003-07-29 | Advanced Micro Devices, Inc. | Shallow trench isolation formation with ion implantation |
| US6248641B1 (en) * | 1999-02-05 | 2001-06-19 | United Microelectronics Corp. | Method of fabricating shallow trench isolation |
| JP2001185731A (ja) * | 1999-12-24 | 2001-07-06 | Toshiba Corp | 半導体装置及びその製造方法 |
| KR100346842B1 (ko) * | 2000-12-01 | 2002-08-03 | 삼성전자 주식회사 | 얕은 트렌치 아이솔레이션 구조를 갖는 반도체 디바이스및 그 제조방법 |
| US6432797B1 (en) | 2001-01-25 | 2002-08-13 | Chartered Semiconductor Manufacturing Ltd. | Simplified method to reduce or eliminate STI oxide divots |
| US20020142531A1 (en) * | 2001-03-29 | 2002-10-03 | Hsu Sheng Teng | Dual damascene copper gate and interconnect therefore |
| US6673695B1 (en) | 2002-02-01 | 2004-01-06 | Chartered Semiconductor Manufacturing Ltd. | STI scheme to prevent fox recess during pre-CMP HF dip |
| JP4318892B2 (ja) * | 2002-05-30 | 2009-08-26 | 富士通マイクロエレクトロニクス株式会社 | 電子装置の設計方法および製造方法 |
| US6566215B1 (en) * | 2002-06-06 | 2003-05-20 | Chartered Semiconductor Manufacturing Ltd. | Method of fabricating short channel MOS transistors with source/drain extensions |
-
2004
- 2004-03-04 US US10/791,759 patent/US7091106B2/en not_active Expired - Lifetime
-
2005
- 2005-02-26 DE DE112005000512T patent/DE112005000512B4/de not_active Expired - Fee Related
- 2005-02-26 KR KR1020067017589A patent/KR20060129037A/ko not_active Application Discontinuation
- 2005-02-26 GB GB0617207A patent/GB2426126B/en not_active Expired - Fee Related
- 2005-02-26 WO PCT/US2005/006177 patent/WO2005093825A1/en active Application Filing
- 2005-02-26 CN CN2005800068145A patent/CN1926679B/zh not_active Expired - Fee Related
- 2005-02-26 JP JP2007501861A patent/JP2007526652A/ja active Pending
- 2005-03-02 TW TW094106204A patent/TWI355678B/zh not_active IP Right Cessation
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