JP2007520081A - 導電性機構を有する部分的にエッチングされた誘電体膜 - Google Patents

導電性機構を有する部分的にエッチングされた誘電体膜 Download PDF

Info

Publication number
JP2007520081A
JP2007520081A JP2006551177A JP2006551177A JP2007520081A JP 2007520081 A JP2007520081 A JP 2007520081A JP 2006551177 A JP2006551177 A JP 2006551177A JP 2006551177 A JP2006551177 A JP 2006551177A JP 2007520081 A JP2007520081 A JP 2007520081A
Authority
JP
Japan
Prior art keywords
dielectric film
metal
conductive
dielectric
array
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
JP2006551177A
Other languages
English (en)
Japanese (ja)
Other versions
JP2007520081A5 (https=
Inventor
デニス・エム・ブルナー
デイビッド・エル・バスター
マイケル・エス・グラフ
ダニエル・ケイ・ルーバート
ネイサン・ピー・クルーター
ルイ・ヤン
グオピン・マオ
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
3M Innovative Properties Co
Original Assignee
3M Innovative Properties Co
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 3M Innovative Properties Co filed Critical 3M Innovative Properties Co
Publication of JP2007520081A publication Critical patent/JP2007520081A/ja
Publication of JP2007520081A5 publication Critical patent/JP2007520081A5/ja
Withdrawn legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/4007—Surface contacts, e.g. bumps
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/01—Manufacture or treatment
    • H10W70/05—Manufacture or treatment of insulating or insulated package substrates, or of interposers, or of redistribution layers
    • H10W70/093—Connecting or disconnecting other interconnections thereto or therefrom, e.g. connecting bond wires or bumps
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/01—Manufacture or treatment
    • H10W70/05—Manufacture or treatment of insulating or insulated package substrates, or of interposers, or of redistribution layers
    • H10W70/095—Manufacture or treatment of insulating or insulated package substrates, or of interposers, or of redistribution layers of vias therein
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/67—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their insulating layers or insulating parts
    • H10W70/688—Flexible insulating substrates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/03—Conductive materials
    • H05K2201/0332—Structure of the conductor
    • H05K2201/0364—Conductor shape
    • H05K2201/0367—Metallic bump or raised conductor not used as solder bump
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/03—Conductive materials
    • H05K2201/0332—Structure of the conductor
    • H05K2201/0388—Other aspects of conductors
    • H05K2201/0394—Conductor crossing over a hole in the substrate or a gap between two separate substrate parts
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09009—Substrate related
    • H05K2201/09036—Recesses or grooves in insulating substrate
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/095—Conductive through-holes or vias
    • H05K2201/09563—Metal filled via
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09818—Shape or layout details not covered by a single group of H05K2201/09009 - H05K2201/09809
    • H05K2201/09827—Tapered, e.g. tapered hole, via or groove
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/03—Metal processing
    • H05K2203/0369—Etching selective parts of a metal substrate through part of its thickness, e.g. using etch resist
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/0011—Working of insulating substrates or insulating layers
    • H05K3/0017—Etching of the substrate by chemical or physical means
    • H05K3/002—Etching of the substrate by chemical or physical means by liquid chemical etching
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/251—Materials

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)
  • Wire Bonding (AREA)
JP2006551177A 2004-01-29 2005-01-13 導電性機構を有する部分的にエッチングされた誘電体膜 Withdrawn JP2007520081A (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US53995904P 2004-01-29 2004-01-29
PCT/US2005/001341 WO2005074339A1 (en) 2004-01-29 2005-01-13 Partially etched dielectric film with conductive features

Publications (2)

Publication Number Publication Date
JP2007520081A true JP2007520081A (ja) 2007-07-19
JP2007520081A5 JP2007520081A5 (https=) 2008-03-06

Family

ID=34826156

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2006551177A Withdrawn JP2007520081A (ja) 2004-01-29 2005-01-13 導電性機構を有する部分的にエッチングされた誘電体膜

Country Status (7)

Country Link
US (2) US7012017B2 (https=)
EP (1) EP1709848A1 (https=)
JP (1) JP2007520081A (https=)
KR (1) KR20060124730A (https=)
CN (1) CN1930928A (https=)
CA (1) CA2554750A1 (https=)
WO (1) WO2005074339A1 (https=)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110942914A (zh) * 2014-06-11 2020-03-31 阿维科斯公司 低噪电容器
JP2020533419A (ja) * 2017-09-11 2020-11-19 フジフイルム エレクトロニック マテリアルズ ユー．エス．エー．， インコーポレイテッド 誘電フィルム形成用組成物

Families Citing this family (28)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4628154B2 (ja) * 2005-03-22 2011-02-09 三井金属鉱業株式会社 フレキシブルプリント配線基板、および半導体装置
US8553364B1 (en) 2005-09-09 2013-10-08 Magnecomp Corporation Low impedance, high bandwidth disk drive suspension circuit
US7829793B2 (en) * 2005-09-09 2010-11-09 Magnecomp Corporation Additive disk drive suspension manufacturing using tie layers for vias and product thereof
US7781679B1 (en) * 2005-09-09 2010-08-24 Magnecomp Corporation Disk drive suspension via formation using a tie layer and product
US8395866B1 (en) 2005-09-09 2013-03-12 Magnecomp Corporation Resilient flying lead and terminus for disk drive suspension
US8764664B2 (en) 2005-11-28 2014-07-01 Vizyontech Imaging, Inc. Methods and apparatus for conformable medical data acquisition pad and configurable imaging system
US20080044623A1 (en) * 2006-08-21 2008-02-21 John Caldwell Probe card for testing imaging devices, and methods of fabricating same
KR100752672B1 (ko) * 2006-09-06 2007-08-29 삼성전자주식회사 신뢰성 있는 범프 접속 구조를 갖는 인쇄 회로 기판 및 그제조방법, 및 이를 이용한 반도체 패키지
US7633035B2 (en) * 2006-10-05 2009-12-15 Mu-Gahat Holdings Inc. Reverse side film laser circuit etching
US20080083706A1 (en) * 2006-10-05 2008-04-10 Mu-Gahat Enterprises, Llc Reverse side film laser circuit etching
US7813082B2 (en) * 2007-01-26 2010-10-12 Hutchinson Technology Incorporated Head suspension flexure with inline lead portions positioned at a level between levels of first and second surfaces of the spring metal layer
US7835112B2 (en) 2007-02-12 2010-11-16 Hutchinson Technology Incorporated Integrated lead flexure with embedded traces
FR2914304B1 (fr) 2007-03-28 2012-11-16 Guerbet Sa Composes pour le diagnostic de maladies liees a l'expression de vcam.
US20080237882A1 (en) * 2007-03-30 2008-10-02 Islam Salama Annular via drilling (AVD) technology
US20090061251A1 (en) * 2007-08-27 2009-03-05 Mu-Gahat Enterprises, Llc Laser circuit etching by additive deposition
US20090061112A1 (en) * 2007-08-27 2009-03-05 Mu-Gahat Enterprises, Llc Laser circuit etching by subtractive deposition
JP5080687B2 (ja) 2009-04-07 2012-11-21 パナソニック株式会社 センサチップとこれを用いる測定器及び血液検査装置
KR20130143067A (ko) 2010-11-03 2013-12-30 쓰리엠 이노베이티브 프로퍼티즈 컴파니 가요성 led 디바이스 및 제조 방법
KR20130141559A (ko) 2010-11-03 2013-12-26 쓰리엠 이노베이티브 프로퍼티즈 컴파니 열 관리를 위한 가요성 ｌｅｄ 디바이스 및 제조 방법
CA2719927C (en) 2010-11-05 2014-04-29 Ibm Canada Limited - Ibm Canada Limitee Laser ashing of polyimide for semiconductor manufacturing
JP2017509159A (ja) 2014-03-25 2017-03-30 スリーエム イノベイティブ プロパティズ カンパニー 同一平面導電性構造体を有するフレキシブル回路及びその製作方法
FR3030112B1 (fr) * 2014-12-12 2018-02-02 Stmicroelectronics (Crolles 2) Sas Assemblage d'une puce de circuits integres et d'une plaque
US20180084635A1 (en) * 2015-03-20 2018-03-22 3M Innovative Properties Company Multilayer substrate for a light emitting semi-conductor device package
KR102414392B1 (ko) 2016-06-23 2022-06-30 쓰리엠 이노베이티브 프로퍼티즈 컴파니 열전 테이프
WO2017222862A1 (en) 2016-06-23 2017-12-28 3M Innovative Properties Company Flexible thermoelectric module
KR102047736B1 (ko) 2016-06-23 2019-11-25 쓰리엠 이노베이티브 프로퍼티즈 컴파니 가요성 열전 모듈
US11018024B2 (en) * 2018-08-02 2021-05-25 Nxp Usa, Inc. Method of fabricating embedded traces
KR102882272B1 (ko) * 2022-04-29 2025-11-06 주식회사 아모그린텍 세라믹 기판 제조방법

Family Cites Families (35)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5134460A (en) * 1986-08-11 1992-07-28 International Business Machines Corporation Aluminum bump, reworkable bump, and titanium nitride structure for tab bonding
US5248446A (en) * 1988-08-26 1993-09-28 Idemitsu Kosan Co., Ltd. Liquid-crystalline copolymer
EP0388312A3 (en) 1989-03-17 1991-04-24 Furukawa Denki Kogyo Kabushiki Kaisha Chip carrier with improved flexing characteristic
US5208066A (en) * 1989-03-18 1993-05-04 Hitachi, Ltd. Process of forming a patterned polyimide film and articles including such a film
JP3245437B2 (ja) 1991-04-05 2002-01-15 株式会社クラレ 積層体の製造方法
US5227008A (en) * 1992-01-23 1993-07-13 Minnesota Mining And Manufacturing Company Method for making flexible circuits
US5401913A (en) * 1993-06-08 1995-03-28 Minnesota Mining And Manufacturing Company Electrical interconnections between adjacent circuit board layers of a multi-layer circuit board
JP2939477B2 (ja) 1994-08-16 1999-08-25 エイチエヌエイ・ホールディングス・インコーポレーテッド 液晶重合体−金属積層品および該積層品の製造法
US5747358A (en) * 1996-05-29 1998-05-05 W. L. Gore & Associates, Inc. Method of forming raised metallic contacts on electrical circuits
US6085414A (en) * 1996-08-15 2000-07-11 Packard Hughes Interconnect Company Method of making a flexible circuit with raised features protruding from two surfaces and products therefrom
JPH1064956A (ja) * 1996-08-20 1998-03-06 Fujitsu Ltd フェースダウンボンディング半導体装置
US6882030B2 (en) * 1996-10-29 2005-04-19 Tru-Si Technologies, Inc. Integrated circuit structures with a conductor formed in a through hole in a semiconductor substrate and protruding from a surface of the substrate
EP0902048B1 (en) * 1997-09-11 2005-11-23 E.I. Du Pont De Nemours And Company High dielectric constant flexible polyimide film and process of preparation
US6313402B1 (en) * 1997-10-29 2001-11-06 Packard Hughes Interconnect Company Stress relief bend useful in an integrated circuit redistribution patch
JP3080047B2 (ja) * 1997-11-07 2000-08-21 日本電気株式会社 バンプ構造体及びバンプ構造体形成方法
US6222136B1 (en) * 1997-11-12 2001-04-24 International Business Machines Corporation Printed circuit board with continuous connective bumps
US6077560A (en) * 1997-12-29 2000-06-20 3M Innovative Properties Company Method for continuous and maskless patterning of structured substrates
JP2000106482A (ja) * 1998-07-29 2000-04-11 Sony Chem Corp フレキシブル基板製造方法
JP3502776B2 (ja) 1998-11-26 2004-03-02 新光電気工業株式会社 バンプ付き金属箔及び回路基板及びこれを用いた半導体装置
US6537854B1 (en) * 1999-05-24 2003-03-25 Industrial Technology Research Institute Method for bonding IC chips having multi-layered bumps with corrugated surfaces and devices formed
US6322903B1 (en) * 1999-12-06 2001-11-27 Tru-Si Technologies, Inc. Package of integrated circuits and vertical integration
US7087181B2 (en) 2000-01-31 2006-08-08 Diagnoswiss S.A. Method for fabricating micro-structures with various surface properties in multi-layer body by plasma etching
US6555908B1 (en) * 2000-02-10 2003-04-29 Epic Technologies, Inc. Compliant, solderable input/output bump structures
WO2002003767A1 (en) 2000-06-29 2002-01-10 3M Innovative Properties Company Multi-metal layer circuit
US6403211B1 (en) * 2000-07-18 2002-06-11 3M Innovative Properties Company Liquid crystal polymer for flexible circuits
US6923919B2 (en) * 2000-07-18 2005-08-02 3M Innovative Properties Company Liquid crystal polymers for flexible circuits
US7348045B2 (en) * 2002-09-05 2008-03-25 3M Innovative Properties Company Controlled depth etched dielectric film
US6696163B2 (en) * 2000-07-18 2004-02-24 3M Innovative Properties Company Liquid crystal polymers for flexible circuits
US6391932B1 (en) * 2000-08-08 2002-05-21 Shipley Company, L.L.C. Porous materials
US6375062B1 (en) * 2000-11-06 2002-04-23 Delphi Technologies, Inc. Surface bumping method and structure formed thereby
KR100878863B1 (ko) * 2001-02-21 2009-01-15 가부시키가이샤 가네카 배선기판 및 그 제조 방법, 및 그 배선기판에 사용되는폴리이미드 필름 및 그 제조 방법에 사용되는 에칭액
US6498381B2 (en) * 2001-02-22 2002-12-24 Tru-Si Technologies, Inc. Semiconductor structures having multiple conductive layers in an opening, and methods for fabricating same
US6611046B2 (en) 2001-06-05 2003-08-26 3M Innovative Properties Company Flexible polyimide circuits having predetermined via angles
US7202556B2 (en) * 2001-12-20 2007-04-10 Micron Technology, Inc. Semiconductor package having substrate with multi-layer metal bumps
US7267883B2 (en) * 2002-09-25 2007-09-11 Kaneka Corporation Polyimide film and laminate having metal layer and same

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110942914A (zh) * 2014-06-11 2020-03-31 阿维科斯公司 低噪电容器
JP2020161846A (ja) * 2014-06-11 2020-10-01 エイブイエックス コーポレイション 低ノイズコンデンサ
JP2022191523A (ja) * 2014-06-11 2022-12-27 キョーセラ・エイブイエックス・コンポーネンツ・コーポレーション 低ノイズコンデンサ
JP2020533419A (ja) * 2017-09-11 2020-11-19 フジフイルム エレクトロニック マテリアルズ ユー．エス．エー．， インコーポレイテッド 誘電フィルム形成用組成物
JP7140687B2 (ja) 2017-09-11 2022-09-21 フジフイルム エレクトロニック マテリアルズ ユー．エス．エー．， インコーポレイテッド 誘電フィルム形成用組成物

Also Published As

Publication number Publication date
KR20060124730A (ko) 2006-12-05
US20060118830A1 (en) 2006-06-08
US7012017B2 (en) 2006-03-14
CN1930928A (zh) 2007-03-14
WO2005074339A1 (en) 2005-08-11
US20050167829A1 (en) 2005-08-04
CA2554750A1 (en) 2005-08-11
EP1709848A1 (en) 2006-10-11

Similar Documents

Publication Publication Date Title
US7012017B2 (en) Partially etched dielectric film with conductive features
TW548816B (en) Formation method of conductor pillar
US8418361B2 (en) Method of manufacturing printed circuit board having landless via hole
TWI454191B (zh) 柔性電路板及其製作方法
EP0433996B1 (en) Process for producing an anisotropic conductive film
US20090095508A1 (en) Printed circuit board and method for manufacturing the same
US20080089046A1 (en) Printed Wiring Board for Mounting Electronic Components and Semiconductor Device Using Same
CN1149649C (zh) 半导体元件安装用中继基板的制造方法
TWI296843B (en) A method for manufacturing a coreless package substrate
TW200939927A (en) Wiring substrate and its manufacturing process
JP4129166B2 (ja) 電解銅箔、電解銅箔付きフィルム及び多層配線基板と、その製造方法
KR20100025572A (ko) 금속 코어 기재를 포함하는 회로 어셈블리 및 그의 제조 방법
CN102111954A (zh) 线路板及其制作工艺
KR20050020699A (ko) 양면 배선 회로 기판 및 그 제조 방법
TW201206296A (en) Multilayer wiring substrate and method of manufacturing the same
JP2008172151A (ja) 多層配線基板
KR100794544B1 (ko) 범프가 부착된 배선회로 기판 및 그 제조방법
US20140042122A1 (en) Method of manufacturing printed circuit board
CN202396084U (zh) 可挠性电路板
KR20100111858A (ko) 인쇄회로기판 제조를 위한 범프 형성 방법
US8171626B1 (en) Method for forming embedded circuit
CN102196673B (zh) 线路结构的制作方法
MXPA06008564A (es) Pelicula dielectrica parcialmente grabada quimicamente con caracteristicas conductoras
KR101122146B1 (ko) 매립형 인쇄회로기판, 다층 인쇄회로기판 및 이들의 제조방법
JPH05325669A (ja) 異方導電フィルムの製造方法

Legal Events

Date Code Title Description
A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20080115

A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20080115

A761 Written withdrawal of application

Free format text: JAPANESE INTERMEDIATE CODE: A761

Effective date: 20080507