JP2007514327A - レジスト剥離中における多孔質低誘電率材料の損傷を阻止する方法 - Google Patents
レジスト剥離中における多孔質低誘電率材料の損傷を阻止する方法 Download PDFInfo
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Abstract
【解決手段】多孔質低誘電率層内に形状を形成する方法が提供される。先ず、基板の上に、多孔質低誘電率層が配される。次いで、多孔質低誘電率層の上に、パターン形成されたフォトレジストマスクが配される。次いで、多孔質低誘電率層内に、形状がエッチングされる。形状のエッチング後は、形状の上に保護層が成長される。そして、保護層の一部が除去されるように、パターン形成されたフォトレジストマスクが剥離され、形状内に、保護層で形成された保護壁を残留させる。
【選択図】図1
Description
本発明の一実施例では、先ず、基板の上に、JSR LKD−5109の多孔質誘電体層がスピン塗布される。次いで、多孔質誘電体層の上に、酸化ケイ素からなるキャップ層が成長される。キャップ層は、約500オングストロームの厚さである。次いで、キャップ層の上に、有機質のARC層が形成される。次いで、ARCの上に、パターン形成されたフォトレジストマスクが形成される。この実施例において、フォトレジストは、シプレイ社による193nm PRである。
208…基板
209…コンタクト
210…障壁層
212…キャップ層
214…反射防止膜
216…レジストマスク
220…アパーチャ
224…開口
228…保護層
230…保護壁
240…障壁層
244…銅コンタクト層
246…銅
300…プラズマ処理チャンバ
302…閉じ込めリング
304…上部電極
308…下部電極
310…ガス供給源
312…エッチャントガス供給源
316…保護層用ガス供給源
318…剥離用ガス供給源
320…排出ポンプ
328…反応容器のトップ
335…制御器
344…第1のRF供給源
348…第2のRF供給源
352…チャンバ壁
1300…コンピュータシステム
1302…モニタ
1304…ディスプレイ
1306…ハウジング
1308…ディスクドライブ
1310…キーボード
1312…マウス
1314…ディスク
1320…システムバス
1322…プロセッサ
1324…メモリ
1326…固定ディスク
1330…スピーカ
1340…ネットワークインターフェース
Claims (18)
- 多孔質低誘電率層内に形状を形成する方法であって、
基板の上に、多孔質低誘電率層を配する工程と、
前記多孔質低誘電率層の上に、パターン形成されたフォトレジストマスクを配する工程と、
前記多孔質低誘電率層内に、形状をエッチングする工程と、
前記形状のエッチング後に、前記形状の上に保護層を成長させる工程と、
前記保護層の一部が除去されるように、前記パターン形成されたフォトレジストマスクを剥離させる工程であって、前記形状内に、前記保護層で形成された保護壁を残留させる、工程と、
を備える方法。 - 請求項1に記載の方法であって、さらに、
前記フォトレジストマスクを配する前に、前記多孔質低誘電率層の上にキャップ層を配する工程であって、前記フォトレジストマスクは、前記キャップ層の上に配される、工程を備える方法。 - 請求項1ないし2のいずれかに記載の方法であって、さらに、
前記保護壁の上に成長層を成長させる工程を備える方法。 - 請求項2ないし3のいずれかに記載の方法であって、さらに、
前記フォトレジストマスクを配する前に、前記キャップ層の上に反射防止膜を形成する工程であって、前記フォトレジストマスクは、前記反射防止膜の上に配される、工程を備える方法。 - 請求項1ないし4のいずれかに記載の方法であって、
前記保護層を成長させる工程は、フッ素を含有しない層を成長させる工程を含む、方法。 - 請求項1ないし5のいずれかに記載の方法であって、
前記保護層を成長させる工程は、さらに、ポリマ層を成長させる工程を含む、方法。 - 請求項1ないし6のいずれかに記載の方法であって、
前記保護層は、100オングストロームから1500オングストロームまでの間の厚さである、方法。 - 請求項1ないし7のいずれかに記載の方法であって、
前記ポリマ層を成長させる工程は、C2H4およびO2の成長用ガスを供給する工程を含む、方法。 - 請求項1ないし8のいずれかに記載の方法であって、
前記剥離させる工程は、水素、窒素、アンモニア、および酸素のうちの少なくとも1つより選択された剥離用ガスを供給する工程を含む、方法。 - 請求項1ないし9のいずれかに記載の方法であって、
前記多孔質低誘電率層は、ナノメートルサイズの孔を有する、方法。 - 請求項1ないし10のいずれかに記載の方法であって、
前記剥離させる工程は、イオン衝撃を使用する工程を含む、方法。 - 請求項11に記載の方法であって、
前記イオン衝撃は、前記保護層の上層は除去するが、前記保護層で形成された保護壁は残留させる、方法。 - 請求項1ないし12のいずれかに記載の方法であって、
前記保護壁の上に成長される成長層は、障壁層である、方法。 - 請求項1ないし13のいずれかに記載の方法であって、さらに、
前記基板をエッチングチャンバ内に配する工程を備え、前記エッチングする工程、前記保護層を成長させる工程、および前記パターン形成されたフォトレジストマスクを剥離させる工程は、前記エッチングチャンバ内のその場で実施される、方法。 - 請求項1ないし14のいずれかに記載の方法によって形成される半導体デバイス。
- 基板の上の多孔質低誘電率層内にマスクを通して形状をエッチングするための装置であって、
プラズマ処理チャンバであって、
プラズマ処理チャンバ筐体を形成するチャンバ壁と、
前記プラズマ処理チャンバ筐体内において基板を支持するための基板支持部と、
前記プラズマ処理チャンバ筐体内における圧力を調整するための圧力調整部と、
プラズマを維持するために前記プラズマ処理チャンバ筐体内に電力を供給するための少なくとも1つの電極と、
前記プラズマ処理チャンバ筐体内にガスを供給するためのガス供給口と、
前記プラズマ処理チャンバ筐体内からガスを排出させるためのガス排出口と
を備えるプラズマ処理チャンバと、
前記ガス供給口に流体接続されているガス供給源と、
前記ガス供給源、前記少なくとも1つの電極、前記圧力調整部、前記ガス供給口、および前記ガス排出口の少なくとも1つに制御可能なかたちで接続されている制御部であって、
少なくとも1つの処理部と、
コンピュータ可読媒体であって、
多孔質低誘電率層内に形状をエッチングするためのエッチング用プラズマを供給するためのコンピュータ可読コードと、
前記形状のエッチング後に前記形状の上に保護層を形成するための成長用プラズマを供給するためのコンピュータ可読コードと、
前記多孔質低誘電率層の上からフォトレジストマスクの剥離を行うためのコンピュータ可読コードと
を含み、前記剥離は、前記保護層の一部を除去し、前記保護層で形成された保護壁を残留させる、コンピュータ可読媒体と
を有する制御部と
を備える装置。 - 基板の上に配され、かつ、パターン形成されたフォトレジストマスクの下に配された多孔質低誘電率層内に、形状を形成する方法であって、
前記フォトレジストマスクを通して、前記多孔質低誘電率層内に形状をエッチングする工程と、
前記形状のエッチング後に、前記形状の上に保護層を成長させる工程と、
前記保護層の一部が除去されるように、前記パターン形成されたフォトレジストマスクを剥離させる工程であって、前記形状内に、前記保護層で形成された保護壁を残留させる、工程と、
を備える方法。 - 請求項17に記載の方法であって、
前記保護層を成長させる工程は、さらに、ポリマ層を成長させる工程を含む、方法。
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US10/738,280 US7081407B2 (en) | 2003-12-16 | 2003-12-16 | Method of preventing damage to porous low-k materials during resist stripping |
PCT/US2004/040267 WO2005060548A2 (en) | 2003-12-16 | 2004-12-01 | Method of preventing damage to porous low-k materials during resist stripping |
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JP2007514327A true JP2007514327A (ja) | 2007-05-31 |
JP2007514327A5 JP2007514327A5 (ja) | 2008-04-24 |
JP4668205B2 JP4668205B2 (ja) | 2011-04-13 |
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JP2006545700A Expired - Fee Related JP4668205B2 (ja) | 2003-12-16 | 2004-12-01 | 多孔質低誘電率層内に形状を形成する方法および装置 |
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Country | Link |
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US (2) | US7081407B2 (ja) |
EP (1) | EP1697984A4 (ja) |
JP (1) | JP4668205B2 (ja) |
KR (1) | KR101094681B1 (ja) |
CN (1) | CN100524668C (ja) |
IL (1) | IL176101A0 (ja) |
TW (1) | TWI353019B (ja) |
WO (1) | WO2005060548A2 (ja) |
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- 2004-12-01 CN CNB2004800375736A patent/CN100524668C/zh active Active
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Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
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JP2001196455A (ja) * | 1999-10-29 | 2001-07-19 | Lucent Technol Inc | 半導体素子の製造方法 |
WO2002003454A2 (en) * | 2000-06-30 | 2002-01-10 | Lam Research Corporation | Method for etching dual damascene structures in organosilicate glass |
JP2003197742A (ja) * | 2001-12-26 | 2003-07-11 | Toshiba Corp | 半導体装置およびその製造方法 |
Also Published As
Publication number | Publication date |
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KR20060114347A (ko) | 2006-11-06 |
EP1697984A2 (en) | 2006-09-06 |
WO2005060548A3 (en) | 2006-02-23 |
US20060240661A1 (en) | 2006-10-26 |
WO2005060548A2 (en) | 2005-07-07 |
CN100524668C (zh) | 2009-08-05 |
CN1894784A (zh) | 2007-01-10 |
TWI353019B (en) | 2011-11-21 |
TW200527532A (en) | 2005-08-16 |
EP1697984A4 (en) | 2009-12-23 |
JP4668205B2 (ja) | 2011-04-13 |
IL176101A0 (en) | 2006-10-05 |
US7081407B2 (en) | 2006-07-25 |
US20050130435A1 (en) | 2005-06-16 |
KR101094681B1 (ko) | 2011-12-20 |
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