TWI353019B - Method of preventing damage to porous low-k materi - Google Patents
Method of preventing damage to porous low-k materi Download PDFInfo
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- TWI353019B TWI353019B TW093137791A TW93137791A TWI353019B TW I353019 B TWI353019 B TW I353019B TW 093137791 A TW093137791 A TW 093137791A TW 93137791 A TW93137791 A TW 93137791A TW I353019 B TWI353019 B TW I353019B
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
- H01L21/76831—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers in via holes or trenches, e.g. non-conductive sidewall liners
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31127—Etching organic layers
- H01L21/31133—Etching organic layers by chemical means
- H01L21/31138—Etching organic layers by chemical means by dry-etching
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31144—Etching the insulating layers by chemical or physical means using masks
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Power Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Chemical Kinetics & Catalysis (AREA)
- General Chemical & Material Sciences (AREA)
- Drying Of Semiconductors (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Formation Of Insulating Films (AREA)
Description
1353019 (1) 九、發明說明 【發明所屬之技術領域】 本發明係有關以半導體爲基礎的裝置之製造。更具體 而言,本發明係有關製造具有多孔低 k値介質層的以半 導體爲基礎的裝置之改良式技術。 【先前技術】 在以半導體爲基礎的裝置(例如積體電路或平板顯示 器)製造時,可配合銅導體材料而使用雙鑲嵌結構,以便 減少與前一代技術中所用的以鋁爲基礎的材料中之信號傳 播相關聯的 RC延遲。在雙鑲嵌中,並不是蝕刻導體材 料,而是可能將通孔及溝槽蝕刻到介質材料,並以銅將其 塡滿。可以化學機械硏磨(Chemical Mechanical Polishing ;簡稱 CMP )製程能去除過多的銅,而留下被 通孔連接的銅線,以供信號傳輸。爲了進一步減少 Rc 延遲,可使用多孔低介電常數的材料。這些多孔低介電常 數的材料可包括多孔有機矽玻璃(〇rgano-Silieate_ Glass;簡稱 〇SG)料料。0SG 材料可以是以諸如甲基 官能基等的有機成分摻雜的二氧化矽。0SG材料具有辛皮 加入二氧化矽晶格的碳及氫原子,因而可降低該材料的介 電常數。然而’當 〇SG材料接觸到被用來剝除光阻的氧 氣、氫氣、及氨氣時,0SG材料易於受損。多孔材料具 有許多細孔,因而可讓剝除電發更深地進入該層,而造成 更大的損害。 -4 - (2) (2)1353019 多孔0S G材料可能因有機成分接觸到用來剝除剛組 及側壁的電號而非常易於受損。該電漿可能擴散到多孔 OSG層的細孔’並造成自開孔的邊界算起深入OSG層 達 300奈米的損傷。該電漿所造成的損傷是自受損區去 除了碳及氫’而造成 OSG更像具有較高介電常數的二氧 化矽。可利用 FTIR分析以量測 OSG層的 SiC/SiO 比率之改變,而將損傷量化。當被換算到溝槽側壁時,意 指在一2000 埃的溝槽側壁的每一面上有幾百埃的損 傷。 最好是能在剝除製程期間減少對多孔低 k値介質層 的損傷。 【發明內容】 爲了達到前文所述的及其他的目的,且根據本發明之 目的,提供了一種在一多孔低 k値介質層中'形成一特徵 部位之方法。在一基材之上設置一多孔低 k値介質層。 在該多孔低 k値介質層之上設置一圖樣化的光阻罩幕 層。將一特徵部位蝕刻到該多孔低 k値介質層。在蝕刻 了該特徵部位之後,在該特徵部位之上沈積一保護層。剝 除該圖樣化的光阻罩幕層,以便去除該保護層的一部分, 其中自該保護層形成的若干保護壁之小部分保留在該特徵 部位中。 在本發明的另一表現形式中,提供了一種經由一基材 之上的一罩幕層而蝕刻一多孔低 k値介質層中之一特徵 -5- (3) (3)1353019 部位之裝置。提供了一電漿處理室,該電漿處理室包含: 用來形成一電漿處理室外殼的一腔室壁、用來支承該電漿 處理室外殼內的一基材之一基材支座、用來調節該電漿處 理室外殼中之壓力的一壓力調節器、用來將電力提供給該 電漿處理室外殼以便維持一電漿之至少一個電極、用來將 氣體提供到該電漿處理室外殼之一進氣口、以及用來自該 電漿處理室外殼排出氣體的一出氣口。一氣體來源係在液 態下連接到該進氣口。將一控制器以可控制之方式連接到 該氣體來源、該等至少一個電極、該壓力調節器、該進氣 口、及該出氣口的至少其中之一。該控制器包含至少一個 處理器及電腦可讀取的媒體。該電腦可讀取的媒體包含: 用來提供一蝕刻電漿以便將一特徵部位蝕刻到一多孔低k 値介質層之電腦可讀取的程式碼、用來提供一沈積電漿以 便在蝕刻了該特徵部位之後在該特徵部位之上形成一保護 層之電腦可讀取的程式碼、以及自該多孔低k値介質層 之上剝除一光阻罩幕層之電腦可讀取的程式碼,其中該剝 除步驟去除了該保護層的一部分,且保留了自該保護層形 成的若干小保護壁。 在本發明的另一表現形式中,提供了一種在一基材之 上且被配置在一圖樣化的光阻罩幕層之下的—多孔低 k 値介質層中形成一特徵部位之方法。經由該光阻罩幕層而 將一特徵部位蝕刻到該多孔低k値介質層。在蝕刻了該 特徵部位之後’在該特徵部位之上沈積一保護層。剝除該 圖樣化的光阻罩幕層,以便去除該保護層的一部分,其中 -6 - (4) (4)1353019 自該保護層形成的若千保護壁保留在該特徵部{立+。 將在下文的本發明之詳細說明中配合各附圖而更詳細 地說明本發明的上述這些及其他的特徵。 【實施方式】 現在將參照附圖中不出的本發明之一些較佳實施例而 說明本發明。在下文的說明中,述及了許多特定的細節, 以便提供對本發明的徹底了解。然而,熟習此項技術者當 可了解,可在沒有這些特定細節的全部或部分之情形下實 施本發明。在其他的情形中,並未詳細說明一些習知的製 程步驟及(或)結構,以便不會非必要地模糊了本發明。 爲了有助於說明,圖1是本發明的一較佳實施例中 所用的多孔低k値介質層的一蝕刻製程之一流程圖。其 中該等細孔是奈米尺寸的細孔。該等細孔更好的是自大約 1奈米至大約10奈米。在定義及申請專利範圍中,多 孔低 k値介質是一種介電常數小於 23的介質,這是 因爲介電常數小於2.3的介質材料通常是多孔的。多孔 低k値介質材料的某些例子是由JSR Corporati〇n (位 於 Tokyo, Japan )製造的 JSR LKD-5109 低 k 値介 質、以及由係爲 Rohm and Haas公司(位於 P h i 1 a d e 1 p h i a, P A )的子公司之 S h i p ] e y M i c r o e 1 e c t r ο n i c s 公司製造的Zirk〇n™ LK。某些多孔低k値介質材料係 基於有機矽玻璃(O S G )。其他的多孔低k値介質材料 是不含矽的純有機材料之多孔S ILK。圖2 A - D是根據 (5) 1353019 圖1所示製程的一多孔低k値介質層 如圖2A所示,可在步驟(〗04 )中在— 沈積一多孔介質層(2〇4)。基材(208) 或任何類型的材料,或者可以是在一晶圓 部分。在步驟(108)中,在多孔介質層彳 —覆蓋層(212)。覆蓋層(212)可以是 而言’該覆蓋層是由一介質材料構成之一 (212)在化學機械硏磨(CMP)及其他 孔介質層(2 04 )。覆蓋層(212 )可以 質’這是因爲該覆蓋層是最終產品的一部 好是一種以氧化矽爲基礎的材料。該覆蓋 約 200 埃與大約 1 000 埃之間的一 (112)中,在覆蓋層(212)之上沈賴 (AntiReflective Coating ;簡稱 ARC)( 塗層(ARC) (214)可以是一有機底 (Bottom AntiReflective Coating ;簡稱 無機介質抗反射塗層 (Dielectric Coating ;簡稱 DARC)。該 ARC 具有, 約 1 0 0 0埃之間的一厚度。在步驟(1 1 < (214)之上提供一圖樣化的光阻罩幕層< 的光阻罩幕層(216)具有一孔(220) 層,使該光阻層暴露於一光線圖樣’然後 而形成該圖樣化的光阻罩幕層。亦可使用 光阻罩幕層之其他方法。基材(208 ) 之示意側視圖。 -基材(20 8 )上 可以是一矽晶圓 之上的一層之一 :204 )之上形成 二氧化砂。一般 保護層。覆蓋層 製程期間保護多 是一低 k 値介 分。該覆蓋層最 層最好是具有大 厚度。在步驟 ί 一抗反射塗層 :2 1 4 )。抗反射 部抗反射塗層 BARC)、或一 AntiReflective :約 100埃與大 5 )中,在 ARC :2 1 6 )。圖樣化 。可設置一光阻 蝕刻該光阻層’ 形成一圖樣化的 可具有一接點 (6) (6)1353019 (209 )及一障壁層(210)。 在步驟(12〇)中,可將基材(208)置於一蝕刻室, 而在該蝕刻室中蝕刻該多孔介質層(204 )。如圖 2B所 示,可使用一電漿乾式蝕刻製程來蝕刻多孔介質層 (204 ),而在圖樣化的光阻罩幕層(216)中之孔 (220 )之下形成一開口( 224 )。在該多孔介質層蝕刻期 間去除了某些圖樣化的光阻罩幕層(216)。此種多孔介 質蝕刻可使用一化學蝕刻,例如使用一以氟爲基礎的蝕刻 劑》例如’ 一蝕刻化學品可使用低壓下的八氟環丁烷 (C4F8 )及氮氣。因此,可蝕刻該特徵部位的側壁。此 外,此種蝕刻可在蝕刻期間沈積聚合物。此種蝕刻可使用 一些氧氣,但氧氣的量通常將小於剝除製程中所使用氧氣 的量。因爲氧氣的量較小,且保持較小的壓力,所以該蝕 刻化學品並未如同剝除製程般地損及該多孔介質。 如圖 2C所示,然後在步驟(124 )中於所蝕刻的特 徵部位之上沈積一保護層(228)。在一較佳實施例中, 係由一聚合物沈積形成該保護層。此種聚合物沈積化學品 可使用由乙烯及氮氣或甲烷及氧氣構成的一沈積化學品。 爲了避免損及露出的多孔介質,最好是將一不含氟的化學 品用於聚合物的形成。該聚合物沈積的厚度最好是在大約 100埃與 15〇〇埃之間。該聚合物沈積的厚度更好是在 大約 200埃與8 00埃之間。該聚合物沈積的厚度尤其 最好是在大約 2 0 0埃與 5 0 0埃之間。 如圖 2 D所示,在步驟(1 2 8 )中,使用一剝除製程 -9- (7) (7)1353019 剝除圖樣化的光阻罩幕層(2 1 6 ),該剝除製程也去除了 該保護層的一部分,而留下特徵部位(224 )中之保護層 的保護壁(23 0 )’以便保護該多孔介質。演型的光阻剝 除化學品使用以氧氣、氨氣、聯氨(N2H2 )爲基礎的剝除 化學品。這些剝除化學品可擴散經過該等細孔,而造成對 在該露出表面之下深處的多孔低 k値介質的有機成分之 損傷,而造成對該低 k値介質的相當大的一部分之損 傷。然而,保護壁(230 )提供了對多孔介質層(2〇4 )的 保護,因而在剝除製程期間不會有多孔介質層的任何露出 表面。保護壁(230)薄的足以避免黏著失敗。如果該等 保護壁太厚,則該等保護壁可能會分層,而造成黏著失 敗。另一方面,如果原始的保護層太薄,則對多孔介質層 的保護不夠。一般而言,可能因蝕刻步驟而形成的側壁是 太薄,而無法對多孔介質層提供足夠的保護,這就是在完 成蝕刻之後需要有一聚合物沈積步驟的原因。在該剝除期 間使用了離子撞擊,以便最好是在無須去除保護壁的情形 下去除保護層的上表面。 在本發明的某些實施例中,可在剝除光阻(2 1 6 )之 後打開障壁層(2 1 0 )。保護壁(23 0 )可在打開障壁層 (210)的期間進一步保護該多孔介質層。在步驟(132) 中,然後在保護壁(230)之上形成次一層。在一例子 中’如圖2 E所示’係在保護壁(2 3 0 )之上形成一障壁 層(240 ),且在該特徵部位中及該特徵部位之上形成一 銅接點層(2 4 4 )。如圖2 F所示,使用化學機械硏磨來 -10 - (8) (8)1353019 去除障壁層(240)及銅接點層( 24 4)的過量部分,以便 形成一銅(246)。 圖 3是一電漿處理室(300 )的一示意圖,可將該 電漿處理室(300 )用來蝕刻特徵部位,然後沈積保護 層,而後在原處剝除光阻。電漿處理室(300)包含若干 限制環(3 02 )、一上電極(3 04 )、一下電極(3 08 )、 —氣體來源(310 )、以及一排氣泵(320 )。氣體來源 (3 1 0 )包含一蝕刻劑氣體來源(3 1 2 )、一保護層氣體來 源(3〗6 )、以及一剝除氣體來源(3 1 8 )。氣體來源 (310)可包含額外的氣體來源。在電漿處理室( 3 00 ) 內,基材(20 8 )被設置在下電極(3 08 )之上。下電極 (308)設有一適當的基材夾持機構(例如,靜電或機械 夾持機構等的夾持機構),用以夾住基材(208)。反應 器頂部(328)設有被配置在下電極(308)正對面的上電 極(304)。上電極(304)、下電極(308)、及限制環 (302)界定了被限制的電漿容積。氣體來源(310)將氣 體供應到該被限制的電漿容積,且排氣泵(3 20 )將氣體 自該被限制的電漿容積經由限制環(3 02 )及一排氣口而 排出。一第一射頻來源(344)係在電氣上連接到上電極 (304)。一第二射頻來源(348)係在電氣上連接到下電 極(308)。腔室壁(352)圍繞限制環(302)、上電極 (3 04 )、及下電極(308)。第一射頻來源(3 44 )及第 二射頻來源(348)可包含一個 27 MHz的電源及一個 2 MHz的電源。將射頻電源連接到電極之方式的不同組合 -11 - (9)1353019 都是可 ί"Τ 的。可將 LAM Research Corporation Fremont, California )所製造的一 Exelan™ 用 的一較佳實施例。 圖 4A及 4B示出一電腦系統(1300), 統( 1300)適於實施本發明的實施例中所用的. (335)。圖 4A示出電腦系統的一種可能的實 當然’該電腦系統可具有範圍自一積體電路、一 板、一小型手持裝置、至一巨大的超級電腦之許 式。電腦系統(1 3 00 )包含一監視器(1 3 02 )、 (1304)、一外殼(1306)、一 磁碟機(1308) (1310)、以及一滑鼠(1312) » 磁碟(1314) 將資料轉移自電腦系統(1 3 0 0 )並自電腦系統( 移資料的一電腦可讀取的媒體。 圖 4B是電腦系統( 1300)的一例示方塊. 的子系統可被連接到系統匯流排(1 320 )。一個 理器(1 3 22 )(也被稱爲中央處理單元 Processing Unit;簡稱 CPU))被耦合到其中包 (1 3 24 )的儲存裝置。記憶體(1 3 24 )包括隨機 體(Random Access Memory;簡稱 RAM)及唯 (Read Only Memory;簡稱 ROM) ^ 如此項技 的’ ROM係用來將資料及指令單向地轉移到 RAM通常係用來以一種雙向之方式轉移資料及; 兩類型的記憶體可包括將於下文中說明的任何適 可讀取的媒體。一固定式磁碟(1 3 2 6 )亦雙向地: ™ (位於 於本發明 該電腦系 一控制器 體形式。 印刷電路 多實體形 一顯示器 、一鍵盤 是一用來 1300)轉 圖。多種 或多個處 (Central 括記憶體 存取記憶 讀記憶體 術中習知 CPU,且 指令。追 用之電腦 被耦合到 -12 - (10) (10)1353019 CPU ( 1 322 );該固定式磁碟(1 326 )提供額外的資料儲 存容量,且亦可包括將於下文中說明的任何適用之電腦可 讀取的媒體。可將固定式磁碟(1 3 26 )用來儲存程式及指 令等的內容,且通常是比主要儲存媒體慢的一輔助儲存媒 體(例如一硬碟)。我們當了解,固定式磁碟( 1326)內 存放的資訊在適當的情形下可以虛擬記憶體之標準方式被 包含在記憶體(1 3 24 )中。抽取式磁碟(1314)可採用將 於下文中說明的任何電腦可讀取的媒體之形式。 處理器(1 322 )也被耦合到諸如顯示器(1 304 )、鍵 盤(1 3 1 0 )、滑鼠(1 3 1 2 )、及喇叭(1 3 3 0 )等的各種輸 入/輸出裝置》—般而言,一輸入/輸出裝置可以是下列 裝置中之任何一種:視訊顯示器、軌跡球、滑鼠、鍵盤、 麥克風、觸控式顯示器、換能器介面卡讀取器、磁帶或紙 帶讀取器、數位板、觸控筆、語音或手寫辨識器、人體特 徵讀取器、或其他的電腦。CPU ( 1322)或者可使用網路 介面(134〇)而被耦合到另一電腦或電訊網路。具有此種 網路介面時’可得知在執行前文所述的方法步驟之過程 中’該 CPU可自網路接收資訊’或可將資訊輸出到網 路。此外,本發明之方法實施例可以只在 CPU ( 1 3 22 ) 中執行,或者可配合分擔該處理的一部分之—遠端 CPU 而經由諸如網際網路等的一網路執行該方法。 此外’本發明的實施例進一步係有關具有一電腦可讀 取的媒體之電腦儲存產品,該電腦可讀取的媒體上具有用 來執行各種以電腦執行的作業之電腦程式碼。該媒體及電 -13 - (11) (11)1353019 腦程式碼可以是爲了本發明而特別設計及建構的那些媒體 及電腦程式碼’或者可以是熟習電腦軟體技術者所習知且 可使用的那類媒體及電腦程式碼。電腦可讀取的媒體的例 子包括(但不限於):諸如硬碟、軟碟、及磁帶等的磁性 媒體;諸如唯讀光碟及全像裝置等的光學媒體;諸如磁光 軟碟等的磁光媒體;以及諸如特定應用積體電路 (Application Specific Integrated Circuit ;簡稱 ASIC)、可程式邏輯裝置(Programmable Logic Device; 簡稱 PLD)、以及 ROM及 RAM裝置等的組態被特殊 設定爲儲存並執行程式碼之硬體裝置。電腦程式碼的例子 包括:諸如一編譯器所產生的機器碼等的機器碼、以及含 有由使用一解譯器的一電腦執行的高階程式碼之檔案。電 腦可讀取的媒體也可以是由一載波中包含的一電腦資料信 號所傳輸且代表可由一處理器執行的一序列的指令之電腦 程式碼。 其他的例子可使用其他的沈積裝置。在其他的實施例 中,可將一特殊蝕刻用來在不損及多孔介質層(204)的 情形下去除保護壁(230)。此外,其他的實施例可在不 同的製程室(非原處)中執行蝕刻、一保護層的沈積、及 剝除。 雖然前文中示出一溝槽的蝕刻,但是亦可將本發明用 於在蝕刻一通孔之後的對一通孔或一溝槽之蝕刻、或在先 蝕刻一溝槽之後的對一通孔之蝕刻。在蝕刻了每一特徵部 位之後,可在剝除光阻之前先在該特徵部位之上形成一保 -14 - (12) (12)1353019 護層。在某些情形中,在該等保護壁之上沈積的次—層可 以是一光阻罩幕層。 例子 在本發明的例子中,係將 JSR LKD-5 1 09的一多孔 介質層旋塗到一基材上。在該多孔介質層之上沈積一氧化 砂覆蓋層。該覆蓋層的厚度大約爲 500埃。在該覆蓋層 之上形成一有機 ARC層。在該 ARC層之上形成一圖 樣化的光阻罩幕層。在該例子中,該光阻是由 Shipley 供應的 193奈米正光阻(PR)。 然後在一 Exel an 23 00介質蝕刻器中置入該基材。 經由該 ARC層及該多孔介質層而蝕刻一特徵部位。係將 由 10 seem的八氟環丁烯及 12 seem的氧氣構成的一 蝕刻化學品用來蝕刻通過該多孔介質層。係將該製程室的 壓力設定爲大約120毫托。由27 MHz的射頻來源提 供 1,000瓦的電力。由 2 MHz的射頻來源提供 1,000 瓦的電力。 在完成了對該特徵部位的蝕刻之後,在該特徵部位之 上沈積一保護層。係在原處執行上述步驟。係將由 50 seem的乙烯及 5 Sccm的氧氣構成的一沈積氣體化學品 用來在該特徵部位上形成一聚合物。係將該製程室的壓力 設定爲大約 120毫托。由 27 MHz的射頻來源提供 5 00瓦的電力。由 2 MHz的射頻來源提供 5 00瓦的電 力。該沈積持續I 5秒,以便提供厚度大約爲3 00埃的 •15- (13) (13)1353019 一沈積層。 在沈積了該保護層之後’剝除該光阻罩幕層。係在原 處執行該剝除步驟。係將由 600 seem 的氫氣及 200 seem的氮氣構成的一剝除氣體化學品用來剝除該光阻罩 幕層。係將該製程室的壓力設定爲大約 300毫托。由 27 MHz的射頻來源提供 400瓦的電力。由 2 MHz的 射頻來源提供 400瓦的電力。 _ 雖然已參照數個較佳實施例而說明了本發明,但是仍 # 然可以有在本發明範圍內的各種改變、變更、及替代的等 效物。亦請注意,許許多實施本發明的方法及裝置之替代 方式。因此,應將最後的申請專利範圍詮釋包含在本發明 的真實精神及範圍內的所有此種改變、變更、修改、及各 種替代等效物。 【圖式簡單說明】 係以舉例之方式單非以限制之方式而參照各附圖說明 鲁 本發明’在該等附圖中,相同的代號參照到類似的元件, 這些附圖有: 圖 1是本發明的一實施例所用的一製程之一流程 圖。 圖2 A - F是根據圖〗所示製程的一被蝕刻的多孔 低k値介質層之—示意側視圖。 圖 3是可用於本發明的一實施例的—製程室之一示 意圖。 -16 - (14)1353019 圖 示意圖。 【主要元 204 208 2 12 2 14 2 16 220 209 2 10,240 224 228 23 0 240 246 300 302 304 308 3 10 320 3 12 4A - B是可被用來作爲一控制器的一電腦系統之 件符號說明】 多孔介質層 基材 覆蓋層 抗反射塗層 圖樣化的光阻罩幕層 孔 接點 障壁層 開口 保護層 保護壁 障壁層 銅 電漿處理室 限制環 上電極 下電極 氣體來源 排氣泵 蝕刻劑氣體來源 -17 - (15)1353019 3 16 保 護 層 氣 體 來 3 18 剝 除 氣 體 來 源 328 反 m hd、 器 頂 部 344 第 一 射 頻 來 源 3 4 8 第 二 射 頻 來 源 3 5 2 腔 室 壁 13 00 電 腦 系 統 3 3 5 控 制 器 13 02 監 視 器 13 04 顯 示 器 13 06 外 殼 13 0 8 磁 碟 機 13 10 鍵 盤 13 12 滑 鼠 13 14 磁 碟 13 20 系 統 匯 流 排 13 22 處 理 器 13 24 記 憶 體 13 26 固 定 式 磁 碟 13 14 抽 取 式 磁 碟 13 3 0 喇 叭 13 40 網 路 介 面
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Claims (1)
1353019 附件3A :第093137791號申請專利範圍修正本 民國100年8月9 曰修正 十、申請專利範圍 1. —種在一多孔低 K値介質層中形成一特徵部位 之方法,包含下列步驟: 在一基材之上設置一多孔低 K値介質層: 在該多孔低 K値介質層之上設置圖樣化的光阻罩幕 層; 將一特徵部位蝕刻到該多孔低 K値介質層; 在蝕刻了該特徵部位之後,在該特徵部位之上沈積一 保護層;以及 剝除該圖樣化的光阻罩幕層,以便去除該保護層的一 部分,其中自該保護層形成的若干保護壁保留在該特徵部 位中。 2. 如申請專利範圍第 1項之方法,進一步包含下 列步驟:在設置該光阻罩幕層之前,先在該多孔低 K値 介質層之上設置一覆蓋層,其中係在該覆蓋層之上設置該 光阻罩幕層。 3. 如申請專利範圍第 2項之方法,進一步包含下 列步驟:在該等保護壁之上沈積一沈積層。 4. 如申請專利範圍第 3項之方法,進一步包含下 列步驟:在設置該光阻罩幕層之前,先在該覆蓋層之上形 成一抗反射塗層,其中係在該抗反射塗層之上設置該光阻 罩幕層。 1353019 ♦ 5. 如申請專利範圍第1項之方法,其中沈積該保 護層之該步驟包含下列步驟:沈積一不含氟的層。 6. 如申請專利範圍第1項之方法,其中沈積該保 護層之該步驟進一步包含下列步驟:沈積一聚合物層。 7. 如申請專利範圍第6項之方法,其中該保護層 的厚度是在 100埃與 1 500埃之間。 8. 如申請專利範圍第 7項之方法,其中沈積該聚 合物層之該步驟包含下列步驟:提供由乙烯及氧氣構成的 沈積氣體》 9. 如申請專利範圍第 7項之方法,其中該剝除步 驟包含下列步驟:提供由氫氣、氮氣、氨氣、及氧氣的至 少其中之一選出的一剝除氣體。 1 〇 ·如申請專利範圍第1項之方法,其中該多孔低 Κ値介質層包含若干奈米尺寸的細孔。 11. 如申請專利範圍第1項之方法,其中該剝除步 驟包含下列步驟:使用離子撞擊。 12. 如申請專利範圍第11項之方法,其中該離子 撞擊去除該保護層的各上方層,但是留下由該保護層形成 的若干保護壁。 13. 如申請專利範圍第1項之方法,其中在該等保 護壁之上沈積的該沈積層是一障壁層。 14. 如申請專利範圍第 1項之方法,進一步包含下 列步驟:在一蝕刻室中設置該基材,其中係在該蝕刻室內 於原處執行該蝕刻、對該保護層的該沈積、以及對該圖樣 -2- 1353019 化的光阻罩幕層的該剝除步驟。 15. —種以申請專利範圍第 1項所述之方法形成之 半導體裝置。 16. —種經由一基材之上的一罩幕層而蝕刻一多孔低 K値介質層中之一特徵部位之裝置,包含: 一電漿處理室,該電漿處理室包含: 用來形成一電漿處理室外殼的一腔室壁; 用來支承該電漿處理室外殼內的一基材之一基材 支座; 用來調節該電漿處理室外殻中之壓力的一壓力調 節器; 用來將電力提供給該電漿處理室外殻以便維持一 電漿之至少一個電極; 用來將氣體提供到該電漿處理室外殼之一進氣口 :以及 用來自該電漿處理室外殼排出氣體的一出氣口; 在液態下連接到該進氣ΰ之一氣體來源’包含: 一蝕刻劑氣體來源: 一保護層氣體來源;以及 一剝除氣體來源; 以可控制之方式連接到該氣體來源、該等至少一個電 極、該壓力調節器、該進氣口、及該出氣口的至少其中之 一控制器,該控制器包含: 至少一個處理器,以及 -3- 1353019 電腦可讀取的媒體,該電腦可讀取的媒體包含: 用來提供一蝕刻電漿以便將一特徵部位鈾刻 到一多孔低 κ値介質層之電腦可讀取的程式碼; 用來藉由從該保護層氣體來源提供一保護層 氣體以便在蝕刻了該特徵部位之後在該多孔低 κ値介質 層中之該特徵部位之上形成一保護層之電腦可讀取的程式 碼:以及 自該多孔低 K値介質層之上剝除一光阻罩 幕層之電腦可讀取的程式碼,其中該剝除步驟去除了該保 護層的一部分,且保留了自該保護層形成的若干保護壁。 17. 如申請專利範圍第 16項之裝置,其中該電腦 可讀取的媒體進一步包含用於在該保護壁之上沈積一沈積 層之電腦可讀取的程式碼。 18. 如申請專利範圍第 16項之裝置,其中該保護 層氣體源含有一不含氟的保護層氣體。 19. —種在一基材之上且被配置在圖樣化的光阻罩幕 層之下的一多孔低 K値介質層中形成一特徵部位之方法 ,包含下列步驟: 經由該光阻罩幕層而將一特徵部位蝕刻到該多孔低 K値介質層; 在蝕刻了該特徵部位之後,在該特徵部位之上沈積一 保護層; 剝除該圖樣化的光阻罩幕層,以便去除該保護層的— 部分,其中自該保護層形成的若干保護壁保留在該特徵部 -4- 1353019 位中。 20.如申請專利範圍第 19項之方法,其中沈積該 保護層的該步驟進一步包含下列步驟:沈積一聚合物層。 -5-
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US6919101B2 (en) * | 2003-02-04 | 2005-07-19 | Tegal Corporation | Method to deposit an impermeable film on porous low-k dielectric film |
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2003
- 2003-12-16 US US10/738,280 patent/US7081407B2/en not_active Expired - Lifetime
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2004
- 2004-12-01 KR KR1020067012218A patent/KR101094681B1/ko not_active IP Right Cessation
- 2004-12-01 EP EP04812717A patent/EP1697984A4/en not_active Withdrawn
- 2004-12-01 CN CNB2004800375736A patent/CN100524668C/zh active Active
- 2004-12-01 JP JP2006545700A patent/JP4668205B2/ja not_active Expired - Fee Related
- 2004-12-01 WO PCT/US2004/040267 patent/WO2005060548A2/en active Application Filing
- 2004-12-07 TW TW093137791A patent/TWI353019B/zh not_active IP Right Cessation
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2006
- 2006-06-04 IL IL176101A patent/IL176101A0/en not_active IP Right Cessation
- 2006-06-07 US US11/449,060 patent/US20060240661A1/en not_active Abandoned
Also Published As
Publication number | Publication date |
---|---|
WO2005060548A2 (en) | 2005-07-07 |
IL176101A0 (en) | 2006-10-05 |
CN1894784A (zh) | 2007-01-10 |
EP1697984A4 (en) | 2009-12-23 |
JP4668205B2 (ja) | 2011-04-13 |
US7081407B2 (en) | 2006-07-25 |
US20050130435A1 (en) | 2005-06-16 |
CN100524668C (zh) | 2009-08-05 |
JP2007514327A (ja) | 2007-05-31 |
US20060240661A1 (en) | 2006-10-26 |
KR101094681B1 (ko) | 2011-12-20 |
TW200527532A (en) | 2005-08-16 |
EP1697984A2 (en) | 2006-09-06 |
WO2005060548A3 (en) | 2006-02-23 |
KR20060114347A (ko) | 2006-11-06 |
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