JP2007513516A5 - - Google Patents

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Publication number
JP2007513516A5
JP2007513516A5 JP2006542571A JP2006542571A JP2007513516A5 JP 2007513516 A5 JP2007513516 A5 JP 2007513516A5 JP 2006542571 A JP2006542571 A JP 2006542571A JP 2006542571 A JP2006542571 A JP 2006542571A JP 2007513516 A5 JP2007513516 A5 JP 2007513516A5
Authority
JP
Japan
Prior art keywords
layer
silicide layer
dopant
forming
semiconductor substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2006542571A
Other languages
English (en)
Japanese (ja)
Other versions
JP2007513516A (ja
Filing date
Publication date
Priority claimed from US10/727,999 external-priority patent/US7081655B2/en
Application filed filed Critical
Publication of JP2007513516A publication Critical patent/JP2007513516A/ja
Publication of JP2007513516A5 publication Critical patent/JP2007513516A5/ja
Pending legal-status Critical Current

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JP2006542571A 2003-12-03 2004-10-26 シリサイド成長ドーパント雪かき効果の使用による、デバイス中に階段接合の形成 Pending JP2007513516A (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US10/727,999 US7081655B2 (en) 2003-12-03 2003-12-03 Formation of abrupt junctions in devices by using silicide growth dopant snowplow effect
PCT/US2004/035408 WO2005062387A1 (en) 2003-12-03 2004-10-26 Formation of abrupt junctions in devices by using silicide growth dopant snowplow effect

Publications (2)

Publication Number Publication Date
JP2007513516A JP2007513516A (ja) 2007-05-24
JP2007513516A5 true JP2007513516A5 (enExample) 2007-12-13

Family

ID=34633603

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2006542571A Pending JP2007513516A (ja) 2003-12-03 2004-10-26 シリサイド成長ドーパント雪かき効果の使用による、デバイス中に階段接合の形成

Country Status (8)

Country Link
US (2) US7081655B2 (enExample)
JP (1) JP2007513516A (enExample)
KR (1) KR101093125B1 (enExample)
CN (1) CN1886838B (enExample)
DE (1) DE112004002401B4 (enExample)
GB (1) GB2425404B (enExample)
TW (1) TWI370518B (enExample)
WO (1) WO2005062387A1 (enExample)

Families Citing this family (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20060228850A1 (en) * 2005-04-06 2006-10-12 Pang-Yen Tsai Pattern loading effect reduction for selective epitaxial growth
US7659172B2 (en) * 2005-11-18 2010-02-09 International Business Machines Corporation Structure and method for reducing miller capacitance in field effect transistors
JP2009520373A (ja) * 2005-12-19 2009-05-21 エヌエックスピー ビー ヴィ シリコン・オン・インシュレータ装置におけるソースおよびドレイン形成
US7745847B2 (en) * 2007-08-09 2010-06-29 United Microelectronics Corp. Metal oxide semiconductor transistor
US8273631B2 (en) * 2009-12-14 2012-09-25 United Microelectronics Corp. Method of fabricating n-channel metal-oxide semiconductor transistor
US8513765B2 (en) 2010-07-19 2013-08-20 International Business Machines Corporation Formation method and structure for a well-controlled metallic source/drain semiconductor device
US8846492B2 (en) 2011-07-22 2014-09-30 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated circuit having a stressor and method of forming the same
KR20160058499A (ko) * 2014-11-17 2016-05-25 삼성전자주식회사 반도체 소자, 및 그 반도체 소자의 제조방법과 제조장치
US10510869B2 (en) 2016-05-06 2019-12-17 Silicet, LLC Devices and methods for a power transistor having a Schottky or Schottky-like contact
US9947787B2 (en) 2016-05-06 2018-04-17 Silicet, LLC Devices and methods for a power transistor having a schottky or schottky-like contact
US11228174B1 (en) 2019-05-30 2022-01-18 Silicet, LLC Source and drain enabled conduction triggers and immunity tolerance for integrated circuits
US10892362B1 (en) 2019-11-06 2021-01-12 Silicet, LLC Devices for LDMOS and other MOS transistors with hybrid contact
US11522053B2 (en) 2020-12-04 2022-12-06 Amplexia, Llc LDMOS with self-aligned body and hybrid source
CN120390443B (zh) * 2025-06-30 2025-09-09 合肥晶合集成电路股份有限公司 一种半导体器件及其制作方法

Family Cites Families (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4293587A (en) 1978-11-09 1981-10-06 Zilog, Inc. Low resistance backside preparation for semiconductor integrated circuit chips
US4274892A (en) 1978-12-14 1981-06-23 Trw Inc. Dopant diffusion method of making semiconductor products
DE2926874A1 (de) 1979-07-03 1981-01-22 Siemens Ag Verfahren zum herstellen von niederohmigen, diffundierten bereichen bei der silizium-gate-technologie
US4362597A (en) 1981-01-19 1982-12-07 Bell Telephone Laboratories, Incorporated Method of fabricating high-conductivity silicide-on-polysilicon structures for MOS devices
KR910006249B1 (ko) * 1983-04-01 1991-08-17 가부시기가이샤 히다찌세이사꾸쇼 반도체 장치
US4692348A (en) 1984-06-21 1987-09-08 International Business Machines Corporation Low temperature shallow doping technique
US4885617A (en) 1986-11-18 1989-12-05 Siemens Aktiengesellschaft Metal-oxide semiconductor (MOS) field effect transistor having extremely shallow source/drain zones and silicide terminal zones, and a process for producing the transistor circuit
JPH04291929A (ja) * 1991-03-20 1992-10-16 Toshiba Corp 半導体装置の製造方法
US5352631A (en) * 1992-12-16 1994-10-04 Motorola, Inc. Method for forming a transistor having silicided regions
US5780341A (en) * 1996-12-06 1998-07-14 Halo Lsi Design & Device Technology, Inc. Low voltage EEPROM/NVRAM transistors and making method
US6136636A (en) 1998-03-25 2000-10-24 Texas Instruments - Acer Incorporated Method of manufacturing deep sub-micron CMOS transistors
US6326251B1 (en) 1999-01-12 2001-12-04 Advanced Micro Devices Method of making salicidation of source and drain regions with metal gate MOSFET
US6087235A (en) * 1999-10-14 2000-07-11 Advanced Micro Devices, Inc. Method for effective fabrication of a field effect transistor with elevated drain and source contact structures
US6451693B1 (en) * 2000-10-05 2002-09-17 Advanced Micro Device, Inc. Double silicide formation in polysicon gate without silicide in source/drain extensions
US6812527B2 (en) * 2002-09-05 2004-11-02 International Business Machines Corporation Method to control device threshold of SOI MOSFET's

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