TWI370518B - Formation of abrupt junctions in devices by using silicide growth dopant snowplow effect - Google Patents

Formation of abrupt junctions in devices by using silicide growth dopant snowplow effect

Info

Publication number
TWI370518B
TWI370518B TW093133585A TW93133585A TWI370518B TW I370518 B TWI370518 B TW I370518B TW 093133585 A TW093133585 A TW 093133585A TW 93133585 A TW93133585 A TW 93133585A TW I370518 B TWI370518 B TW I370518B
Authority
TW
Taiwan
Prior art keywords
formation
devices
abrupt junctions
silicide growth
snowplow effect
Prior art date
Application number
TW093133585A
Other languages
English (en)
Chinese (zh)
Other versions
TW200524082A (en
Inventor
Witold P Maszara
Original Assignee
Advanced Micro Devices Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Family has litigation
First worldwide family litigation filed litigation Critical https://patents.darts-ip.com/?family=34633603&utm_source=google_patent&utm_medium=platform_link&utm_campaign=public_patent_search&patent=TWI370518(B) "Global patent litigation dataset” by Darts-ip is licensed under a Creative Commons Attribution 4.0 International License.
Application filed by Advanced Micro Devices Inc filed Critical Advanced Micro Devices Inc
Publication of TW200524082A publication Critical patent/TW200524082A/zh
Application granted granted Critical
Publication of TWI370518B publication Critical patent/TWI370518B/zh

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
    • H01L21/26513—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors of electrically active species
    • H01L21/2652—Through-implantation
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/20—Electrodes characterised by their shapes, relative sizes or dispositions 
    • H10D64/23—Electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. sources, drains, anodes or cathodes
    • H10D64/251—Source or drain electrodes for field-effect devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/027—Manufacture or treatment of FETs having insulated gates [IGFET] of lateral single-gate IGFETs
    • H10D30/0275—Manufacture or treatment of FETs having insulated gates [IGFET] of lateral single-gate IGFETs forming single crystalline semiconductor source or drain regions resulting in recessed gates, e.g. forming raised source or drain regions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/0212—Manufacture or treatment of FETs having insulated gates [IGFET] using self-aligned silicidation
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/601—Insulated-gate field-effect transistors [IGFET] having lightly-doped drain or source extensions, e.g. LDD IGFETs or DDD IGFETs 
    • H10D30/608—Insulated-gate field-effect transistors [IGFET] having lightly-doped drain or source extensions, e.g. LDD IGFETs or DDD IGFETs  having non-planar bodies, e.g. having recessed gate electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/20—Electrodes characterised by their shapes, relative sizes or dispositions 
    • H10D64/23—Electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. sources, drains, anodes or cathodes
    • H10D64/251—Source or drain electrodes for field-effect devices
    • H10D64/258—Source or drain electrodes for field-effect devices characterised by the relative positions of the source or drain electrodes with respect to the gate electrode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
    • H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
    • H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table
    • H01L21/28518—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table the conductive layers comprising silicides

Landscapes

  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • High Energy & Nuclear Physics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Toxicology (AREA)
  • Health & Medical Sciences (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Electrodes Of Semiconductors (AREA)
TW093133585A 2003-12-03 2004-11-04 Formation of abrupt junctions in devices by using silicide growth dopant snowplow effect TWI370518B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US10/727,999 US7081655B2 (en) 2003-12-03 2003-12-03 Formation of abrupt junctions in devices by using silicide growth dopant snowplow effect

Publications (2)

Publication Number Publication Date
TW200524082A TW200524082A (en) 2005-07-16
TWI370518B true TWI370518B (en) 2012-08-11

Family

ID=34633603

Family Applications (1)

Application Number Title Priority Date Filing Date
TW093133585A TWI370518B (en) 2003-12-03 2004-11-04 Formation of abrupt junctions in devices by using silicide growth dopant snowplow effect

Country Status (8)

Country Link
US (2) US7081655B2 (enExample)
JP (1) JP2007513516A (enExample)
KR (1) KR101093125B1 (enExample)
CN (1) CN1886838B (enExample)
DE (1) DE112004002401B4 (enExample)
GB (1) GB2425404B (enExample)
TW (1) TWI370518B (enExample)
WO (1) WO2005062387A1 (enExample)

Families Citing this family (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20060228850A1 (en) * 2005-04-06 2006-10-12 Pang-Yen Tsai Pattern loading effect reduction for selective epitaxial growth
US7659172B2 (en) * 2005-11-18 2010-02-09 International Business Machines Corporation Structure and method for reducing miller capacitance in field effect transistors
JP2009520373A (ja) * 2005-12-19 2009-05-21 エヌエックスピー ビー ヴィ シリコン・オン・インシュレータ装置におけるソースおよびドレイン形成
US7745847B2 (en) * 2007-08-09 2010-06-29 United Microelectronics Corp. Metal oxide semiconductor transistor
US8273631B2 (en) * 2009-12-14 2012-09-25 United Microelectronics Corp. Method of fabricating n-channel metal-oxide semiconductor transistor
US8513765B2 (en) 2010-07-19 2013-08-20 International Business Machines Corporation Formation method and structure for a well-controlled metallic source/drain semiconductor device
US8846492B2 (en) 2011-07-22 2014-09-30 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated circuit having a stressor and method of forming the same
KR20160058499A (ko) * 2014-11-17 2016-05-25 삼성전자주식회사 반도체 소자, 및 그 반도체 소자의 제조방법과 제조장치
US10510869B2 (en) 2016-05-06 2019-12-17 Silicet, LLC Devices and methods for a power transistor having a Schottky or Schottky-like contact
US9947787B2 (en) 2016-05-06 2018-04-17 Silicet, LLC Devices and methods for a power transistor having a schottky or schottky-like contact
US11228174B1 (en) 2019-05-30 2022-01-18 Silicet, LLC Source and drain enabled conduction triggers and immunity tolerance for integrated circuits
US10892362B1 (en) 2019-11-06 2021-01-12 Silicet, LLC Devices for LDMOS and other MOS transistors with hybrid contact
US11522053B2 (en) 2020-12-04 2022-12-06 Amplexia, Llc LDMOS with self-aligned body and hybrid source
CN120390443B (zh) * 2025-06-30 2025-09-09 合肥晶合集成电路股份有限公司 一种半导体器件及其制作方法

Family Cites Families (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4293587A (en) 1978-11-09 1981-10-06 Zilog, Inc. Low resistance backside preparation for semiconductor integrated circuit chips
US4274892A (en) 1978-12-14 1981-06-23 Trw Inc. Dopant diffusion method of making semiconductor products
DE2926874A1 (de) 1979-07-03 1981-01-22 Siemens Ag Verfahren zum herstellen von niederohmigen, diffundierten bereichen bei der silizium-gate-technologie
US4362597A (en) 1981-01-19 1982-12-07 Bell Telephone Laboratories, Incorporated Method of fabricating high-conductivity silicide-on-polysilicon structures for MOS devices
KR910006249B1 (ko) * 1983-04-01 1991-08-17 가부시기가이샤 히다찌세이사꾸쇼 반도체 장치
US4692348A (en) 1984-06-21 1987-09-08 International Business Machines Corporation Low temperature shallow doping technique
US4885617A (en) 1986-11-18 1989-12-05 Siemens Aktiengesellschaft Metal-oxide semiconductor (MOS) field effect transistor having extremely shallow source/drain zones and silicide terminal zones, and a process for producing the transistor circuit
JPH04291929A (ja) * 1991-03-20 1992-10-16 Toshiba Corp 半導体装置の製造方法
US5352631A (en) * 1992-12-16 1994-10-04 Motorola, Inc. Method for forming a transistor having silicided regions
US5780341A (en) * 1996-12-06 1998-07-14 Halo Lsi Design & Device Technology, Inc. Low voltage EEPROM/NVRAM transistors and making method
US6136636A (en) 1998-03-25 2000-10-24 Texas Instruments - Acer Incorporated Method of manufacturing deep sub-micron CMOS transistors
US6326251B1 (en) 1999-01-12 2001-12-04 Advanced Micro Devices Method of making salicidation of source and drain regions with metal gate MOSFET
US6087235A (en) * 1999-10-14 2000-07-11 Advanced Micro Devices, Inc. Method for effective fabrication of a field effect transistor with elevated drain and source contact structures
US6451693B1 (en) * 2000-10-05 2002-09-17 Advanced Micro Device, Inc. Double silicide formation in polysicon gate without silicide in source/drain extensions
US6812527B2 (en) * 2002-09-05 2004-11-02 International Business Machines Corporation Method to control device threshold of SOI MOSFET's

Also Published As

Publication number Publication date
GB2425404B (en) 2007-05-16
CN1886838A (zh) 2006-12-27
KR20060115892A (ko) 2006-11-10
DE112004002401B4 (de) 2009-02-26
GB2425404A (en) 2006-10-25
GB0612074D0 (en) 2006-07-26
US7306998B2 (en) 2007-12-11
CN1886838B (zh) 2011-03-16
US7081655B2 (en) 2006-07-25
US20060211245A1 (en) 2006-09-21
US20050121731A1 (en) 2005-06-09
KR101093125B1 (ko) 2011-12-13
TW200524082A (en) 2005-07-16
JP2007513516A (ja) 2007-05-24
WO2005062387A1 (en) 2005-07-07
DE112004002401T5 (de) 2006-11-30

Similar Documents

Publication Publication Date Title
TWI370518B (en) Formation of abrupt junctions in devices by using silicide growth dopant snowplow effect
GB2417829B (en) Method for forming structures in finfet devices
EP1659850A4 (en) SOIL AERATION APPARATUS
GB0525651D0 (en) Method of fabriating polycrystalline silicon and switching device using polycrystalline silicon
TWI346974B (en) Polycrystalline sige junctions for advanced devices
GB2443819B (en) Methods and compositions for inhibiting intracellular aggregate formation
GB0314390D0 (en) Trench field effect transistor structure
SG117502A1 (en) Concrete for paving
GB2403885B (en) Lawn aerator
GB0205650D0 (en) Gardening implement
GB2415390B (en) Ground tending device
GB0326587D0 (en) Garden spike pole holder
GB0311432D0 (en) Natural thatch tile
GB0318522D0 (en) Field effect transistor
GB0207777D0 (en) Easy paving
GB0221581D0 (en) Soil aeration device
HUP0202499A2 (hu) Eke-szántóvas
GB0317191D0 (en) Dormant turf tile
SG119190A1 (en) Global network based public share placement systemand method
GB0317058D0 (en) Improvements in tractor-powered implements
GB0304228D0 (en) Lawn aerator
AU2004900755A0 (en) Soil Heat of Hydration
AU153349S (en) Paving edging
HU0301760D0 (en) Oyster mushroom growing place
GB0204997D0 (en) Lateral ground effect

Legal Events

Date Code Title Description
MM4A Annulment or lapse of patent due to non-payment of fees