JP2007512704A - シリサイドをソース/ドレインに用いた半導体素子 - Google Patents

シリサイドをソース/ドレインに用いた半導体素子 Download PDF

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Publication number
JP2007512704A
JP2007512704A JP2006541193A JP2006541193A JP2007512704A JP 2007512704 A JP2007512704 A JP 2007512704A JP 2006541193 A JP2006541193 A JP 2006541193A JP 2006541193 A JP2006541193 A JP 2006541193A JP 2007512704 A JP2007512704 A JP 2007512704A
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JP
Japan
Prior art keywords
source
drain
atoms
drain contact
ion implantation
Prior art date
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Withdrawn
Application number
JP2006541193A
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English (en)
Japanese (ja)
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JP2007512704A5 (enExample
Inventor
ジャワラニ、ダルメシュ
ジー. ケイブ、ニゲル
レンデン、マイケル
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NXP USA Inc
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NXP USA Inc
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Publication date
Application filed by NXP USA Inc filed Critical NXP USA Inc
Publication of JP2007512704A publication Critical patent/JP2007512704A/ja
Publication of JP2007512704A5 publication Critical patent/JP2007512704A5/ja
Withdrawn legal-status Critical Current

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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/24Alloying of impurity materials, e.g. doping materials, electrode materials, with a semiconductor body
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26Bombardment with radiation
    • H01L21/263Bombardment with radiation with high-energy radiation
    • H01L21/265Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/26506Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26Bombardment with radiation
    • H01L21/263Bombardment with radiation with high-energy radiation
    • H01L21/265Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/2658Bombardment with radiation with high-energy radiation producing ion implantation of a molecular ion, e.g. decaborane
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00Field-effect transistors [FET]
    • H10D30/01Manufacture or treatment
    • H10D30/021Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/0223Manufacture or treatment of FETs having insulated gates [IGFET] having source and drain regions or source and drain extensions self-aligned to sides of the gate
    • H10D30/0227Manufacture or treatment of FETs having insulated gates [IGFET] having source and drain regions or source and drain extensions self-aligned to sides of the gate having both lightly-doped source and drain extensions and source and drain regions self-aligned to the sides of the gate, e.g. lightly-doped drain [LDD] MOSFET or double-diffused drain [DDD] MOSFET
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00Field-effect transistors [FET]
    • H10D30/01Manufacture or treatment
    • H10D30/021Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/0212Manufacture or treatment of FETs having insulated gates [IGFET] using self-aligned silicidation
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00Electrodes of devices having potential barriers
    • H10D64/01Manufacture or treatment
    • H10D64/021Manufacture or treatment using multiple gate spacer layers, e.g. bilayered sidewall spacers

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  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • High Energy & Nuclear Physics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Toxicology (AREA)
  • Health & Medical Sciences (AREA)
  • Spectroscopy & Molecular Physics (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
JP2006541193A 2003-11-21 2004-10-26 シリサイドをソース/ドレインに用いた半導体素子 Withdrawn JP2007512704A (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US10/718,892 US7262105B2 (en) 2003-11-21 2003-11-21 Semiconductor device with silicided source/drains
PCT/US2004/035546 WO2005052992A2 (en) 2003-11-21 2004-10-26 Semiconductor device with silicided source/drains

Publications (2)

Publication Number Publication Date
JP2007512704A true JP2007512704A (ja) 2007-05-17
JP2007512704A5 JP2007512704A5 (enExample) 2007-12-06

Family

ID=34591179

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2006541193A Withdrawn JP2007512704A (ja) 2003-11-21 2004-10-26 シリサイドをソース/ドレインに用いた半導体素子

Country Status (5)

Country Link
US (1) US7262105B2 (enExample)
JP (1) JP2007512704A (enExample)
KR (1) KR20060126972A (enExample)
CN (1) CN1883042A (enExample)
WO (1) WO2005052992A2 (enExample)

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2005294360A (ja) * 2004-03-31 2005-10-20 Nec Electronics Corp 半導体装置の製造方法
US7253071B2 (en) * 2004-06-02 2007-08-07 Taiwan Semiconductor Manufacturing Company Methods for enhancing the formation of nickel mono-silicide by reducing the formation of nickel di-silicide
US20090159111A1 (en) * 2007-12-21 2009-06-25 The Woodside Group Pte. Ltd Photovoltaic device having a textured metal silicide layer
US20090162966A1 (en) * 2007-12-21 2009-06-25 The Woodside Group Pte Ltd Structure and method of formation of a solar cell
JP2009182089A (ja) * 2008-01-30 2009-08-13 Panasonic Corp 半導体装置の製造方法
US8178430B2 (en) 2009-04-08 2012-05-15 International Business Machines Corporation N-type carrier enhancement in semiconductors
CN102867748B (zh) * 2011-07-06 2015-09-23 中国科学院微电子研究所 一种晶体管及其制作方法和包括该晶体管的半导体芯片
US8648412B1 (en) 2012-06-04 2014-02-11 Semiconductor Components Industries, Llc Trench power field effect transistor device and method
CN117712162A (zh) * 2022-09-08 2024-03-15 联华电子股份有限公司 N型金属氧化物半导体晶体管及其制作方法

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4243433A (en) * 1978-01-18 1981-01-06 Gibbons James F Forming controlled inset regions by ion implantation and laser bombardment
JP2947654B2 (ja) * 1990-10-31 1999-09-13 キヤノン株式会社 Mis型トランジスタ
US5296387A (en) * 1991-03-06 1994-03-22 National Semiconductor Corporation Method of providing lower contact resistance in MOS transistor structures
JP3156436B2 (ja) * 1993-04-05 2001-04-16 日本電気株式会社 ヘテロ接合バイポーラトランジスタ
JP3219996B2 (ja) * 1995-03-27 2001-10-15 株式会社東芝 半導体装置及びその製造方法
US6399452B1 (en) * 2000-07-08 2002-06-04 Advanced Micro Devices, Inc. Method of fabricating transistors with low thermal budget
US6486062B1 (en) * 2000-08-10 2002-11-26 Advanced Micro Devices, Inc. Selective deposition of amorphous silicon for formation of nickel silicide with smooth interface on N-doped substrate
US6445016B1 (en) * 2001-02-28 2002-09-03 Advanced Micro Devices, Inc. Silicon-on-insulator (SOI) transistor having partial hetero source/drain junctions fabricated with high energy germanium implantation
US20020187614A1 (en) * 2001-04-16 2002-12-12 Downey Daniel F. Methods for forming ultrashallow junctions with low sheet resistance
US6998353B2 (en) * 2001-11-05 2006-02-14 Ibis Technology Corporation Active wafer cooling during damage engineering implant to enhance buried oxide formation in SIMOX wafers
US6638802B1 (en) * 2002-06-20 2003-10-28 Intel Corporation Forming strained source drain junction field effect transistors
US6797593B2 (en) * 2002-09-13 2004-09-28 Texas Instruments Incorporated Methods and apparatus for improved mosfet drain extension activation
US20050054164A1 (en) * 2003-09-09 2005-03-10 Advanced Micro Devices, Inc. Strained silicon MOSFETs having reduced diffusion of n-type dopants

Also Published As

Publication number Publication date
CN1883042A (zh) 2006-12-20
KR20060126972A (ko) 2006-12-11
US7262105B2 (en) 2007-08-28
US20050112829A1 (en) 2005-05-26
WO2005052992A2 (en) 2005-06-09
WO2005052992A3 (en) 2005-10-20

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