JP2007511096A5 - - Google Patents

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Publication number
JP2007511096A5
JP2007511096A5 JP2006539644A JP2006539644A JP2007511096A5 JP 2007511096 A5 JP2007511096 A5 JP 2007511096A5 JP 2006539644 A JP2006539644 A JP 2006539644A JP 2006539644 A JP2006539644 A JP 2006539644A JP 2007511096 A5 JP2007511096 A5 JP 2007511096A5
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JP
Japan
Prior art keywords
etching
electrode
computer readable
trench
dielectric layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2006539644A
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English (en)
Japanese (ja)
Other versions
JP2007511096A (ja
JP4865564B2 (ja
Filing date
Publication date
Priority claimed from US10/712,410 external-priority patent/US6949460B2/en
Application filed filed Critical
Publication of JP2007511096A publication Critical patent/JP2007511096A/ja
Publication of JP2007511096A5 publication Critical patent/JP2007511096A5/ja
Application granted granted Critical
Publication of JP4865564B2 publication Critical patent/JP4865564B2/ja
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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JP2006539644A 2003-11-12 2004-11-03 誘電体レイヤにフィーチャをエッチングするための方法及び装置 Expired - Fee Related JP4865564B2 (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US10/712,410 US6949460B2 (en) 2003-11-12 2003-11-12 Line edge roughness reduction for trench etch
US10/712,410 2003-11-12
PCT/US2004/036746 WO2005050700A2 (en) 2003-11-12 2004-11-03 Line edge roughness reduction for trench etch

Publications (3)

Publication Number Publication Date
JP2007511096A JP2007511096A (ja) 2007-04-26
JP2007511096A5 true JP2007511096A5 (enExample) 2008-04-24
JP4865564B2 JP4865564B2 (ja) 2012-02-01

Family

ID=34552675

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2006539644A Expired - Fee Related JP4865564B2 (ja) 2003-11-12 2004-11-03 誘電体レイヤにフィーチャをエッチングするための方法及び装置

Country Status (8)

Country Link
US (2) US6949460B2 (enExample)
EP (1) EP1683194A4 (enExample)
JP (1) JP4865564B2 (enExample)
KR (1) KR101134327B1 (enExample)
CN (1) CN100477135C (enExample)
IL (1) IL175527A0 (enExample)
TW (1) TWI351054B (enExample)
WO (1) WO2005050700A2 (enExample)

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US7723235B2 (en) * 2004-09-17 2010-05-25 Renesas Technology Corp. Method for smoothing a resist pattern prior to etching a layer using the resist pattern
US7196014B2 (en) * 2004-11-08 2007-03-27 International Business Machines Corporation System and method for plasma induced modification and improvement of critical dimension uniformity
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US7556992B2 (en) * 2006-07-31 2009-07-07 Freescale Semiconductor, Inc. Method for forming vertical structures in a semiconductor device
US20080124937A1 (en) * 2006-08-16 2008-05-29 Songlin Xu Selective etching method and apparatus
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US8026180B2 (en) 2007-07-12 2011-09-27 Micron Technology, Inc. Methods of modifying oxide spacers
US8003522B2 (en) * 2007-12-19 2011-08-23 Fairchild Semiconductor Corporation Method for forming trenches with wide upper portion and narrow lower portion
CN103258729B (zh) 2007-12-21 2016-07-06 朗姆研究公司 硅结构的制造和带有形貌控制的深硅蚀刻
US7998872B2 (en) * 2008-02-06 2011-08-16 Tokyo Electron Limited Method for etching a silicon-containing ARC layer to reduce roughness and CD
US8298958B2 (en) * 2008-07-17 2012-10-30 Lam Research Corporation Organic line width roughness with H2 plasma treatment
US8173547B2 (en) * 2008-10-23 2012-05-08 Lam Research Corporation Silicon etch with passivation using plasma enhanced oxidation
US8394722B2 (en) * 2008-11-03 2013-03-12 Lam Research Corporation Bi-layer, tri-layer mask CD control
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JP5655296B2 (ja) * 2009-12-01 2015-01-21 セントラル硝子株式会社 エッチングガス
US8877641B2 (en) * 2009-12-28 2014-11-04 Spansion Llc Line-edge roughness improvement for small pitches
US20130078815A1 (en) * 2011-09-23 2013-03-28 Nanya Technology Corporation Method for forming semiconductor structure with reduced line edge roughness
CN103854995B (zh) * 2012-12-06 2016-10-19 中微半导体设备(上海)有限公司 一种改善侧壁条痕的刻蚀工艺及其装置
JP6239365B2 (ja) * 2013-12-11 2017-11-29 東京エレクトロン株式会社 シリコン層をエッチングする方法
US10734228B2 (en) 2017-12-19 2020-08-04 Tokyo Electron Limited Manufacturing methods to apply stress engineering to self-aligned multi-patterning (SAMP) processes
US11473191B2 (en) * 2019-02-27 2022-10-18 Applied Materials, Inc. Method for creating a dielectric filled nanostructured silica substrate for flat optical devices

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US6686293B2 (en) * 2002-05-10 2004-02-03 Applied Materials, Inc Method of etching a trench in a silicon-containing dielectric material
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