JP2007273698A - 回路装置およびその製造方法 - Google Patents
回路装置およびその製造方法 Download PDFInfo
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- JP2007273698A JP2007273698A JP2006097084A JP2006097084A JP2007273698A JP 2007273698 A JP2007273698 A JP 2007273698A JP 2006097084 A JP2006097084 A JP 2006097084A JP 2006097084 A JP2006097084 A JP 2006097084A JP 2007273698 A JP2007273698 A JP 2007273698A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/191—Disposition
- H01L2924/19101—Disposition of discrete passive components
- H01L2924/19105—Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/191—Disposition
- H01L2924/19101—Disposition of discrete passive components
- H01L2924/19107—Disposition of discrete passive components off-chip wires
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/301—Electrical effects
- H01L2924/30107—Inductance
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Abstract
【解決手段】矩形の回路基板11の表面には、絶縁層12が形成されている。そして、所定の形状の導電パターン13が、絶縁層12の表面に形成されている。更に、導電パターン13には、半田や導電性ペーストを介して、半導体素子15Aおよびチップ素子15Bが電気的に接続されている。回路基板11の表面に形成された導電パターン13、半導体素子15Aおよびチップ素子15Bは、封止樹脂14により被覆されている。リード25は、金属細線17を介して基板上のパッド27と接続され、その一端は回路基板11と重畳している。
【選択図】図1
Description
本形態では、回路装置の一例として混成集積回路装置10の構造を説明する。
本形態では、図2から図5を参照して、混成集積回路装置の製造方法を説明する。
11 回路基板
12 絶縁層
13 導電パターン
14 封止樹脂
15A 半導体素子
15B チップ素子
17 金属細線
19 メッキ膜
20 被覆樹脂
21 孔部
22A 上金型
22B 下金型
23 キャビティ
24 メッキ膜
25A 第1リード
25B 第2リード
26 載置領域
27 パッド
28 配線
29 パッド
30 電極
31 クランパー
40 リードフレーム
41 外枠
44 タイバー
46 ユニット
Claims (10)
- 導電パターン、前記導電パターンから成るパッドおよび前記導電パターンと接続された回路素子が表面に形成された回路基板と、
前記パッドと金属細線を介して接続されたリードと、
少なくとも前記回路基板の表面および前記リードの一部分を被覆する封止樹脂とを具備し、
前記リードの一端は、前記回路基板と重畳することを特徴とする回路装置。 - 前記パッドよりも外側の前記回路基板の表面に、前記導電パターンから成る配線を配置することを特徴とする請求項1記載の回路装置。
- 前記リードの前記封止樹脂に埋め込まれる部分に、前記リードを厚み方向に貫通する孔部を設けることを特徴とする請求項1記載の回路装置。
- 回路基板が配置される載置領域の内部まで端部が延在する複数のリードが一体に連結されたリードフレームを用意する工程と、
前記回路基板を前記載置領域に配置して、前記回路基板と前記リードとを重ね合わせて両者をスポット溶接により接合する工程とを具備することを特徴とする回路装置の製造方法。 - 回路基板が配置される載置領域の内部まで端部が延在する複数のリードが一体に連結されたリードフレームを用意する工程と、
前記回路基板を前記載置領域に配置して、スポット溶接により、少なくとも1つの前記リードと前記回路基板とを接合する工程と、
前記回路基板の表面に設けられたパッドと前記リードとを金属細線を介して接続する工程とを具備することを特徴とする回路装置の製造方法。 - 少なくとも前記回路基板の表面および前記リードを部分的に封止樹脂により被覆する工程を具備することを特徴とする請求項4または請求項5記載の回路装置の製造方法。
- 前記金属細線を介して接続する工程では、前記リードを前記回路基板の表面に当接させることを特徴とする請求項5記載の回路装置の製造方法。
- 前記リードと前記回路基板とを接合する工程は、常温下で行うことを特徴とする請求項4または請求項5記載の回路装置の製造方法。
- 前記リードフレームと前記回路基板は、同じ金属材料から成ることを特徴とする請求項4または請求項5記載の回路装置の製造方法。
- 前記リードフレームおよび前記回路基板は、銅を主材料とする金属から成ることを特徴とする請求項4または請求項5記載の回路装置の製造方法。
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JP2007273698A true JP2007273698A (ja) | 2007-10-18 |
JP5132070B2 JP5132070B2 (ja) | 2013-01-30 |
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Citations (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH02184054A (ja) * | 1989-01-11 | 1990-07-18 | Toshiba Corp | ハイブリッド型樹脂封止半導体装置 |
JPH06291249A (ja) * | 1993-03-31 | 1994-10-18 | Toppan Printing Co Ltd | マルチチップ半導体装置 |
JPH07326708A (ja) * | 1994-06-01 | 1995-12-12 | Toppan Printing Co Ltd | マルチチップモジュール半導体装置 |
JPH0883876A (ja) * | 1994-07-13 | 1996-03-26 | Seiko Epson Corp | 樹脂封止型半導体装置およびその製造方法 |
JP2003017631A (ja) * | 2001-06-28 | 2003-01-17 | Sanyo Electric Co Ltd | 混成集積回路装置およびその製造方法 |
JP2003060126A (ja) * | 2001-08-17 | 2003-02-28 | Hitachi Ltd | 半導体装置の製造方法 |
JP2003174135A (ja) * | 2001-12-07 | 2003-06-20 | Matsushita Electric Ind Co Ltd | リード付き電子部品 |
JP2004221615A (ja) * | 2004-04-01 | 2004-08-05 | Oki Electric Ind Co Ltd | 半導体装置 |
-
2006
- 2006-03-31 JP JP2006097084A patent/JP5132070B2/ja active Active
Patent Citations (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH02184054A (ja) * | 1989-01-11 | 1990-07-18 | Toshiba Corp | ハイブリッド型樹脂封止半導体装置 |
JPH06291249A (ja) * | 1993-03-31 | 1994-10-18 | Toppan Printing Co Ltd | マルチチップ半導体装置 |
JPH07326708A (ja) * | 1994-06-01 | 1995-12-12 | Toppan Printing Co Ltd | マルチチップモジュール半導体装置 |
JPH0883876A (ja) * | 1994-07-13 | 1996-03-26 | Seiko Epson Corp | 樹脂封止型半導体装置およびその製造方法 |
JP2003017631A (ja) * | 2001-06-28 | 2003-01-17 | Sanyo Electric Co Ltd | 混成集積回路装置およびその製造方法 |
JP2003060126A (ja) * | 2001-08-17 | 2003-02-28 | Hitachi Ltd | 半導体装置の製造方法 |
JP2003174135A (ja) * | 2001-12-07 | 2003-06-20 | Matsushita Electric Ind Co Ltd | リード付き電子部品 |
JP2004221615A (ja) * | 2004-04-01 | 2004-08-05 | Oki Electric Ind Co Ltd | 半導体装置 |
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JP5132070B2 (ja) | 2013-01-30 |
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