JP4676252B2 - 回路装置の製造方法 - Google Patents
回路装置の製造方法 Download PDFInfo
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- JP4676252B2 JP4676252B2 JP2005159163A JP2005159163A JP4676252B2 JP 4676252 B2 JP4676252 B2 JP 4676252B2 JP 2005159163 A JP2005159163 A JP 2005159163A JP 2005159163 A JP2005159163 A JP 2005159163A JP 4676252 B2 JP4676252 B2 JP 4676252B2
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45144—Gold (Au) as principal constituent
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
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- H—ELECTRICITY
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- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/191—Disposition
- H01L2924/19101—Disposition of discrete passive components
- H01L2924/19105—Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/191—Disposition
- H01L2924/19101—Disposition of discrete passive components
- H01L2924/19107—Disposition of discrete passive components off-chip wires
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- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/301—Electrical effects
- H01L2924/30107—Inductance
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- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
Description
本形態では、回路装置の一例として混成集積回路装置10の構造を説明する。
本形態では、図4から図6を参照して、混成集積回路装置の製造方法を説明する。本形態の製造方法では、回路基板11上のパッド13Aとリード25との接続を金属細線17により行う。また、多数個のリード25およびランド45が設けられたリードフレーム40を用いて、混成集積回路装置を製造する。製造工程の途中段階に於いては、ランド45に回路基板11が固着されることで、回路基板11はリードフレーム40に保持されている。
本形態では、図7から図9を参照して、混成集積回路装置の他の製造方法を説明する。本形態の回路装置の製造方法は、基本的には第2の実施の形態と同様である。本形態では、回路基板11の周辺部に対応する部分の吊りリード43を、製造工程の途中にて除去している。更に、吊りリード43を除去した後では、リード25Aにより回路基板11を機械的に支持している。回路基板11の周辺部に位置する吊りリード43が除去されることで、製造される混成集積回路装置に於いて、吊りリード43と回路基板11とのショートを防止することができる。
11 回路基板
12A 第1の絶縁層
12B 第2の絶縁層
13 導電パターン
14 封止樹脂
15 回路素子
15A 半導体素子
15B チップ素子
16 金属基板
17 金属細線
19 メッキ膜
18 固定部
22A 上金型
22B 下金型
23 キャビティ
25 リード
25A リード
Claims (5)
- 吊りリードにより外枠と連結されたランドと、前記ランド上に載置予定の金属からなる回路基板の載置領域に一端が接近した複数個のリードとを有するリードフレームを用意する工程と、
上面全域に設けられた第1の絶縁層の上には、導電パターン、前記導電パターンから成るパッドおよび前記導電パターンと固着された回路素子が設けられ、裏面全域に設けられた第2の絶縁層とを有する前記回路基板を前記ランドに載置する工程と、
前記回路基板のパッドと前記リードとを金属細線により電気的に接続する工程と、
前記ランドの裏面を金型を構成する下金型に当接させ、前記金型を構成する上金型と前記下金型を当接させることにより、前記金型のキャビティティの内部に前記回路基板を収納し、前記金属細線が接続する部分の前記リード、前記回路基板および前記金属細線が覆われるように封止樹脂を形成する工程とを具備し、
前記ランドは前記回路基板よりも小さく、中央部に形成され、
前記ランドにより被覆されない前記回路基板の裏面を前記封止樹脂により被覆し、
前記ランドの裏面を前記封止樹脂から露出させることを特徴とする回路装置の製造方法。 - 前記金属細線を介して、前記回路基板に載置された前記回路素子と前記リードとを接続することを特徴とする請求項1記載の回路装置の製造方法。
- 前記回路基板のパッドと前記リードとを金属細線により電気的に接続し、少なくとも2つの前記リードを前記回路基板と機械的に結合した後に、
前記回路基板の周辺部に対応する領域の前記吊りリードを部分的に除去し、
前記金属細線が接続する部分の前記リード、前記回路基板および前記金属細線が覆われるように封止樹脂をする事を特徴とした請求項1または請求項2に記載の回路装置の製造方法。 - 前記吊りリードを除去した後の工程では、前記回路基板と機械的に結合された前記リードにより、前記回路基板を支持することを特徴とする請求項3記載の回路装置の製造方法。
- 前記回路基板を部分的に突出させて突起部を形成し、
前記リードを前記突起部にかしめることで、前記リードを前記回路基板に機械的に結合することを特徴とする請求項3または請求項4に記載の回路装置の製造方法。
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JP2005159163A JP4676252B2 (ja) | 2005-05-31 | 2005-05-31 | 回路装置の製造方法 |
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JP2006339231A JP2006339231A (ja) | 2006-12-14 |
JP4676252B2 true JP4676252B2 (ja) | 2011-04-27 |
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JP2012199436A (ja) * | 2011-03-22 | 2012-10-18 | Toshiba Corp | 半導体装置及びその製造方法 |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH07302859A (ja) * | 1994-04-29 | 1995-11-14 | Ibiden Co Ltd | 半導体チップ搭載用多層配線基板の製造方法及び半導体チップ搭載装置の製造方法 |
JP2004335493A (ja) * | 2003-03-13 | 2004-11-25 | Denso Corp | 半導体装置の実装構造 |
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Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH07302859A (ja) * | 1994-04-29 | 1995-11-14 | Ibiden Co Ltd | 半導体チップ搭載用多層配線基板の製造方法及び半導体チップ搭載装置の製造方法 |
JP2004335493A (ja) * | 2003-03-13 | 2004-11-25 | Denso Corp | 半導体装置の実装構造 |
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