JP2007265552A - 半導体記憶装置 - Google Patents

半導体記憶装置 Download PDF

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Publication number
JP2007265552A
JP2007265552A JP2006090423A JP2006090423A JP2007265552A JP 2007265552 A JP2007265552 A JP 2007265552A JP 2006090423 A JP2006090423 A JP 2006090423A JP 2006090423 A JP2006090423 A JP 2006090423A JP 2007265552 A JP2007265552 A JP 2007265552A
Authority
JP
Japan
Prior art keywords
potential
data line
mos transistor
channel mos
line pair
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
JP2006090423A
Other languages
English (en)
Japanese (ja)
Other versions
JP2007265552A5 (enExample
Inventor
Kenichi Origasa
憲一 折笠
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP2006090423A priority Critical patent/JP2007265552A/ja
Priority to CN2007100915922A priority patent/CN101047026B/zh
Priority to US11/727,910 priority patent/US7535781B2/en
Publication of JP2007265552A publication Critical patent/JP2007265552A/ja
Publication of JP2007265552A5 publication Critical patent/JP2007265552A5/ja
Withdrawn legal-status Critical Current

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Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/12—Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/4074—Power supply or voltage generation circuits, e.g. bias voltage generators, substrate voltage generators, back-up power, power control circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G11C11/4091—Sense or sense/refresh amplifiers, or associated sense circuitry, e.g. for coupled bit-line precharging, equalising or isolating
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G11C11/4094—Bit-line management or control circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/06—Sense amplifiers; Associated circuits, e.g. timing or triggering circuits
    • G11C7/065—Differential amplifiers of latching type
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/06—Sense amplifiers; Associated circuits, e.g. timing or triggering circuits
    • G11C7/08—Control thereof
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
    • G11C7/1069—I/O lines read out arrangements
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2207/00—Indexing scheme relating to arrangements for writing information into, or reading information out from, a digital store
    • G11C2207/002—Isolation gates, i.e. gates coupling bit lines to the sense amplifier
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2207/00—Indexing scheme relating to arrangements for writing information into, or reading information out from, a digital store
    • G11C2207/06—Sense amplifier related aspects
    • G11C2207/065—Sense amplifier drivers

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Dram (AREA)
  • Static Random-Access Memory (AREA)
JP2006090423A 2006-03-29 2006-03-29 半導体記憶装置 Withdrawn JP2007265552A (ja)

Priority Applications (3)

Application Number Priority Date Filing Date Title
JP2006090423A JP2007265552A (ja) 2006-03-29 2006-03-29 半導体記憶装置
CN2007100915922A CN101047026B (zh) 2006-03-29 2007-03-29 半导体存储器件
US11/727,910 US7535781B2 (en) 2006-03-29 2007-03-29 Semiconductor memory

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2006090423A JP2007265552A (ja) 2006-03-29 2006-03-29 半導体記憶装置

Publications (2)

Publication Number Publication Date
JP2007265552A true JP2007265552A (ja) 2007-10-11
JP2007265552A5 JP2007265552A5 (enExample) 2009-04-23

Family

ID=38558688

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2006090423A Withdrawn JP2007265552A (ja) 2006-03-29 2006-03-29 半導体記憶装置

Country Status (3)

Country Link
US (1) US7535781B2 (enExample)
JP (1) JP2007265552A (enExample)
CN (1) CN101047026B (enExample)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8947963B2 (en) * 2013-01-11 2015-02-03 Apple Inc. Variable pre-charge levels for improved cell stability
US9640231B1 (en) * 2016-02-03 2017-05-02 Qualcomm Incorporated Shared sense amplifier
US10177760B1 (en) * 2017-06-28 2019-01-08 Arm Limited Circuit with impedance elements connected to sources and drains of pMOSFET headers
US10720193B2 (en) 2018-09-28 2020-07-21 Apple Inc. Technique to lower switching power of bit-lines by adiabatic charging of SRAM memories
CN113760173B (zh) * 2020-06-05 2025-05-02 长鑫存储技术(上海)有限公司 读写转换电路以及存储器
CN116230053B (zh) * 2023-03-01 2023-12-22 芯立嘉集成电路(杭州)有限公司 一种四晶体管静态随机存取存储器和存取方法

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4780850A (en) * 1986-10-31 1988-10-25 Mitsubishi Denki Kabushiki Kaisha CMOS dynamic random access memory
JPS6425394A (en) * 1987-07-21 1989-01-27 Mitsubishi Electric Corp Nonvolatile semiconductor memory device
US5999469A (en) * 1998-03-04 1999-12-07 Lsi Logic Corporation Sense time reduction using midlevel precharge
US6005793A (en) * 1998-03-31 1999-12-21 Tran; Thang Minh Multiple-bit random-access memory array
JP2000036190A (ja) * 1998-07-17 2000-02-02 Toshiba Corp 半導体装置
KR100402243B1 (ko) 2001-09-24 2003-10-17 주식회사 하이닉스반도체 개선된 주변회로를 갖는 반도체 기억장치
US6751152B2 (en) 2001-10-31 2004-06-15 International Business Machines Corporation Method and configuration to allow a lower wordline boosted voltage operation while increasing a sensing signal with access transistor threshold voltage
US7099215B1 (en) 2005-02-11 2006-08-29 North Carolina State University Systems, methods and devices for providing variable-latency write operations in memory devices

Also Published As

Publication number Publication date
US20070230262A1 (en) 2007-10-04
US7535781B2 (en) 2009-05-19
CN101047026B (zh) 2011-12-07
CN101047026A (zh) 2007-10-03

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