JP2007265552A5 - - Google Patents

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Publication number
JP2007265552A5
JP2007265552A5 JP2006090423A JP2006090423A JP2007265552A5 JP 2007265552 A5 JP2007265552 A5 JP 2007265552A5 JP 2006090423 A JP2006090423 A JP 2006090423A JP 2006090423 A JP2006090423 A JP 2006090423A JP 2007265552 A5 JP2007265552 A5 JP 2007265552A5
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JP
Japan
Prior art keywords
potential
data line
mos transistor
channel mos
line pair
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
JP2006090423A
Other languages
English (en)
Japanese (ja)
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JP2007265552A (ja
Filing date
Publication date
Application filed filed Critical
Priority to JP2006090423A priority Critical patent/JP2007265552A/ja
Priority claimed from JP2006090423A external-priority patent/JP2007265552A/ja
Priority to CN2007100915922A priority patent/CN101047026B/zh
Priority to US11/727,910 priority patent/US7535781B2/en
Publication of JP2007265552A publication Critical patent/JP2007265552A/ja
Publication of JP2007265552A5 publication Critical patent/JP2007265552A5/ja
Withdrawn legal-status Critical Current

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JP2006090423A 2006-03-29 2006-03-29 半導体記憶装置 Withdrawn JP2007265552A (ja)

Priority Applications (3)

Application Number Priority Date Filing Date Title
JP2006090423A JP2007265552A (ja) 2006-03-29 2006-03-29 半導体記憶装置
CN2007100915922A CN101047026B (zh) 2006-03-29 2007-03-29 半导体存储器件
US11/727,910 US7535781B2 (en) 2006-03-29 2007-03-29 Semiconductor memory

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2006090423A JP2007265552A (ja) 2006-03-29 2006-03-29 半導体記憶装置

Publications (2)

Publication Number Publication Date
JP2007265552A JP2007265552A (ja) 2007-10-11
JP2007265552A5 true JP2007265552A5 (enExample) 2009-04-23

Family

ID=38558688

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2006090423A Withdrawn JP2007265552A (ja) 2006-03-29 2006-03-29 半導体記憶装置

Country Status (3)

Country Link
US (1) US7535781B2 (enExample)
JP (1) JP2007265552A (enExample)
CN (1) CN101047026B (enExample)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8947963B2 (en) * 2013-01-11 2015-02-03 Apple Inc. Variable pre-charge levels for improved cell stability
US9640231B1 (en) * 2016-02-03 2017-05-02 Qualcomm Incorporated Shared sense amplifier
US10177760B1 (en) * 2017-06-28 2019-01-08 Arm Limited Circuit with impedance elements connected to sources and drains of pMOSFET headers
US10720193B2 (en) 2018-09-28 2020-07-21 Apple Inc. Technique to lower switching power of bit-lines by adiabatic charging of SRAM memories
CN113760173B (zh) * 2020-06-05 2025-05-02 长鑫存储技术(上海)有限公司 读写转换电路以及存储器
CN116230053B (zh) * 2023-03-01 2023-12-22 芯立嘉集成电路(杭州)有限公司 一种四晶体管静态随机存取存储器和存取方法

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4780850A (en) * 1986-10-31 1988-10-25 Mitsubishi Denki Kabushiki Kaisha CMOS dynamic random access memory
JPS6425394A (en) * 1987-07-21 1989-01-27 Mitsubishi Electric Corp Nonvolatile semiconductor memory device
US5999469A (en) * 1998-03-04 1999-12-07 Lsi Logic Corporation Sense time reduction using midlevel precharge
US6005793A (en) * 1998-03-31 1999-12-21 Tran; Thang Minh Multiple-bit random-access memory array
JP2000036190A (ja) * 1998-07-17 2000-02-02 Toshiba Corp 半導体装置
KR100402243B1 (ko) 2001-09-24 2003-10-17 주식회사 하이닉스반도체 개선된 주변회로를 갖는 반도체 기억장치
US6751152B2 (en) 2001-10-31 2004-06-15 International Business Machines Corporation Method and configuration to allow a lower wordline boosted voltage operation while increasing a sensing signal with access transistor threshold voltage
US7099215B1 (en) 2005-02-11 2006-08-29 North Carolina State University Systems, methods and devices for providing variable-latency write operations in memory devices

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