JP2007200291A - 半導体装置およびその作製方法 - Google Patents
半導体装置およびその作製方法 Download PDFInfo
- Publication number
- JP2007200291A JP2007200291A JP2006345314A JP2006345314A JP2007200291A JP 2007200291 A JP2007200291 A JP 2007200291A JP 2006345314 A JP2006345314 A JP 2006345314A JP 2006345314 A JP2006345314 A JP 2006345314A JP 2007200291 A JP2007200291 A JP 2007200291A
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- Prior art keywords
- film
- insulating film
- semiconductor
- semiconductor film
- gate insulating
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Images
Classifications
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- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
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- H01L27/1255—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs integrated with passive devices, e.g. auxiliary capacitors
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Abstract
【解決手段】アンテナと、アンテナとに電気的に接続された電源生成回路と、電源生成回路に電気的に接続されたICチップ回路および表示素子と、電源生成回路に設けられた第1のTFT、ICチップ回路に設けられた第2のTFTおよび表示素子に設けられた第3のTFTと、第1のTFT、第2のTFTおよび第3のTFTを覆って設けられた絶縁膜と、絶縁膜上に形成された第1のソース電極またはドレイン電極と、第2のソース電極またはドレイン電極および第3のソース電極またはドレイン電極と、第3のソースまたはドレイン電極と電気的に接続された画素電極とを有し、第1のソース電極またはドレイン電極をアンテナと電気的に接続する。
【選択図】図1
Description
本実施の形態では、本発明の表示機能付きの非接触ICカードの一例に関して図面を参照して説明する。
本実施の形態では、上記実施の形態で示した表示機能付き半導体装置の作製方法の一例に関して図面を参照して説明する。
(実施の形態3)
本実施の形態では、表示機能付き半導体装置の作製方法に関して図面を参照して説明する。
以下に、本発明の表示機能付きであって無線で認証可能な半導体装置の応用例を図面に基づいて説明する。具体的には、電波発信源システムの一例について図13を参照して説明する。
2 表示部
3 ゲートドライバ
4 ソースドライバ
5 コントローラ
6 アンテナ
7 電源生成回路
8 集積回路
9 表示素子
11 検波容量
12 整流回路
13 保持容量
14 定電圧回路
15 信号分離回路
16 表示用電源回路
19a システム
19b アンテナ
20 実線
21 点線
101 基板
102 絶縁膜
103 半導体膜
104 ゲート絶縁膜
105 第1の導電膜
106 第2の導電膜
107 レジスト
108 第1のゲート電極
109 レジスト
110 第2のゲート電極
111 レジスト
112 第3のゲート電極
113 レジスト
120 低濃度の不純物イオン
130 低濃度不純物領域
131 低濃度不純物領域
132 高濃度不純物領域
133 高濃度不純物領域
134 チャネル形成領域
135 層間絶縁膜
136 配線
137 配線
138 不純物領域
139 不純物領域
140 不純物イオン
200 半導体膜
201 半導体膜
202 半導体膜
203 ゲート絶縁膜
204 ゲート絶縁膜
205 下地膜
206 半導体膜
207 ゲート絶縁膜
208 ゲート絶縁膜
209 ゲート絶縁膜
501 メインサーバー
502 店舗サーバー
503 R/W
504 R/W
505 R/W
506 Webサーバー
507 ICカード
508 ICカード
509 ICカード
510 個人用PC
701 基板
702 絶縁膜
703 半導体膜
704a 半導体膜
704b 半導体膜
704c 半導体膜
704d 半導体膜
705a ゲート絶縁膜
705b ゲート絶縁膜
706a ゲート電極
706b ゲート電極
707 絶縁膜
708 絶縁膜
709 導電膜
710 絶縁膜
711a 導電膜
711b 導電膜
712 導電膜
713 導電膜
714 絶縁膜
715 液晶材料
716 導電膜
717 対向基板
720a 薄膜トランジスタ
720b 薄膜トランジスタ
720c 薄膜トランジスタ
720d 薄膜トランジスタ
721a 電源生成回路が設けられる領域
721b 集積回路が設けられる領域
721c 表示部が設けられる領域
724 剥離層
726 基板
728 導電性粒子
731 導電膜
733 導電膜
732 マイクロカプセル
736 導電膜
737 導電膜
738 基板
Claims (11)
- アンテナとして機能する導電膜と、
前記アンテナとして機能する導電膜に電気的に接続された電源生成回路と、
前記電源生成回路に設けられた定電圧回路及び表示用電源回路と、
前記定電圧回路から第1の電圧が供給される集積回路と、前記表示用電源回路から第2の電圧が供給される表示素子と、
前記電源生成回路を構成する第1の薄膜トランジスタと、
前記集積回路を構成する第2の薄膜トランジスタと、
前記表示素子を構成する第3の薄膜トランジスタと、
前記第1の薄膜トランジスタ、前記第2の薄膜トランジスタおよび前記第3の薄膜トランジスタを覆って設けられた絶縁膜と、
前記絶縁膜上に形成された、前記第1の薄膜トランジスタのソース電極およびドレイン電極と、前記第2の薄膜トランジスタのソース電極およびドレイン電極と、前記第3の薄膜トランジスタのソース電極およびドレイン電極と、
前記第3の薄膜トランジスタのソース電極またはドレイン電極と電気的に接続された画素電極とを有し、
前記第1の薄膜トランジスタのソース電極またはドレイン電極は、前記アンテナとして機能する導電膜に電気的に接続されていることを特徴とする半導体装置。 - 請求項1において、
前記第1の薄膜トランジスタは、第1の半導体膜と、前記第1の半導体膜上に設けられた第1のゲート絶縁膜と、前記第1のゲート絶縁膜上に設けられた第1のゲート電極を有し、
前記第2の薄膜トランジスタは、第2の半導体膜と、前記第2の半導体膜上に設けられた第2のゲート絶縁膜と、前記第2のゲート絶縁膜上に設けられた第2のゲート電極を有し、
前記第3の薄膜トランジスタは、第3の半導体膜と、前記第3の半導体膜上に設けられた第3のゲート絶縁膜と、前記第3のゲート絶縁膜上に設けられた第3のゲート電極を有し、
前記第3のゲート絶縁膜は、前記第1のゲート絶縁膜及び前記第2のゲート絶縁膜と厚さが異なることを特徴とする半導体装置。 - 請求項1または請求項2において、
前記第1の薄膜トランジスタ、前記第2の薄膜トランジスタ及び前記第3の薄膜トランジスタは、同一の基板上に設けられていることを特徴とする半導体装置。 - 請求項3において、
前記基板は、可撓性を有する基板であることを特徴とする半導体装置。 - 請求項1乃至請求項4のいずれか一項において、
前記第1の電圧は前記第2の電圧より低いことを特徴とする半導体装置。 - 請求項1乃至請求項5のいずれか一項において、
前記表示素子は、液晶素子が設けられた表示部を有することを特徴とする半導体装置。 - 請求項1乃至請求項5のいずれか一項において、
前記表示素子は、発光素子が設けられた表示部を有することを特徴とする半導体装置。 - 請求項1乃至請求項5のいずれか一項において、
前記表示素子は、電気泳動素子が設けられた表示部を有することを特徴とする半導体装置。 - 基板上に半導体膜を形成し、
前記半導体膜をエッチングして、第1の半導体膜および第2の半導体膜を形成し、
前記第1の半導体膜および前記第2の半導体膜を覆うように第1のゲート絶縁膜を形成し、
前記第2の半導体膜上に形成された第1のゲート絶縁膜を除去した後、
前記第2の半導体膜をエッチングして第3の半導体膜を形成し、
前記第1のゲート絶縁膜と前記第3の半導体膜とを覆うように第2のゲート絶縁膜を形成し、
前記第1の半導体膜上に前記第1のゲート絶縁膜および前記第2のゲート絶縁膜を介して第1のゲート電極を形成し、
前記第3の半導体膜上に前記第2のゲート絶縁膜を介して第2のゲート電極を形成し、
前記第1の半導体膜および前記第3の半導体膜に不純物元素を導入してソース領域とドレイン領域とを形成し、
前記第1のゲート電極および前記第2のゲート電極を覆うように層間絶縁膜を形成し、
前記層間絶縁膜上に、前記第1の半導体膜のソース領域またはドレイン領域と電気的に接続する第1の導電膜と、前記第3の半導体膜のソース領域またはドレイン領域と電気的に接続する第2の導電膜を形成し、
前記第2の導電膜と電気的に接続するアンテナとして機能する導電膜を形成することを特徴とする半導体装置の作製方法。 - 基板上に半導体膜を形成し、
前記半導体膜をエッチングして、第1の半導体膜および第2の半導体膜を形成し、
前記第1の半導体膜および前記第2の半導体膜を覆うように第1のゲート絶縁膜を形成し、
前記第2の半導体膜上に形成された第1のゲート絶縁膜を除去した後、
前記第2の半導体膜をエッチングして第3の半導体膜を形成し、
前記第1のゲート絶縁膜と前記第3の半導体膜とを覆うように第2のゲート絶縁膜を形成し、
前記第1の半導体膜上に前記第1のゲート絶縁膜および前記第2のゲート絶縁膜を介して第1のゲート電極を形成し、
前記第3の半導体膜上に前記第2のゲート絶縁膜を介して第2のゲート電極を形成し、
前記第1の半導体膜および前記第3の半導体膜に不純物元素を導入してソース領域とドレイン領域とを形成し、
前記第1のゲート電極および前記第2のゲート電極を覆うように層間絶縁膜を形成し、
前記層間絶縁膜上に、前記第1の半導体膜のソース領域またはドレイン領域と電気的に接続する第1の導電膜と、前記第3の半導体膜のソース領域またはドレイン領域と電気的に接続する第2の導電膜を形成し、
前記第1の導電膜と電気的に接続する画素電極を形成し、
前記第2の導電膜と電気的に接続するアンテナとして機能する導電膜を形成することを特徴とする半導体装置の作製方法。 - 基板上に半導体膜を形成し、
前記半導体膜を覆うようにゲート絶縁膜を形成し、
前記半導体膜上に前記絶縁膜を介してゲート電極を形成し、
前記半導体膜に不純物元素を導入してソース領域とドレイン領域とを形成し、
前記ゲート電極を覆うように層間絶縁膜を形成し、
前記層間絶縁膜上に、画素電極として機能する第1の導電膜と前記半導体膜のソース領域またはドレイン領域と電気的に接続する第2の導電膜を形成し、
前記第2の導電膜と電気的に接続するアンテナとして機能する導電膜を形成し、
前記第1の導電膜と対向する対向電極を設け、
前記第1の導電膜と前記対向電極の間にマイクロカプセルを形成することを特徴とする半導体装置の作製方法。
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US8476632B2 (en) | 2013-07-02 |
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