JP2007134458A5 - - Google Patents
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- Publication number
- JP2007134458A5 JP2007134458A5 JP2005325090A JP2005325090A JP2007134458A5 JP 2007134458 A5 JP2007134458 A5 JP 2007134458A5 JP 2005325090 A JP2005325090 A JP 2005325090A JP 2005325090 A JP2005325090 A JP 2005325090A JP 2007134458 A5 JP2007134458 A5 JP 2007134458A5
- Authority
- JP
- Japan
- Prior art keywords
- pattern
- forming
- connection portion
- wiring
- semiconductor chip
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000000034 method Methods 0.000 claims 10
- 239000004065 semiconductor Substances 0.000 claims 10
- 238000009713 electroplating Methods 0.000 claims 9
- 238000004519 manufacturing process Methods 0.000 claims 6
- 238000005530 etching Methods 0.000 claims 5
- 239000000463 material Substances 0.000 claims 2
Priority Applications (4)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2005325090A JP4718305B2 (ja) | 2005-11-09 | 2005-11-09 | 配線基板の製造方法および半導体装置の製造方法 |
| KR1020060104331A KR101195886B1 (ko) | 2005-11-09 | 2006-10-26 | 배선 기판의 제조 방법 및 반도체 장치의 제조 방법 |
| US11/594,074 US20070111387A1 (en) | 2005-11-09 | 2006-11-08 | Manufacturing method of wiring board and manufacturing method of semiconductor device |
| TW095141468A TW200731436A (en) | 2005-11-09 | 2006-11-09 | Manufacturing method of wiring board and manufacturing method of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2005325090A JP4718305B2 (ja) | 2005-11-09 | 2005-11-09 | 配線基板の製造方法および半導体装置の製造方法 |
Publications (3)
| Publication Number | Publication Date |
|---|---|
| JP2007134458A JP2007134458A (ja) | 2007-05-31 |
| JP2007134458A5 true JP2007134458A5 (enExample) | 2008-08-07 |
| JP4718305B2 JP4718305B2 (ja) | 2011-07-06 |
Family
ID=38041418
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2005325090A Expired - Fee Related JP4718305B2 (ja) | 2005-11-09 | 2005-11-09 | 配線基板の製造方法および半導体装置の製造方法 |
Country Status (4)
| Country | Link |
|---|---|
| US (1) | US20070111387A1 (enExample) |
| JP (1) | JP4718305B2 (enExample) |
| KR (1) | KR101195886B1 (enExample) |
| TW (1) | TW200731436A (enExample) |
Families Citing this family (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TWI434405B (zh) * | 2011-06-07 | 2014-04-11 | 國立交通大學 | 具有積體電路與發光二極體之異質整合結構及其製作方法 |
| US20150195912A1 (en) * | 2014-01-08 | 2015-07-09 | Zhuhai Advanced Chip Carriers & Electronic Substrate Solutions Technologies Co. Ltd. | Substrates With Ultra Fine Pitch Flip Chip Bumps |
| US9642261B2 (en) * | 2014-01-24 | 2017-05-02 | Zhuhai Advanced Chip Carriers & Electronic Substrate Solutions Technologies Co. Ltd. | Composite electronic structure with partially exposed and protruding copper termination posts |
| JP6502814B2 (ja) * | 2015-09-25 | 2019-04-17 | 京セラ株式会社 | 指紋センサー用配線基板 |
| JP2017063163A (ja) * | 2015-09-25 | 2017-03-30 | 京セラ株式会社 | 指紋センサー用配線基板 |
Family Cites Families (18)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0245996A (ja) * | 1988-08-05 | 1990-02-15 | Nec Corp | 混成集積回路の製造方法 |
| JPH02162734A (ja) * | 1988-12-16 | 1990-06-22 | Fujitsu Ltd | 半導体装置の製造方法 |
| JPH03129831A (ja) * | 1989-10-16 | 1991-06-03 | Nec Corp | 半導体装置の製造方法 |
| JPH03139851A (ja) * | 1989-10-25 | 1991-06-14 | Aoi Denshi Kk | 半導体装置 |
| JP3003394B2 (ja) * | 1992-06-24 | 2000-01-24 | 松下電器産業株式会社 | 突起電極の製造方法 |
| JPH0964493A (ja) * | 1995-08-29 | 1997-03-07 | Nippon Mektron Ltd | 回路基板の配線構造及びその形成法 |
| JP3405640B2 (ja) * | 1996-08-09 | 2003-05-12 | 松下電工株式会社 | 独立回路へのメッキ方法 |
| JP2002009203A (ja) * | 2000-06-23 | 2002-01-11 | Dainippon Printing Co Ltd | 配線形成方法と配線基板 |
| JP4480111B2 (ja) * | 2000-08-02 | 2010-06-16 | 大日本印刷株式会社 | 配線形成方法および配線部材 |
| US6890829B2 (en) * | 2000-10-24 | 2005-05-10 | Intel Corporation | Fabrication of on-package and on-chip structure using build-up layer process |
| JP2002141437A (ja) * | 2000-11-06 | 2002-05-17 | Dainippon Printing Co Ltd | Ｃｓｐタイプの半導体装置及びその作製方法 |
| JP2002170845A (ja) * | 2000-12-04 | 2002-06-14 | Sumitomo Bakelite Co Ltd | 半導体装置の製造方法および半導体装置 |
| JP2002246744A (ja) * | 2001-02-20 | 2002-08-30 | Nec Corp | 導体形成方法およびこれを用いた多層配線基板製造方法 |
| US6660633B1 (en) * | 2002-02-26 | 2003-12-09 | Advanced Micro Devices, Inc. | Method of reducing electromigration in a copper line by electroplating an interim copper-zinc alloy thin film on a copper surface and a semiconductor device thereby formed |
| DE10355953B4 (de) * | 2003-11-29 | 2005-10-20 | Infineon Technologies Ag | Verfahren zum Galvanisieren und Kontaktvorsprungsanordnung |
| KR100597993B1 (ko) * | 2004-04-08 | 2006-07-10 | 주식회사 네패스 | 반도체 패키지용 범프, 그 범프를 적용한 반도체 패키지 및 제조방법 |
| JP4441328B2 (ja) * | 2004-05-25 | 2010-03-31 | 株式会社ルネサステクノロジ | 半導体装置及びその製造方法 |
| US7179738B2 (en) * | 2004-06-17 | 2007-02-20 | Texas Instruments Incorporated | Semiconductor assembly having substrate with electroplated contact pads |
-
2005
- 2005-11-09 JP JP2005325090A patent/JP4718305B2/ja not_active Expired - Fee Related
-
2006
- 2006-10-26 KR KR1020060104331A patent/KR101195886B1/ko not_active Expired - Fee Related
- 2006-11-08 US US11/594,074 patent/US20070111387A1/en not_active Abandoned
- 2006-11-09 TW TW095141468A patent/TW200731436A/zh unknown