JP2007103947A - 薄膜トランジスタおよび電子デバイスを製造するための方法 - Google Patents
薄膜トランジスタおよび電子デバイスを製造するための方法 Download PDFInfo
- Publication number
- JP2007103947A JP2007103947A JP2006272643A JP2006272643A JP2007103947A JP 2007103947 A JP2007103947 A JP 2007103947A JP 2006272643 A JP2006272643 A JP 2006272643A JP 2006272643 A JP2006272643 A JP 2006272643A JP 2007103947 A JP2007103947 A JP 2007103947A
- Authority
- JP
- Japan
- Prior art keywords
- electrode
- layer
- forming
- film
- insulator
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000000034 method Methods 0.000 title claims abstract description 89
- 238000004519 manufacturing process Methods 0.000 title claims description 35
- 239000010409 thin film Substances 0.000 title claims description 9
- 239000012212 insulator Substances 0.000 claims abstract description 34
- 239000000758 substrate Substances 0.000 claims abstract description 28
- 238000007639 printing Methods 0.000 claims abstract description 15
- 238000005530 etching Methods 0.000 claims abstract description 8
- 238000007687 exposure technique Methods 0.000 claims abstract description 4
- 239000004065 semiconductor Substances 0.000 claims description 28
- 239000010408 film Substances 0.000 claims description 23
- 238000007641 inkjet printing Methods 0.000 claims description 16
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 claims description 15
- 229910052709 silver Inorganic materials 0.000 claims description 13
- 239000004332 silver Substances 0.000 claims description 13
- 229920001609 Poly(3,4-ethylenedioxythiophene) Polymers 0.000 claims description 6
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims description 6
- 229920000172 poly(styrenesulfonic acid) Polymers 0.000 claims description 6
- 239000000725 suspension Substances 0.000 claims description 6
- 229940005642 polystyrene sulfonic acid Drugs 0.000 claims description 5
- 229910052737 gold Inorganic materials 0.000 claims description 4
- 239000010931 gold Substances 0.000 claims description 4
- 239000000084 colloidal system Substances 0.000 claims description 3
- 229910052751 metal Inorganic materials 0.000 claims description 2
- 239000002184 metal Substances 0.000 claims description 2
- 239000012780 transparent material Substances 0.000 claims description 2
- 229920002120 photoresistant polymer Polymers 0.000 description 33
- 239000000463 material Substances 0.000 description 13
- 150000001875 compounds Chemical class 0.000 description 8
- 238000000206 photolithography Methods 0.000 description 7
- 238000011161 development Methods 0.000 description 6
- 229910010272 inorganic material Inorganic materials 0.000 description 5
- 239000011147 inorganic material Substances 0.000 description 5
- 229920003229 poly(methyl methacrylate) Polymers 0.000 description 5
- -1 polymethylsiloxane Polymers 0.000 description 5
- MWPLVEDNUUSJAV-UHFFFAOYSA-N anthracene Chemical compound C1=CC=CC2=CC3=CC=CC=C3C=C21 MWPLVEDNUUSJAV-UHFFFAOYSA-N 0.000 description 4
- 238000001020 plasma etching Methods 0.000 description 4
- 229920000301 poly(3-hexylthiophene-2,5-diyl) polymer Polymers 0.000 description 4
- 229920000642 polymer Polymers 0.000 description 4
- 239000004926 polymethyl methacrylate Substances 0.000 description 4
- 125000006850 spacer group Chemical group 0.000 description 4
- 238000002508 contact lithography Methods 0.000 description 3
- 239000011521 glass Substances 0.000 description 3
- 238000012986 modification Methods 0.000 description 3
- 230000004048 modification Effects 0.000 description 3
- 239000011368 organic material Substances 0.000 description 3
- 238000000059 patterning Methods 0.000 description 3
- 238000007650 screen-printing Methods 0.000 description 3
- 150000003384 small molecules Chemical class 0.000 description 3
- 238000004528 spin coating Methods 0.000 description 3
- DZUNDTRLGXGTGU-UHFFFAOYSA-N 2-(3-dodecylthiophen-2-yl)-5-[5-(3-dodecylthiophen-2-yl)thiophen-2-yl]thiophene Chemical compound C1=CSC(C=2SC(=CC=2)C=2SC(=CC=2)C2=C(C=CS2)CCCCCCCCCCCC)=C1CCCCCCCCCCCC DZUNDTRLGXGTGU-UHFFFAOYSA-N 0.000 description 2
- YTPLMLYBLZKORZ-UHFFFAOYSA-N Thiophene Chemical compound C=1C=CSC=1 YTPLMLYBLZKORZ-UHFFFAOYSA-N 0.000 description 2
- UMIVXZPTRXBADB-UHFFFAOYSA-N benzocyclobutene Chemical compound C1=CC=C2CCC2=C1 UMIVXZPTRXBADB-UHFFFAOYSA-N 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 239000012528 membrane Substances 0.000 description 2
- 238000007645 offset printing Methods 0.000 description 2
- SLIUAWYAILUBJU-UHFFFAOYSA-N pentacene Chemical compound C1=CC=CC2=CC3=CC4=CC5=CC=CC=C5C=C4C=C3C=C21 SLIUAWYAILUBJU-UHFFFAOYSA-N 0.000 description 2
- 238000002207 thermal evaporation Methods 0.000 description 2
- GKWLILHTTGWKLQ-UHFFFAOYSA-N 2,3-dihydrothieno[3,4-b][1,4]dioxine Chemical compound O1CCOC2=CSC=C21 GKWLILHTTGWKLQ-UHFFFAOYSA-N 0.000 description 1
- 229920001665 Poly-4-vinylphenol Polymers 0.000 description 1
- 230000002411 adverse Effects 0.000 description 1
- 238000000137 annealing Methods 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 229920001940 conductive polymer Polymers 0.000 description 1
- 230000008602 contraction Effects 0.000 description 1
- 238000005520 cutting process Methods 0.000 description 1
- 239000003989 dielectric material Substances 0.000 description 1
- 238000003618 dip coating Methods 0.000 description 1
- 238000007606 doctor blade method Methods 0.000 description 1
- 238000007772 electroless plating Methods 0.000 description 1
- 238000004049 embossing Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- 230000008018 melting Effects 0.000 description 1
- 238000002844 melting Methods 0.000 description 1
- 239000002070 nanowire Substances 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 238000007649 pad printing Methods 0.000 description 1
- 239000002861 polymer material Substances 0.000 description 1
- 239000011116 polymethylpentene Substances 0.000 description 1
- 229920000306 polymethylpentene Polymers 0.000 description 1
- 229920000123 polythiophene Polymers 0.000 description 1
- 238000009751 slip forming Methods 0.000 description 1
- 239000002904 solvent Substances 0.000 description 1
- 238000005507 spraying Methods 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 229930192474 thiophene Natural products 0.000 description 1
- 238000012546 transfer Methods 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823487—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of vertical transistor structures, i.e. with channel vertical to the substrate surface
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7827—Vertical transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78642—Vertical transistors
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K10/00—Organic devices specially adapted for rectifying, amplifying, oscillating or switching; Organic capacitors or resistors having potential barriers
- H10K10/40—Organic transistors
- H10K10/46—Field-effect transistors, e.g. organic thin-film transistors [OTFT]
- H10K10/462—Insulated gate field-effect transistors [IGFETs]
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K10/00—Organic devices specially adapted for rectifying, amplifying, oscillating or switching; Organic capacitors or resistors having potential barriers
- H10K10/40—Organic transistors
- H10K10/46—Field-effect transistors, e.g. organic thin-film transistors [OTFT]
- H10K10/462—Insulated gate field-effect transistors [IGFETs]
- H10K10/481—Insulated gate field-effect transistors [IGFETs] characterised by the gate conductors
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Ceramic Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Thin Film Transistor (AREA)
- Electrodes Of Semiconductors (AREA)
Abstract
【解決手段】絶縁体の第1の層を基板上に形成すること、印刷技法を用いて絶縁体上に第1の膜を形成すること、および、写真露光技法またはエッチング技法を用いて、第1の膜をマスクと使用して絶縁体の所定の部分を除去することを含む。
【選択図】図1
Description
本発明の一態様によれば、市販の電子デバイスおよび回路を製造するための方法を提供する。本発明に係る方法は、印刷とセルフアライン式写真露光またはエッチングとを組み合わせて、両技法の利点を活用する。本発明に係る方法において、第1の膜は、印刷技法に起因して画像度が比較的低くなっているが、このように低画像度であることが結果として得られるデバイスに対して及ぼす悪影響は、続けてこの第1の膜をマスクとして使用することによって最小限に押さえられる。その結果、本発明によって、ロール・トゥ・ロール工程を用いて、以前可能であったよりも大規模に高解像度エレクトロニクスを製造することができるようになる。
Claims (17)
- 電子デバイスを製造するための方法であって、
絶縁体を含む第1の層を基板上に形成する第1の工程と、
前記第1の層上に印刷技法を用いて第1の膜を形成する第2の工程と、
写真露光技法またはエッチング技法を用いて、前記第1の膜をマスクとして使用することにより前記第1の層の一部を除去する第3の工程と、を含むことを特徴とする、方法。 - 前記第1の工程を行う前に第2の膜を前記基板上に形成する第4の工程をさらに含むことを特徴とする請求項1に記載の方法。
- 前記第4の工程は、透明材料を形成することを含むことを特徴とする請求項2に記載の方法。
- 前記第1の膜は、前記第2の膜に対して偏心されていることを特徴とする請求項2または3に記載の方法。
- 前記第4の工程は、第1の電極を形成する工程を含み、
前記第2の工程は、第2の電極を形成する工程を含むことを特徴とする請求項2ないし4のいずれか1項に記載の方法。 - 半導体層を、前記第1の電極と前記第1の層と前記第2の電極との上に形成する第5の工程をさらに含むことを特徴とする請求項5に記載の方法。
- 誘電層を前記半導体層上に形成する第6の工程をさらに含むことを特徴とする請求項6に記載の方法。
- 前記第1の電極と前記第2の電極との間の間隙の少なくとも一部分にわたって延在する第3の電極を形成する第7の工程をさらに含むことを特徴とする請求項7に記載の方法。
- 前記第3の電極はインクジェット印刷によって形成されることを特徴とする請求項8に記載の方法。
- 前記第7の工程は、ポリ(3,4エチレンジオキシチオフェン)−ポリスチレンスルホン酸(PEDOT−PSS)または金属コロイド懸濁液を形成することを含むことを特徴とする請求項8または9に記載の方法。
- 前記第7の工程は、銀または金から成るコロイド懸濁液を形成することを含むことを特徴とする請求項9に記載の方法。
- 前記第4の工程の前に絶縁体を含む第2の層を前記基板上に形成する第8の工程をさらに含み、
前記第3の工程において、前記第2の膜の一部を除去することを含むことを特徴とする請求項2ないし11のいずれか1項に記載の方法。 - 前記第2の工程は、銀コロイドインクまたは金コロイドインクを印刷することを含むことを特徴とする請求項1ないし12のいずれか1項に記載の方法。
- 前記第1の層の膜厚は1μm以下であることを特徴とする請求項1ないし13のいずれか1項に記載の方法。
- 薄膜トランジスタを製造するための方法であって、請求項1ないし14のいずれか1項に記載の方法を含むことを特徴とする方法。
- 垂直方向短チャネル薄膜トランジスタであって、
基板と、
前記基板上に形成された第1の電極と、
前記第1の電極の所定の部分の上に形成された絶縁体の第1の層と、
前記絶縁体の第1の層の上に形成された第2の電極と、
前記第1の電極および前記第2の電極の間にチャネルを形成する半導体層と、
前記半導体層上に形成された誘電層と、
前記誘電層上に形成されるとともに前記第1の電極および前記第2の電極の間の前記チャネルの少なくとも一部分にわたって延在するゲート電極と、を備えることを特徴とするトランジスタ。 - 前記第1の電極は透明であり、前記第2の電極は不透明であることを特徴とする請求項16に記載のトランジスタ。
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
GB0520350.0 | 2005-10-06 | ||
GB0520350A GB2432714A (en) | 2005-10-06 | 2005-10-06 | Thin film transistor and method for fabricating an electronic device |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2007103947A true JP2007103947A (ja) | 2007-04-19 |
JP4730275B2 JP4730275B2 (ja) | 2011-07-20 |
Family
ID=35429932
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2006272643A Expired - Fee Related JP4730275B2 (ja) | 2005-10-06 | 2006-10-04 | 薄膜トランジスタおよび薄膜トランジスタの製造方法 |
Country Status (3)
Country | Link |
---|---|
US (1) | US20070082438A1 (ja) |
JP (1) | JP4730275B2 (ja) |
GB (1) | GB2432714A (ja) |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2009535805A (ja) * | 2006-04-27 | 2009-10-01 | オーガニックアイディー インコーポレイテッド | 自己整合型高性能有機fetの構造及び製造 |
US8463116B2 (en) | 2008-07-01 | 2013-06-11 | Tap Development Limited Liability Company | Systems for curing deposited material using feedback control |
JP2016092058A (ja) * | 2014-10-30 | 2016-05-23 | 株式会社ジャパンディスプレイ | 半導体装置 |
Families Citing this family (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7459400B2 (en) * | 2005-07-18 | 2008-12-02 | Palo Alto Research Center Incorporated | Patterned structures fabricated by printing mask over lift-off pattern |
US20090004368A1 (en) * | 2007-06-29 | 2009-01-01 | Weyerhaeuser Co. | Systems and methods for curing a deposited layer on a substrate |
EP2924754B1 (en) * | 2014-03-28 | 2021-10-20 | Novaled GmbH | Method for producing an organic transistor and organic transistor |
GB2552488A (en) | 2016-07-25 | 2018-01-31 | Saralon Gmbh | Field-effect transistor and method for the production thereof |
KR20200115753A (ko) | 2019-03-25 | 2020-10-08 | 삼성디스플레이 주식회사 | 박막 트랜지스터 기판, 표시 장치 및 이의 제조 방법 |
Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2003347552A (ja) * | 2002-05-29 | 2003-12-05 | Konica Minolta Holdings Inc | 有機トランジスタ及びその製造方法 |
JP2004304182A (ja) * | 2003-03-19 | 2004-10-28 | Semiconductor Energy Lab Co Ltd | 薄膜トランジスタ及びその作製方法 |
JP2005159329A (ja) * | 2003-10-28 | 2005-06-16 | Semiconductor Energy Lab Co Ltd | 半導体装置の作製方法 |
JP2005190992A (ja) * | 2003-11-14 | 2005-07-14 | Semiconductor Energy Lab Co Ltd | 表示装置及びその作製方法 |
JP2005202194A (ja) * | 2004-01-16 | 2005-07-28 | Seiko Epson Corp | 電気光学装置用基板、電気光学装置用基板の製造方法、電気光学装置、及び電子機器 |
WO2005091376A1 (ja) * | 2004-03-17 | 2005-09-29 | Japan Science And Technology Agency | 有機縦形トランジスタおよびその製造方法 |
Family Cites Families (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2587124B2 (ja) * | 1990-08-09 | 1997-03-05 | 株式会社ジーティシー | 薄膜トランジスタ回路の製造方法 |
US5259799A (en) * | 1992-03-02 | 1993-11-09 | Micron Technology, Inc. | Method to form self-aligned gate structures and focus rings |
KR970006260B1 (ko) * | 1994-01-07 | 1997-04-25 | 금성일렉트론 주식회사 | 박막트랜지스터 제조방법 |
KR100343222B1 (ko) * | 1995-01-28 | 2002-11-23 | 삼성에스디아이 주식회사 | 전계방출표시소자의제조방법 |
US6492232B1 (en) * | 1998-06-15 | 2002-12-10 | Motorola, Inc. | Method of manufacturing vertical semiconductor device |
KR20000027776A (ko) * | 1998-10-29 | 2000-05-15 | 김영환 | 액정 표시 장치의 제조방법 |
KR100401130B1 (ko) * | 2001-03-28 | 2003-10-10 | 한국전자통신연구원 | 수직형 채널을 가지는 초미세 mos 트랜지스터 제조방법 |
GB0111424D0 (en) * | 2001-05-10 | 2001-07-04 | Koninkl Philips Electronics Nv | Electronic devices comprising thin film transistors |
US6664576B1 (en) * | 2002-09-25 | 2003-12-16 | International Business Machines Corporation | Polymer thin-film transistor with contact etch stops |
US8026565B2 (en) * | 2003-01-30 | 2011-09-27 | University Of Cape Town | Thin film semiconductor device comprising nanocrystalline silicon powder |
-
2005
- 2005-10-06 GB GB0520350A patent/GB2432714A/en not_active Withdrawn
-
2006
- 2006-10-02 US US11/540,729 patent/US20070082438A1/en not_active Abandoned
- 2006-10-04 JP JP2006272643A patent/JP4730275B2/ja not_active Expired - Fee Related
Patent Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2003347552A (ja) * | 2002-05-29 | 2003-12-05 | Konica Minolta Holdings Inc | 有機トランジスタ及びその製造方法 |
JP2004304182A (ja) * | 2003-03-19 | 2004-10-28 | Semiconductor Energy Lab Co Ltd | 薄膜トランジスタ及びその作製方法 |
JP2005159329A (ja) * | 2003-10-28 | 2005-06-16 | Semiconductor Energy Lab Co Ltd | 半導体装置の作製方法 |
JP2005190992A (ja) * | 2003-11-14 | 2005-07-14 | Semiconductor Energy Lab Co Ltd | 表示装置及びその作製方法 |
JP2005202194A (ja) * | 2004-01-16 | 2005-07-28 | Seiko Epson Corp | 電気光学装置用基板、電気光学装置用基板の製造方法、電気光学装置、及び電子機器 |
WO2005091376A1 (ja) * | 2004-03-17 | 2005-09-29 | Japan Science And Technology Agency | 有機縦形トランジスタおよびその製造方法 |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2009535805A (ja) * | 2006-04-27 | 2009-10-01 | オーガニックアイディー インコーポレイテッド | 自己整合型高性能有機fetの構造及び製造 |
US8463116B2 (en) | 2008-07-01 | 2013-06-11 | Tap Development Limited Liability Company | Systems for curing deposited material using feedback control |
JP2016092058A (ja) * | 2014-10-30 | 2016-05-23 | 株式会社ジャパンディスプレイ | 半導体装置 |
Also Published As
Publication number | Publication date |
---|---|
JP4730275B2 (ja) | 2011-07-20 |
US20070082438A1 (en) | 2007-04-12 |
GB2432714A (en) | 2007-05-30 |
GB0520350D0 (en) | 2005-11-16 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JP4730275B2 (ja) | 薄膜トランジスタおよび薄膜トランジスタの製造方法 | |
US7271098B2 (en) | Method of fabricating a desired pattern of electronically functional material | |
US10707079B2 (en) | Orthogonal patterning method | |
US7226804B2 (en) | Method for forming pattern of organic insulating film | |
JP2010525381A (ja) | 基板上のパターン形成方法およびそれによって形成された電子素子 | |
JP2009272523A (ja) | 薄膜トランジスタおよび薄膜トランジスタの製造方法 | |
JP4984416B2 (ja) | 薄膜トランジスタの製造方法 | |
US20080006161A1 (en) | Method of fabricating a structure | |
WO2016067590A1 (ja) | 薄膜トランジスタおよびその製造方法 | |
WO2014015627A1 (zh) | 有机薄膜晶体管阵列基板及其制备方法和显示装置 | |
US20080029833A1 (en) | Transistor, an electronic circuit and an electronic device | |
KR101182522B1 (ko) | 나노 패턴 형성 방법과 그를 이용한 박막트랜지스터 및액정표시장치의 제조 방법 | |
JP2008073911A (ja) | スクリーン印刷方法、スクリーン印刷機及び有機薄膜トランジスタの製造方法 | |
KR20140047133A (ko) | 탑 게이트 트랜지스터 형성 방법 | |
JP5332145B2 (ja) | 積層構造体、電子素子、電子素子アレイ及び表示装置 | |
US8153512B2 (en) | Patterning techniques | |
TWI469224B (zh) | 有機薄膜電晶體及其製造方法 | |
US20090117686A1 (en) | Method of fabricating organic semiconductor device | |
US20100320463A1 (en) | Method of Fabricating a Semiconductor Device | |
JP2010045369A (ja) | ピンホールアンダーカット部を含む装置と工程 | |
US20060024859A1 (en) | Reverse printing | |
KR20180046257A (ko) | 박막 트랜지스터 제조 방법, 박막 트랜지스터, 및 이를 포함하는 전자 소자 | |
JP5458296B2 (ja) | 微細加工構造及びその加工方法並びに電子デバイス及びその製造方法 | |
US8288761B2 (en) | Composition for photosensitive organic dielectric material and application thereof | |
JP4501444B2 (ja) | トランジスタにおける配線構造の形成方法及び電界効果型トランジスタの製造方法 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
RD04 | Notification of resignation of power of attorney |
Free format text: JAPANESE INTERMEDIATE CODE: A7424 Effective date: 20070406 |
|
A977 | Report on retrieval |
Free format text: JAPANESE INTERMEDIATE CODE: A971007 Effective date: 20090924 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20091006 |
|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20091204 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20100720 |
|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20100913 |
|
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 20110322 |
|
A61 | First payment of annual fees (during grant procedure) |
Free format text: JAPANESE INTERMEDIATE CODE: A61 Effective date: 20110404 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20140428 Year of fee payment: 3 |
|
R150 | Certificate of patent or registration of utility model |
Free format text: JAPANESE INTERMEDIATE CODE: R150 |
|
S531 | Written request for registration of change of domicile |
Free format text: JAPANESE INTERMEDIATE CODE: R313531 |
|
R350 | Written notification of registration of transfer |
Free format text: JAPANESE INTERMEDIATE CODE: R350 |
|
LAPS | Cancellation because of no payment of annual fees |