JP2007067078A - 洗浄半導体チップトレー - Google Patents
洗浄半導体チップトレー Download PDFInfo
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- JP2007067078A JP2007067078A JP2005249535A JP2005249535A JP2007067078A JP 2007067078 A JP2007067078 A JP 2007067078A JP 2005249535 A JP2005249535 A JP 2005249535A JP 2005249535 A JP2005249535 A JP 2005249535A JP 2007067078 A JP2007067078 A JP 2007067078A
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- JP
- Japan
- Prior art keywords
- semiconductor chip
- groove
- tray
- solvent
- resist
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 54
- 238000004140 cleaning Methods 0.000 title abstract description 21
- 239000002904 solvent Substances 0.000 claims abstract description 23
- 230000001105 regulatory effect Effects 0.000 claims abstract description 7
- 230000002093 peripheral effect Effects 0.000 claims description 6
- 239000000463 material Substances 0.000 claims description 4
- 239000011248 coating agent Substances 0.000 claims 1
- 238000000576 coating method Methods 0.000 claims 1
- 238000007598 dipping method Methods 0.000 abstract 1
- 230000004308 accommodation Effects 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 2
- 238000007654 immersion Methods 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 229910001220 stainless steel Inorganic materials 0.000 description 2
- 239000010935 stainless steel Substances 0.000 description 2
- 238000000034 method Methods 0.000 description 1
- 230000000149 penetrating effect Effects 0.000 description 1
- 238000002791 soaking Methods 0.000 description 1
- 238000003860 storage Methods 0.000 description 1
Images
Landscapes
- Container, Conveyance, Adherence, Positioning, Of Wafer (AREA)
- Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)
- Exposure And Positioning Against Photoresist Photosensitive Materials (AREA)
- Stackable Containers (AREA)
- Packaging Frangible Articles (AREA)
Abstract
【課題の解決手段】 半導体チップ100を洗浄半導体チップトレー1の横方向規制部2と縦方向規制部3で規制される部分に収容し、半導体チップ100を収容していない他の洗浄半導体チップトレー1を重ね合わせた状態で、溶剤槽内に浸積することにより、洗浄半導体チップトレー1の各貫通孔7,12から溶剤を洗浄半導体チップトレー1内に導入し、溶剤を洗浄半導体チップトレー1の各溝4,5,10を通じて、隅々まで万遍なく行き渡らせ、レジスト101をムラなく除去する。
【選択図】 図7
Description
2 横方向規制部
3 縦方向規制部
4 上横溝
5 上縦溝
6 拡張部
7 縦溝貫通孔
8 横溝貫通孔
9 テーパー状凹部
10 下横溝
11 突縁部
12 側部貫通孔
13 下縦溝
14 平坦部
Claims (1)
- 表面にレジストを塗布した半導体チップを収容し、溶剤中に浸積して前記レジストを除去するための溶剤に対して不溶な材質からなる洗浄半導体チップトレーであって、
半導体チップをレジスト塗布面とは反対面において載置する表面側には、前記半導体チップの横方向の移動を規制する横方向規制部と、前記半導体チップの縦方向の移動を規制する縦方向規制部とを、互いに平行に伸びる上横溝を挟んで交互に連設するとともに、各横方向規制部同士及び各縦方向規制部同士は、互いに平行にかつ前記上横溝とは直交して伸びる上縦溝を挟んで連設し、前記上縦溝は前記上横溝よりも深く形成するとともに、前記横方向規制部に対応する部分では幅を拡張した拡張部を設けて、前記半導体チップの四隅部分を前記上横溝の底面で支持すべくなし、前記各上縦溝の前記各拡張部の中央部に対応する部分にはそれぞれ縦溝貫通孔を設け、前記各上横溝には各規制部の中央部に対応して横溝貫通孔をそれぞれ設け、四周縁には平坦部を設ける一方、裏面側には、各縦溝貫通孔に対応してテーパー状凹部を設け、これらテーパー状凹部を列状につなげるように、横方向規制部に対応して前記上横溝と平行に伸びる下横溝を設け、前記横溝貫通孔と連通しかつ前記下横溝と直交するように伸びる下縦溝を設けるとともに、四周縁に前記平坦部に対応して突縁部を設けた
ことを特徴とする洗浄半導体チップトレー。
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2005249535A JP4841898B2 (ja) | 2005-08-30 | 2005-08-30 | 洗浄半導体チップトレー |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2005249535A JP4841898B2 (ja) | 2005-08-30 | 2005-08-30 | 洗浄半導体チップトレー |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2007067078A true JP2007067078A (ja) | 2007-03-15 |
JP4841898B2 JP4841898B2 (ja) | 2011-12-21 |
Family
ID=37928940
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2005249535A Active JP4841898B2 (ja) | 2005-08-30 | 2005-08-30 | 洗浄半導体チップトレー |
Country Status (1)
Country | Link |
---|---|
JP (1) | JP4841898B2 (ja) |
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2009240977A (ja) * | 2008-03-31 | 2009-10-22 | Kyocera Kinseki Corp | 洗浄治具 |
JP2014034395A (ja) * | 2012-08-07 | 2014-02-24 | Sanko Co Ltd | 洗浄用トレー |
WO2017223345A1 (en) * | 2016-06-24 | 2017-12-28 | Invensas Corportion | Method and apparatus for stacking devices in an integrated circuit assembly |
US10796936B2 (en) | 2016-12-22 | 2020-10-06 | Invensas Bonding Technologies, Inc. | Die tray with channels |
Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0481686A (ja) * | 1990-07-24 | 1992-03-16 | Seiko Epson Corp | 電子機器 |
JPH06302575A (ja) * | 1993-04-15 | 1994-10-28 | Fujitsu Ltd | 半導体チップ洗浄方法 |
JPH07176511A (ja) * | 1993-12-17 | 1995-07-14 | Fujitsu Ltd | 半導体装置の製造方法 |
JPH07254637A (ja) * | 1994-03-15 | 1995-10-03 | Fujitsu Ltd | 半導体チップトレー |
JP2006253522A (ja) * | 2005-03-14 | 2006-09-21 | Matsushita Electric Ind Co Ltd | チップホルダー及びチップ処理方法 |
-
2005
- 2005-08-30 JP JP2005249535A patent/JP4841898B2/ja active Active
Patent Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0481686A (ja) * | 1990-07-24 | 1992-03-16 | Seiko Epson Corp | 電子機器 |
JPH06302575A (ja) * | 1993-04-15 | 1994-10-28 | Fujitsu Ltd | 半導体チップ洗浄方法 |
JPH07176511A (ja) * | 1993-12-17 | 1995-07-14 | Fujitsu Ltd | 半導体装置の製造方法 |
JPH07254637A (ja) * | 1994-03-15 | 1995-10-03 | Fujitsu Ltd | 半導体チップトレー |
JP2006253522A (ja) * | 2005-03-14 | 2006-09-21 | Matsushita Electric Ind Co Ltd | チップホルダー及びチップ処理方法 |
Cited By (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2009240977A (ja) * | 2008-03-31 | 2009-10-22 | Kyocera Kinseki Corp | 洗浄治具 |
JP2014034395A (ja) * | 2012-08-07 | 2014-02-24 | Sanko Co Ltd | 洗浄用トレー |
WO2017223345A1 (en) * | 2016-06-24 | 2017-12-28 | Invensas Corportion | Method and apparatus for stacking devices in an integrated circuit assembly |
US10163675B2 (en) | 2016-06-24 | 2018-12-25 | Invensas Corporation | Method and apparatus for stacking devices in an integrated circuit assembly |
US10515838B2 (en) | 2016-06-24 | 2019-12-24 | Invensas Corporation | Method and apparatus for stacking devices in an integrated circuit assembly |
US10796936B2 (en) | 2016-12-22 | 2020-10-06 | Invensas Bonding Technologies, Inc. | Die tray with channels |
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Publication number | Publication date |
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JP4841898B2 (ja) | 2011-12-21 |
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