JP2006518114A - 集積回路を静電放電の過渡現象から保護する回路およびその方法 - Google Patents
集積回路を静電放電の過渡現象から保護する回路およびその方法 Download PDFInfo
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- 238000000034 method Methods 0.000 title claims abstract description 22
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- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
- H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
- H01L27/0266—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using field effect transistors as protective elements
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Abstract
【解決手段】ICをESD過渡現象から保護する回路は、ESD電圧V(t)に応答し、出力を有するマスタ回路(26)と、該マスタ回路の該出力に接続された共通の入力を有する複数の並列分岐デバイスを備えるスレーブ回路(28)と、を備える。V(t)が増加するにつれて、前記マスタ回路は、V(t)の一部を前記スレーブ回路分岐デバイスの前記入力へ印加し、それによって、前記スレーブ回路分岐デバイスが通常ならば作動するしきい値電圧Vt1を、前記分岐デバイスの保持電圧Vhにはるかに近いより小さな値Vt1’に下げる。V(t)がVt1’に達した時、前記スレーブ回路デバイスのすべては、ほぼ同時に作動し、それによって、ESD過渡現象をグラウンドに無害に分岐する。
Description
Claims (11)
- ICをESD過渡現象から保護する回路であって、
ESD電圧V(t)に応答し、出力を有するマスタ回路と、
該マスタ回路の該出力に接続された共通の入力を有する複数の並列分岐デバイスを備えるスレーブ回路と、
を備え、
V(t)が増加するにつれて、前記マスタ回路は、V(t)の一部を前記スレーブ回路分岐デバイスの前記入力へ印加し、それによって、前記スレーブ回路分岐デバイスが通常ならば作動するしきい値電圧Vt1を、前記分岐デバイスの保持電圧Vhにはるかに近いより小さな値Vt1’に下げ、
V(t)がVt1’に達した時、前記スレーブ回路デバイスのすべては、ほぼ同時に作動し、それによって、ESD過渡現象をグラウンドに無害に分岐する、
ICをESD過渡現象から保護する回路。 - 前記スレーブ回路分岐デバイスの前記入力に印加されるV(t)の前記一部は、Vt1をほぼその最小値Vt1’に低減するのに十分なものである、請求項1に記載のICをESD過渡現象から保護する回路。
- 前記並列分岐デバイスはNMOSデバイスであり、該NMOSデバイスのゲート入力に印加されるV(t)の前記一部は、Vt1’を最小にする電圧である、請求項1に記載のICをESD過渡現象から保護する回路。
- 前記ESD過渡現象をグラウンドにほぼ分岐することによって、ICの節点を電圧V(t)に上昇するESD過渡現象から保護する請求項1に記載のICをESD過渡現象から保護する回路であって、
V(t)に応答するマスタ回路であって、該マスタ回路のいずれのコンポーネントの降伏もトリガすることなく、V(t)よりも小さな出力電圧Vmoを生成するマスタ回路と、
前記節点と前記グラウンドとの間に接続された電力端子を有する複数の並列デバイスを備えるスレーブ回路と、
を備え、
前記複数の並列デバイスは、前記マスタ回路の前記出力電圧Vmoを受け取る共通の入力端子を有し、前記出力電圧は、該共通の入力端子のすべてにほぼ同時に印加され、前記共通の入力端子で動作する前記出力電圧は、前記複数の並列デバイスのそれぞれの前記電力端子の少なくとも1つの降伏電圧を、現在のESD電圧V(t)以下に低減し、それによって、前記電力端子をほぼ同時に導通状態にさせ、該電力端子に前記EST過渡現象をグラウンドへ分岐させる、
請求項1に記載のICをESD過渡現象から保護する回路。 - 前記マスタ回路は、V(t)に応答した過渡電圧分圧器を備え、前記降伏電圧を最小にする電圧に等しいVmoを生成する、請求項4に記載のICをESD過渡現象から保護する回路。
- 前記マスタ回路は、しきい値電圧Vthを有するトランジスタを備え、前記降伏電圧を最小にする電圧に等しいVmoを生成する、請求項5に記載のICをESD過渡現象から保護する回路。
- 前記マスタ回路は、値Cのコンデンサ、及び、該コンデンサに直列に接続されてRの総抵抗値を有する1つ又は複数の抵抗器を備え、積RCは、前記ESD過渡現象のV(t)への立ち上がり時間の間、前記コンデンサの両端の電圧降下を無視できるものにする、請求項4に記載のICをESD過渡現象から保護する回路。
- ICの節点に現れる過渡電圧V(t)を無害にクランプする方法であって、
低減された過渡電圧Vmiを得るために、前記過渡電圧V(t)を分圧すること、
出力電圧Vmoを生成するために、能動デバイスの出力端子が抵抗器を通じて前記ICの基準グラウンドに接続された当該能動デバイスの制御端子に、前記低減された電圧Vmiを接続すること、及び
複数の並列能動デバイスの電力端子が前記節点と前記基準グラウンドとの間に接続された当該並列能動デバイスの入力に前記出力電圧Vmoをほぼ同時に接続すること、
を含み、
前記出力電圧Vmoは、前記複数の並列能動デバイスをほぼ電圧V(t)でほぼ同時に作動させるのに十分なレベルに前記複数の並列能動デバイスの作動電圧を低減し、それによって、前記節点に現れる前記過渡電圧を安全なレベルにクランプするのに十分なものである、
ICの節点に現れる過渡電圧V(t)を無害にクランプする方法。 - 前記最初の接続するステップは、前記低減された電圧よりも小さなしきい値電圧あたりの出力電圧を生成するために、能動デバイスの出力端子が抵抗器を通じて前記ICの基準グラウンドに接続された当該能動デバイスの制御端子に、前記低減された電圧を接続することを含む、請求項8に記載のICの節点に現れる過渡電圧V(t)を無害にクランプする方法。
- 前記分圧するステップ及び前記最初の接続するステップは、前記過渡電圧V(t)よりも小さな出力電圧Vmoを得るために、ツェナーダイオードが生成した電圧によって前記過渡電圧を低減することを含む、請求項8に記載のICの節点に現れる過渡電圧V(t)を無害にクランプする方法。
- ガードバンドを提供することをさらに含み、前記複数の並列デバイスは、十分な電流容量を提供して、ESD過渡現象が過ぎ去った後に、前記ICの漏電の増加が発生することを阻止する、請求項8に記載のICの節点に現れる過渡電圧V(t)を無害にクランプする方法。
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US10/365,791 US7224560B2 (en) | 2003-02-13 | 2003-02-13 | Destructive electrical transient protection |
PCT/US2004/004211 WO2004073040A2 (en) | 2003-02-13 | 2004-02-12 | Esd protection circuit |
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JP2006518114A true JP2006518114A (ja) | 2006-08-03 |
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JP2006503542A Pending JP2006518114A (ja) | 2003-02-13 | 2004-02-12 | 集積回路を静電放電の過渡現象から保護する回路およびその方法 |
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Country | Link |
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US (1) | US7224560B2 (ja) |
EP (1) | EP1597766A2 (ja) |
JP (1) | JP2006518114A (ja) |
CA (1) | CA2515956A1 (ja) |
WO (1) | WO2004073040A2 (ja) |
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-
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- 2004-02-12 EP EP04710681A patent/EP1597766A2/en not_active Withdrawn
- 2004-02-12 JP JP2006503542A patent/JP2006518114A/ja active Pending
- 2004-02-12 CA CA002515956A patent/CA2515956A1/en not_active Abandoned
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JP2010232572A (ja) * | 2009-03-30 | 2010-10-14 | New Japan Radio Co Ltd | 半導体静電保護装置 |
JP2011114056A (ja) * | 2009-11-25 | 2011-06-09 | Sharp Corp | 静電気放電保護回路 |
JP2012169522A (ja) * | 2011-02-16 | 2012-09-06 | Lapis Semiconductor Co Ltd | 過電圧保護回路及び半導体集積回路 |
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WO2004073040A3 (en) | 2004-10-07 |
US7224560B2 (en) | 2007-05-29 |
US20040160717A1 (en) | 2004-08-19 |
EP1597766A2 (en) | 2005-11-23 |
WO2004073040A2 (en) | 2004-08-26 |
CA2515956A1 (en) | 2004-08-26 |
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