JP2006507684A5 - - Google Patents

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Publication number
JP2006507684A5
JP2006507684A5 JP2004555330A JP2004555330A JP2006507684A5 JP 2006507684 A5 JP2006507684 A5 JP 2006507684A5 JP 2004555330 A JP2004555330 A JP 2004555330A JP 2004555330 A JP2004555330 A JP 2004555330A JP 2006507684 A5 JP2006507684 A5 JP 2006507684A5
Authority
JP
Japan
Prior art keywords
gate
area
finfe
finfet
doped
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2004555330A
Other languages
English (en)
Japanese (ja)
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JP2006507684A (ja
Filing date
Publication date
Priority claimed from US10/301,617 external-priority patent/US6842048B2/en
Application filed filed Critical
Publication of JP2006507684A publication Critical patent/JP2006507684A/ja
Publication of JP2006507684A5 publication Critical patent/JP2006507684A5/ja
Pending legal-status Critical Current

Links

JP2004555330A 2002-11-22 2003-10-14 ２トランジスタｎｏｒデバイス Pending JP2006507684A (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US10/301,617 US6842048B2 (en) 2002-11-22 2002-11-22 Two transistor NOR device
PCT/US2003/032782 WO2004049445A1 (en) 2002-11-22 2003-10-14 Two transistor nor device

Publications (2)

Publication Number Publication Date
JP2006507684A JP2006507684A (ja) 2006-03-02
JP2006507684A5 true JP2006507684A5 (enExample) 2006-11-30

Family

ID=32324568

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2004555330A Pending JP2006507684A (ja) 2002-11-22 2003-10-14 ２トランジスタｎｏｒデバイス

Country Status (8)

Country Link
US (1) US6842048B2 (enExample)
EP (1) EP1563543A1 (enExample)
JP (1) JP2006507684A (enExample)
KR (1) KR20050086701A (enExample)
CN (1) CN100524762C (enExample)
AU (1) AU2003279293A1 (enExample)
TW (1) TWI317985B (enExample)
WO (1) WO2004049445A1 (enExample)

Families Citing this family (21)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8008136B2 (en) * 2003-09-03 2011-08-30 Advanced Micro Devices, Inc. Fully silicided gate structure for FinFET devices
US6855588B1 (en) * 2003-10-07 2005-02-15 United Microelectronics Corp. Method of fabricating a double gate MOSFET device
JP4852694B2 (ja) * 2004-03-02 2012-01-11 独立行政法人産業技術総合研究所 半導体集積回路およびその製造方法
US7212432B2 (en) * 2004-09-30 2007-05-01 Infineon Technologies Ag Resistive memory cell random access memory device and method of fabrication
KR100679693B1 (ko) * 2004-10-29 2007-02-09 한국과학기술원 비대칭적인 일함수를 갖는 이중 게이트 구조를 이용한2비트 비휘발성 메모리 소자 제조 방법 및 그 구조
CN100364094C (zh) * 2005-01-31 2008-01-23 北京大学 一种FinFET电路与纳机电梁集成的芯片及其制作方法
US7368787B2 (en) * 2005-05-19 2008-05-06 International Business Machines Corporation Fin field effect transistors (FinFETs) and methods for making the same
US7323374B2 (en) * 2005-09-19 2008-01-29 International Business Machines Corporation Dense chevron finFET and method of manufacturing same
US7592841B2 (en) * 2006-05-11 2009-09-22 Dsm Solutions, Inc. Circuit configurations having four terminal JFET devices
EP1987541A1 (en) * 2006-02-13 2008-11-05 Nxp B.V. Double-gate semiconductor devices having gates with different work functions and methods of manufacture thereof
US8368144B2 (en) * 2006-12-18 2013-02-05 Infineon Technologies Ag Isolated multigate FET circuit blocks with different ground potentials
US8217435B2 (en) 2006-12-22 2012-07-10 Intel Corporation Floating body memory cell having gates favoring different conductivity type regions
FR2911004B1 (fr) * 2006-12-28 2009-05-15 Commissariat Energie Atomique Procede de realisation de transistors a double-grille asymetriques permettant la realisation de transistors a double-grille asymetriques et symetriques sur un meme substrat
US8492796B2 (en) * 2007-03-13 2013-07-23 Infineon Technologies Ag MuGFET switch
US7667499B2 (en) * 2007-06-11 2010-02-23 Infineon Technologies Ag MuGFET circuit for increasing output resistance
US8263446B2 (en) 2010-09-13 2012-09-11 International Business Machines Corporation Asymmetric FinFET devices
WO2013106799A1 (en) * 2012-01-13 2013-07-18 Tela Innovations, Inc. Circuits with linear finfet structures
KR101424755B1 (ko) * 2013-01-03 2014-07-31 한국과학기술원 독립적으로 구동이 가능하고 다른 일함수를 가지는 이중 게이트 구조를 포함하는 전자-정공 이중층 터널 전계 효과 트랜지스터 및 그 제조 방법
US9391204B1 (en) 2015-03-12 2016-07-12 International Business Machines Corporation Asymmetric FET
CN107222204B (zh) * 2017-04-20 2020-07-24 宁波大学 基于FinFET晶体管的电流模RM或非-异或单元电路
US11551930B2 (en) * 2018-12-12 2023-01-10 Tokyo Electron Limited Methods to reshape spacer profiles in self-aligned multiple patterning

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5612563A (en) 1992-03-02 1997-03-18 Motorola Inc. Vertically stacked vertical transistors used to form vertical logic gate structures
JP3128364B2 (ja) 1992-11-13 2001-01-29 新日本製鐵株式会社 半導体装置及びその製造方法
JPH06275826A (ja) 1993-03-24 1994-09-30 Fujitsu Ltd 半導体装置
JP2000340795A (ja) 1999-05-26 2000-12-08 Sony Corp 半導体論理素子およびそれを用いた論理回路
US6396108B1 (en) 2000-11-13 2002-05-28 Advanced Micro Devices, Inc. Self-aligned double gate silicon-on-insulator (SOI) device
US6583440B2 (en) * 2000-11-30 2003-06-24 Seiko Epson Corporation Soi substrate, element substrate, semiconductor device, electro-optical apparatus, electronic equipment, method of manufacturing the soi substrate, method of manufacturing the element substrate, and method of manufacturing the electro-optical apparatus
JP2002198518A (ja) * 2000-12-25 2002-07-12 Toshiba Corp 半導体装置及びその製造方法
US6462585B1 (en) 2001-02-20 2002-10-08 International Business Machines Corporation High performance CPL double-gate latch
JP2002289697A (ja) * 2001-03-27 2002-10-04 Toshiba Corp 相補型絶縁ゲート型トランジスタ
US6433609B1 (en) * 2001-11-19 2002-08-13 International Business Machines Corporation Double-gate low power SOI active clamp network for single power supply and multiple power supply applications
US6580293B1 (en) * 2001-12-14 2003-06-17 International Business Machines Corporation Body-contacted and double gate-contacted differential logic circuit and method of operation

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