TWI630684B - 形成用於ｃｍｏｓ的雙軸拉伸應變鍺通道的方法及具有該通道的設備 - Google Patents

形成用於ｃｍｏｓ的雙軸拉伸應變鍺通道的方法及具有該通道的設備 Download PDF

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TWI630684B
TWI630684B TW106123825A TW106123825A TWI630684B TW I630684 B TWI630684 B TW I630684B TW 106123825 A TW106123825 A TW 106123825A TW 106123825 A TW106123825 A TW 106123825A TW I630684 B TWI630684 B TW I630684B
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channel
mosfet
channel mosfet
buffer layer
lattice constant
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普瑞斯韓特 馬吉
尼洛依 穆可吉
拉維 皮拉瑞斯提
威利 瑞奇曼第
羅伯特 喬
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英特爾股份有限公司
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Abstract

一種設備包含：互補金屬氧化物半導體(CMOS)反相器，包含有n-通道金屬氧化物半導體場效電晶體(MOSFET)；及p-通道MOSFET，其中在該n-通道MOSFET的通道材料與在該p-通道MOSFET中的通道材料受到雙軸拉伸應變。一種方法，包含：形成n-通道金屬氧化物半導體場效電晶體(MOSFET)；形成p-通道MOSFET；及連接該n-通道MOSFET及該p-通道MOSFET的閘極電極與汲極區，其中在該n-通道MOSFET中之通道材料與在該p-通道MOSFET中之通道材料受到雙軸拉伸應變。

Description

形成用於CMOS的雙軸拉伸應變鍺通道的方法及具有該通道的設備
本案關係於半導體裝置。
對於過去幾十年來，在積體電路中之特性的縮小化已經在持續成長的半導體工業中一直是種驅使力量。縮小至更小更小特性使得能在半導體晶片的有限實體內完成增加功能單元的密度。例如，縮小的電晶體尺寸允許加入增加數量的記憶體單元於晶片上，導致可以製造具有增加容量的產品。然而，更大容量的驅動並不是一直沒有問題。因此，將各個裝置的效能最佳化變得更加重要。
增加載體移動率(超出矽的載體移動率)係想要持續縮小電晶體裝置，包含互補金屬氧化物半導體(CMOS)反相器並輸送增加的效能與較低功率。例如III-V族化合物半導體材料的有希望材料提供n-通道金屬氧化物半導體場效電晶體(MOSFET)高電子移動率及鍺為主材料提供p-通道MOSFET高電洞移動率。因為在III-V族化合物半導體材料與鍺材料間之差異，所以，對於次 -10奈米(nm)節點幾何中，將兩分開系統整合至矽上之高度縮小CMOS反相器中有著嚴重的挑戰。另外，包含緩衝層、閘堆疊、接點等等之薄膜堆疊係期待與III-V族化合物半導體與鍺有所不同，這進一步增加在縮小CMOS中整合不同通道材料的複雜度。
100‧‧‧反相器
110‧‧‧基板
120‧‧‧緩衝層
130‧‧‧p-通道MOSFET
132‧‧‧閘極電極
134‧‧‧源極區
135‧‧‧汲極區
136‧‧‧通道
140‧‧‧n-通道MOSFET
142‧‧‧閘極電極
144‧‧‧源極區
145‧‧‧汲極區
146‧‧‧通道
150‧‧‧STI結構
200‧‧‧反相器
230‧‧‧p-通道MOSFET
232A-D‧‧‧閘極電極部
234‧‧‧源極區
235‧‧‧汲極區
236A-C‧‧‧通道
240‧‧‧n-通道MOSFET
242A-C‧‧‧閘極電極部
244‧‧‧源極區
245‧‧‧汲極區
246A-C‧‧‧通道
300‧‧‧計算裝置
302‧‧‧板
304‧‧‧處理器
306‧‧‧通訊晶片
圖1顯示CMOS反相器實施例之側俯視透視圖。
圖2為CMOS反相器的另一實施例。
圖3為依據一實施法的計算裝置。
【發明內容與實施方式】
本案描述半導體裝置與形成與使用半導體裝置的方法。同時，也描述一起整合n-通道MOSFET與p-通道MOSFET裝置，用於CMOS實施法(CMOS反相器)，其中各個電晶體裝置包含受到雙軸拉伸應變的通道材料。在一實施例中，n-通道MOSFET與p-通道MOSFET係被以共同通道材料形成，該通道材料受到雙軸拉伸應變。在一實施例中，該共同材料為鍺材料。
圖1顯示CMOS反相器的俯視側透視圖。在此實施例中，反相器100包含p-通道MOSFET130及n-通道MOSFET140。在此實施例中，各個p-通道MOSFET130及n-通道MOSFET140為平面裝置。在圖1所示之實施例中，各個p-通道MOSFET130及n-通道MOSFET140係被 形成在基板110上。基板110例如為單晶矽基板或絕緣層上有矽(SOI)基板。在矽基板110上，有緩衝層120。P-通道MOSFET130與n-通道MOSFET140係分別形成在緩衝層120上並為例如介電材料，如氧化物的淺溝渠隔離(STI)結構150所分開。P-通道MOSFET130包含閘極電極132、源極區134、汲極區135、及通道136配置於閘極電極132之下的源極區134與汲極區135之間。閘極電極132係與通道136分開，並為配置於其間之閘極介電質所分開，閘極介電質係例如具有介電常數大於二氧化矽的介電材料(高K材料)。N-通道MOSFET140包括閘極電極142、源極區144、汲極區145、及通道146配置於源極區144與汲極區145之間。閘極電極142與通道區域被配置於其間的閘極介電質所分開，例如高K介電材料所分開。P-通道MOSFET130包括閘極電極132、源極區134及汲極區135大致摻雜或構成p-型材料。N-通道MOSFET140包括閘極電極142、源極區144及汲極區145大致摻雜或構成n-型材料。CMOS反相器100係藉由連接p-通道MOSFET130的汲極區135與n-通道MOSFET140的汲極區145所形成，及各個閘極電極的連接係如所示。
在一實施例中，緩衝層120選擇一材料，其具有大於p-通道MOSFET130的通道136與n-通道MOSFET140的通道146材料為大的晶格常數。如所示，通道136與通道146係配置於緩衝層120上。在材料間之晶格常數差異將在各個通道136與通道146中產生雙軸拉 伸應變。在一實施例中，通道136的材料與通道146的材料為共同的。這些通道的代表性共同材料為鍺。在鍺中之雙軸拉伸應變修改其能帶結構及電子與電洞的載體有效質量(移動率)。在一實施例中用於具有大於鍺的晶格常數的緩衝層120的材料為III-V族化合物半導體材料，例如，磷化銦鎵(InGaP)。在一實施例中，雙軸拉伸應變位準為大於1.5百分比。
用以形成CMOS反相器，例如反相器100的技術係為磊晶或沉積緩衝層120於基板110上。可以了解的是，緩衝層120的想要材料施加至少1.5百分比的雙軸拉伸應變於鍺上，也可能類似地施加應變於基板110上。為了降低或禁止在基板110上之應變，可以使用階層式緩衝層，例如階層式III-V族化合物半導體(例如，InGaP)，其在通道介面具有最大晶格常數。
在形成緩衝層120後，通道136與通道236與接面區(源極區134及汲極區135與源極區234與汲極區235)可以例如以磊晶沉積形成。閘極介電質與閘極電極可以然後被引入用於各個裝置(閘極電極132、閘極電極232)及個別裝置被依需要摻雜。於汲極區與電極間之接點係被完成，以形成CMOS反相器。
圖2顯示例如在一CMOS反相器中之整合p-通道與n-通道MOSFET的另一實施例。在此實施例中，p-通道MOSFET與n-通道MOSFET各個為非平面裝置，更明確地說，奈米線或奈米帶裝置。參考圖2，反相器 200包括n-通道MOSFET結構230其含有閘極電極部232A、232B、232C、232D；源極區234；汲極區235；及通道236A、236B及236C分別配置於閘極電極間。CMOS反相器200同時也包括含有閘極電極部242A、242B、242C及242D；源極區244；汲極區245；及通道246A、246B、246C配置於各個閘極電極部間的n-通道MOSFET結構240。對於p-通道MOSFET結構230，各個閘極電極部232A-232D係與個別通道(通道236A-236C)被閘極介電材料分開，例如高K介電質及閘極電極與源極與汲極區係被摻雜或構成p-型。類似地，n-通道MOSFET240的閘極電極部242A-242D係與個別通道246A-246C被閘極介電材料分開，例如高介電常數材料，及閘極電極部與源極與汲極區係被摻雜或構成n-型。CMOS反相器係被顯示為將p-通道MOSFET結構230的汲極區235連接至n-通道MOSFET結構240的汲極區245，及連接該等結構的閘極電極。
在一實施例中，用於p-通道MOSFET結構230的通道236A-236C及用於n-通道MOSFET結構240的通道246A-246C材料係各個受到雙軸拉伸應變。在一實施例中，用於p-通道MOSFET結構230與n-通道MOSFET結構240的此等通道的材料係為共同或相同。代表性材料為鍺。在一實施例中，雙軸拉伸應變係被該閘極電極部所施加至通道上。閘極電極的代表性材料包含氮化鈦(TiN)及氮化鉭(TaN)。在一實施例中，對於示於 圖2的奈米帶組態形成的通道，奈米帶通道具有大約15奈米或更低之厚度。為了施加雙軸拉伸應變於奈米帶通道上，在一實施例中，閘極電極部具有大於100奈米的長度。在另一實施例中，源極與汲極區被作用為錨，以侷限該應變於通道中。源極與汲極區的材料(源極區234、汲極區235、源極區244、汲極區245)及/或配置在閘極電極部與源極與汲極區間之間隔材料施加應變或作用以保留該應變。
圖2的結構可以以各種方式形成。一種技術為圖案化奈米帶/奈米線通道236A-236C及246A-246C為交替的鍺磊晶層於例如矽的犧牲材料層之間。犧牲層可以然後被移除，以留下奈米帶(236A-236C或246A-246C)懸於在基板上或之上的支撐部間之不同平面。在此點，源極與汲極區可以例如藉由適當摻雜用於懸吊奈米線的支撐部加以形成。例如高K介電材料的介電材料然後可以被引入於各個奈米線附近，其後引入閘極電極材料。在一實施例中，犧牲閘極電極可以被引入並圖案化，然後以想要閘極電極材料替換。間隔層也可以加入於奈米帶通道與源極與汲極區之間。為了形成CMOS反相器，可以作成接點並連接於p-通道MOSFET與n-通道MOSFET的汲極之間及在該等裝置的閘極之間。
上述說明係參考CMOS反相器的兩個結構實施例。可以了解的是，該特定結構實施例並不需要被限制，各種不同結構實施例可以被製造，其中雙軸拉伸應變 係被施加在CMOS反相器的p-通道MOSFET的通道與n-通道MOSFET的通道及各個通道具有共同材料(例如鍺)。因此，可以想到例如多閘裝置及多橋通道裝置的其他結構實施例。
圖3例示依據一實施法的計算裝置300。計算裝置300包圍住板302。板302可以包含若干元件，包括但並不限於處理器304及至少一通訊晶片306。處理器304係實體及電耦接至板302。在一些實施法中，至少一通訊晶片306也實體及電耦接至板302。在其他實施法中，通訊晶片306係為處理器304的一部份。
取決於其應用，計算裝置300可以包含其他元件，這些元件可以可不實體及電耦接至板302。這些其他元件包括但並不限定於揮發記憶體(例如DRAM)、非揮發記憶體(例如ROM)、快閃記憶體、圖形處理器、數位信號處理器、密碼處理器、晶片組、天線、顯示器、觸控螢幕顯示器、觸控螢幕控制器、電池、音訊編解碼器、視訊編解碼器、功率放大器、全球定位系統(GPS)裝置、羅盤、加速計、陀螺儀、喇叭、攝像機、及大量儲存裝置(例如，硬碟機、光碟(CD)、數位多功能光碟(DVD)、等等)。
通訊晶片306完成資料進出計算裝置300的無線通訊。用語“無線”及其衍生詞可以用以描述電路、裝置、系統、方法、技術、通訊頻道等等，這些可以透過非實體媒體藉由使用調變電磁輻射加以傳遞資料。雖然在一 些實施例中，可能不包含電線，但該用語並不暗示相關裝置不包含任何電線。通訊晶片306可以實施若干無線標準或協定的任一者，包含但並不限於Wi-Fi(IEEE802.11系列)、WiMAX(IEEE802.16系列)、IEEE802.20、長期演進(LTE)、Ev-DO、HSPA+、HSDPA+、HSUPA+、EDGE、GSM、GPRS、CDMA、TDMA、DECT、藍芽、及其衍生協定，以及可以被指定為3G、4G、5G及後續的其他任何無線協定。計算裝置300可以包括多數通訊晶片306。例如，第一通訊晶片306可以專屬於短距無線通訊，例如Wi-Fi及藍芽，及第二通訊晶片306可以專屬於長距無線通訊，例如GPS、EDGE、GPRS、CDMA、WiMAX、LTE、Ev-DO等等。
計算裝置300的處理器304包含封裝在處理器304內的積體電路晶粒。在本發明之一些實施法中，處理器的積體電路晶粒包括一或更多裝置，裝置係例如，如上所述之共同材料(例如，鍺)的雙軸拉伸應變電晶體的一或更多CMOS反相器。用語“處理器”可以表示任何裝置或裝置的部份，其處理來自暫存器及/或記憶體的電子資料，並將該電子資料轉換為可以儲存在暫存器及/或記憶體中的其他電子資料。
通訊晶片306也包括封裝在通訊晶片306內的積體電路晶粒。依據另一實施法，通訊晶片的積體電路晶粒包括一或更多裝置，例如CMOS反相器，其可以依據上述實施法加以形成者。
在其他實施法中，包圍在計算裝置300內的另一元件可以包括積體電路晶粒，其包含一或更多裝置，例如，依據該等實施法形成的CMOS反相器。
在各種實施法中，計算裝置300可以為膝上型電腦、小筆電、筆記型電腦、超筆記型電腦、智慧手機、平板電腦、個人數位助理(PDA)、超行動PC、行動電話、桌上型電腦、伺服器、印表機、掃描器、監視器、機上盒、娛樂控制單元、數位相機、攜帶式音樂播放器、或數位視訊記錄器。在其他實施法中，計算裝置300可以為處理資料的任何電子裝置。
〔例子〕
以下例子屬於實施例。
例子1為一種包含互補金屬氧化物半導體(CMOS)反相器的設備，該CMOS反相器包含n-通道金屬氧化物半導體場效電晶體(MOSFET)及p-通道MOSFET，其中在n-通道MOSFET中之通道材料與在p-通道MOSFET中之通道材料各個受到雙軸拉伸應變。
在例子2中，在例子1的設備中的n-通道MOSFET中之通道材料與在p-通道MOSFET中之通道材料相同。
在例子3中，在例子1的設備中的n-通道MOSFET中之通道材料與在p-通道MOSFET中之通道材料均為鍺。
在例子4中，在例子1的設備中的n-通道MOSFET與p-通道MOSFET中之各個通道係配置在緩衝層上，且該緩衝層包括具有晶粒常數大於在該n-通道MOSFET的通道材料與在該p-通道MOSFET的通道材料的晶格常數。
在例子5中，在例子4的設備中的緩衝層的材料包括III-V族化合物半導體材料。
在例子6中，在例子4的設備中的n-通道MOSFET與p-通道MOSFET為平面電晶體。
在例子7中，在例子1的設備中的n-通道MOSFET中之通道材料與在p-通道MOSFET中之通道材料各個的晶格常數係小於個別閘極電極材料之晶格常數。
在例子8中，在例子7的設備中的個別閘極電極具有大於100奈米的長度。
例子9為一種包括n-通道金屬氧化物半導體場效電晶體(MOSFET)與p-通道MOSFET的設備，該n-通道MOSFET包括閘極電極、源極區、汲極區、及通道，該p-通道MOSFET包括閘極電極、源極區、汲極區、及通道，其中該n-通道MOSFET的該閘極電極係耦接至該p-通道MOSFET的該閘極電極；以及該n-通道MOSFET的該汲極係耦接至該p-通道MOSFET的該汲極，及其中在該n-通道MOSFET中之該通道的材料與在該p-通道MOSFET中之該通道的材料係共同並受到雙軸拉伸應變。
在例子10中，在例子9的設備中的n-通道MOSFET的通道材料與在p-通道MOSFET中之通道材料共同為鍺。
在例子11中，在例子9的設備中的各個n-通道MOSFET與p-通道MOSFET之通道係配置在緩衝層上及該緩衝層包含一材料，其晶格常數係大於在該n-通道MOSFET通道材料與在該p-通道MOSFET的通道材料的共同材料的晶格常數。
在例子12中，在例子11的設備中的緩衝層的材料包括III-V族化合物半導體材料。
在例子13中，在例子11的設備中的n-通道MOSFET與p-通道MOSFET為平面電晶體。
在例子14中，在例子9的設備中的n-通道MOSFET中之通道的共同材料與在p-通道MOSFET中之通道之材料的晶格常數小於個別閘極電極的材料之晶格常數。
在例子15中，在例子14的設備中的閘極電極具有大於100奈米的長度。
在例子16中，在例子14的設備中的n-通道MOSFET中之通道與在p-通道MOSFET中之通道包含奈米帶。
例子17為一種方法，包含：形成n-通道金屬氧化物半導體場效電晶體(MOSFET)；形成p-通道MOSFET；及連接該n-通道MOSFET與該p-通道MOSFET 的閘極電極與汲極區，其中在該n-通道MOSFET中之通道材料與在該p-通道MOSFET中之通道材料受到雙軸拉伸應變。
在例子18中，在例子17的設備中的n-通道MOSFET中之通道材料與在p-通道MOSFET中之通道材料為共同的。
在例子19中，在例子17的方法更包含形成緩衝層在該基板上，該緩衝層配置鄰近該n-通道MOSFET之通道與p-通道MOSFET之通道，該緩衝層具有大於在該n-通道MOSFET中之通道材料與在該p-通道MOSFET中之通道材料的該共同材料的晶格常數。
在例子20中，在例子17的方法中的n-通道MOSFET中之通道共同材料與在p-通道MOSFET中之通道材料為鍺。
在例子21中，在例子17的方法中的n-通道MOSFET中之通道與在p-通道MOSFET中之通道的共同材料各個的晶格常數，低於個別閘極電極的材料的晶格常數。
在例子22中，在例子21的方法中的個別閘極電極具有大於100奈米的長度。
在例子23中，在例子21的方法中的n-通道MOSFET中之通道與在p-通道MOSFET中之通道包含奈米帶。
在上述說明中，為了解釋的目的，各種特定 細節已經加以說明，以提供對實施例的完整了解。然而，明顯地，對於熟習於本技藝者，一或更多其他實施例可以在沒有這些特定細節下加以實施。於此所述之特定實施例並不是提供用以限定本發明而只作例示。本發明之範圍並不是由以上提供的特定例所決定，而是只由以下的申請專利範圍所決定。在其他例子中，已知結構、裝置、及操作已經以方塊圖形式並沒有細節加以顯示，以避免模糊對本說明的了解。其中參考元件符號或參考符號的末端部份已經在該等圖式中重覆，以表示對應或類似元件，其可以選用以具有類似特徵。
應了解的是，例如，在說明書中之“一實施例”、“實施例”、“一或更多實施例”或“不同實施例”可以表示包含在本發明實施中之特定特性。類似地，應了解的是，說明書的各種特性有時被集合在單一實施例、圖式或說明中，為了合理化本案與協助各種發明態樣的了解。然而，本案的方法並不解譯為反映本發明需要較在各請求項中所描更多特性。相反地，如同以下請求項所反映，本發明的態樣可以在單一揭露實施例之所有特性為少。因此，以下發明說明後的申請專利範圍係被表示為加入此詳細說明，各個請求項本身表示為本發明分開實施例。

Claims (28)

  1. 一種具有雙軸應變通道的設備，包含：互補金屬氧化物半導體(CMOS)反相器，包含：n-通道金屬氧化物半導體場效電晶體(MOSFET)及p-通道MOSFET，其中在該n-通道MOSFET中之通道材料與在該p-通道MOSFET中之通道材料各個受到雙軸應變，其中各個該n-通道MOSFET與該p-通道MOSFET的所述通道係配置在緩衝層上及該緩衝層包含一材料，該材料的晶格常數與在該n-通道MOSFET的該通道材料與在該p-通道MOSFET的該通道材料的晶格常數不同，其中該n-通道MOSFET中的該通道材料與該p-通道MOSFET中的該通道材料各個具有一晶格常數，其係小於個別閘極電極材料的晶格常數。
  2. 如申請專利範圍第1項所述之設備，其中所述雙軸應變為雙軸拉伸應變。
  3. 如申請專利範圍第1項所述之設備，其中該緩衝層具有一晶格常數，該晶格常數大於在該n-通道MOSFET中的該通道材料的晶格常數。
  4. 如申請專利範圍第1項所述之設備，其中在該n-通道MOSFET中的該通道材料與在該p-通道MOSFET中的該通道材料類似。
  5. 如申請專利範圍第1項所述之設備，其中在該n-通道MOSFET中的該通道材料與在該p-通道MOSFET中 的該通道材料各個都是鍺。
  6. 如申請專利範圍第1項所述之設備，其中該緩衝層的材料包含III-V族化合物半導體材料。
  7. 如申請專利範圍第1項所述之設備，其中該n-通道MOSFET與該p-通道MOSFET為平面電晶體。
  8. 如申請專利範圍第1項所述之設備，其中該個別閘極電極具有大於100奈米的長度。
  9. 一種反相器，包含：n-通道金屬氧化物半導體場效電晶體(MOSFET)，包含閘極電極、源極區、汲極區及通道；及p-通道MOSFET，包含閘極電極、源極區、汲極區及通道，其中該n-通道MOSFET的該閘極電極耦接至該p-通道MOSFET的該閘極電極；以及，該n-通道MOSFET的該汲極耦接至該p-通道MOSFET的該汲極，其中在該n-通道MOSFET中的該通道的材料與在該p-通道MOSFET中的該通道的材料被選擇為類似材料並受到雙軸應變，及其中各個該n-通道MOSFET與該p-通道MOSFET的該通道配置在緩衝層上，以及，該緩衝層包含一材料，該材料的晶格常數與該n-通道MOSFET的該通道的共同材料與該p-通道MOSFET中的該通道的材料的晶格常數不同，其中在該n-通道MOSFET中的該通道的該共同材料與在該p-通道MOSFET中的該通道的材料具有晶格常 數，其小於所述個別閘極電極的材料的晶格常數。
  10. 如申請專利範圍第9項所述之反相器，其中該雙軸應變為雙軸拉伸應變。
  11. 如申請專利範圍第9項所述之反相器，其中該緩衝層具有一晶格常數，該晶格常數大於在該n-通道MOSFET中的該通道的該材料的晶格常數。
  12. 如申請專利範圍第9項所述之反相器，其中在該n-通道MOSFET中的該通道的該共同材料與在該p-通道MOSFET的該通道的材料為鍺。
  13. 如申請專利範圍第9項所述之設備，其中該緩衝層的材料包含III-V族化合物半導體材料。
  14. 如申請專利範圍第9項所述之設備，其中該n-通道MOSFET與該p-通道MOSFET為平面電晶體。
  15. 如申請專利範圍第9項所述之設備，其中該閘極電極具有大於100奈米的長度。
  16. 如申請專利範圍第9項所述之設備，其中該n-通道MOSFET的該通道與該p-通道MOSFET的該通道包含奈米帶。
  17. 一種形成反相器的方法，包含：形成n-通道金屬氧化物半導體場效電晶體(MOSFET)；形成p-通道MOSFET；連接該n-通道MOSFET與該p-通道MOSFET的閘極電極與汲極區；及 在基板上形成緩衝層，該緩衝層配置鄰近該n-通道MOSFET的通道與該p-通道MOSFET的通道，該緩衝層包含一材料，該材料的晶格常數與在該n-通道MOSFET中的該通道的材料及在該p-通道MOSFET中的該通道的該材料的晶格常數不同，其中在該n-通道MOSFET的該通道之材料與在該p-通道MOSFET的該通道之材料受到雙軸應變，其中在該n-通道MOSFET中的該通道與在該p-通道MOSFET中的該通道的共同材料各個具有小於個別所述閘極電極的材料的晶格常數。
  18. 如申請專利範圍第17項所述之方法，其中該雙軸應變為雙軸拉伸應變。
  19. 如申請專利範圍第17項所述之方法，其中該緩衝層具有一晶格常數，該晶格常數大於在該n-通道MOSFET中的該通道的該材料的晶格常數。
  20. 如申請專利範圍第17項所述之方法，其中在該n-通道MOSFET中的該通道的該材料與在該p-通道MOSFET中的該通道的該材料為共同的。
  21. 如申請專利範圍第17項所述之方法，其中在該n-通道MOSFET中的該通道的該共同材料與在該p-通道MOSFET中的該通道的該材料為鍺。
  22. 如申請專利範圍第17項所述之方法，其中個別該閘極電極具有大於100奈米的長度。
  23. 如申請專利範圍第17項所述之方法，其中該n- 通道MOSFET的該通道與該p-通道MOSFET的該通道包含奈米帶。
  24. 一種具有雙軸應變通道的設備，包含：互補金屬氧化物半導體(CMOS)反相器，包含：n-通道金屬氧化物半導體場效電晶體(MOSFET)及p-通道MOSFET，其中在該n-通道MOSFET中的通道的材料與在該p-通道MOSFET中的通道的材料各個受到雙軸應變，其中各個該n-通道MOSFET與該p-通道MOSFET的所述通道係配置在緩衝層上及該緩衝層包含一材料，該材料的晶格常數與在該n-通道MOSFET的該通道材料與在該p-通道MOSFET的該通道材料的晶格常數不同，其中該n-通道MOSFET中的該通道材料與該p-通道MOSFET中的該通道材料各個都是鍺。
  25. 一種具有雙軸應變通道的設備，包含：互補金屬氧化物半導體(CMOS)反相器，包含：n-通道金屬氧化物半導體場效電晶體(MOSFET)及p-通道MOSFET，其中在該n-通道MOSFET中的通道的材料與在該p-通道MOSFET中的通道的材料各個受到雙軸應變，其中各個該n-通道MOSFET與該p-通道MOSFET的所述通道係配置在緩衝層上及該緩衝層包含一材料，該材料的晶格常數與在該n-通道MOSFET的該通道材料與在該p-通道MOSFET的該通道材料的晶格常數不同，其中該緩衝層的材料包含III-V族化合物半導體材料。
  26. 一種反相器，包含： n-通道金屬氧化物半導體場效電晶體(MOSFET)，包含閘極電極、源極區、汲極區及通道；及p-通道MOSFET，包含閘極電極、源極區、汲極區及通道，其中該n-通道MOSFET的該閘極電極耦接至該p-通道MOSFET的該閘極電極；以及，該n-通道MOSFET的該汲極耦接至該p-通道MOSFET的該汲極，其中在該n-通道MOSFET中的該通道的材料與在該p-通道MOSFET中的該通道的材料被選擇為類似材料並受到雙軸應變，及其中各個該n-通道MOSFET與該p-通道MOSFET的該通道配置在緩衝層上，以及，該緩衝層包含一材料，該材料的晶格常數與該n-通道MOSFET的該通道的共同材料與該p-通道MOSFET中的該通道的材料的晶格常數不同，其中在該n-通道MOSFET中的該通道的該共同材料與在該p-通道MOSFET中的該通道的材料為鍺。
  27. 一種反相器，包含：n-通道金屬氧化物半導體場效電晶體(MOSFET)，包含閘極電極、源極區、汲極區及通道；及p-通道MOSFET，包含閘極電極、源極區、汲極區及通道，其中該n-通道MOSFET的該閘極電極耦接至該p-通道MOSFET的該閘極電極；以及，該n-通道MOSFET的該汲極耦接至該p-通道MOSFET的該汲極， 其中在該n-通道MOSFET中的該通道的材料與在該p-通道MOSFET中的該通道的材料被選擇為類似材料並受到雙軸應變，及其中各個該n-通道MOSFET與該p-通道MOSFET的該通道配置在緩衝層上，以及，該緩衝層包含一材料，該材料的晶格常數與該n-通道MOSFET的該通道的共同材料與該p-通道MOSFET中的該通道的材料的晶格常數不同，其中該緩衝層的材料包含III-V族化合物半導體材料。
  28. 一種形成反相器的方法，包含：形成n-通道金屬氧化物半導體場效電晶體(MOSFET)；形成p-通道MOSFET；連接該n-通道MOSFET與該p-通道MOSFET的閘極電極與汲極區；及在基板上形成緩衝層，該緩衝層配置鄰近該n-通道MOSFET的通道與該p-通道MOSFET的通道，該緩衝層包含一材料，該材料的晶格常數與在該n-通道MOSFET中的該通道的材料及在該p-通道MOSFET中的該通道的材料的晶格常數不同，其中在該n-通道MOSFET的該通道之該材料與在該p-通道MOSFET的該通道之該材料受到雙軸應變，其中在該n-通道MOSFET中的該通道的共同材料與在該p-通道MOSFET中的該通道的該材料的各個都是鍺。
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