CN106062953A - 用于CMOS的双轴向拉伸应变的Ge沟道 - Google Patents

用于CMOS的双轴向拉伸应变的Ge沟道 Download PDF

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CN106062953A
CN106062953A CN201380081249.3A CN201380081249A CN106062953A CN 106062953 A CN106062953 A CN 106062953A CN 201380081249 A CN201380081249 A CN 201380081249A CN 106062953 A CN106062953 A CN 106062953A
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channel mosfet
raceway groove
mosfet
channel
gate electrode
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CN106062953B (zh
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P·马吉
N·慕克吉
R·皮拉里塞
W·拉赫马迪
R·S·周
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Abstract

一种装置，包括：互补金属氧化物半导体(CMOS)反相器，该反相器包括n沟道金属氧化物半导体场效应晶体管(MOSFET)；以及p沟道MOSFET，其中，n沟道MOSFET中的沟道的材料和p沟道MOSFET中的沟道的材料经受双轴向拉伸应变。一种方法，包括：形成n沟道金属氧化物半导体场效应晶体管(MOSFET)；形成p沟道MOSFET；以及连接n沟道MOSFET和p沟道MOSFET的栅极电极，并且连接n沟道MOSFET和p沟道MOSFET的漏极区，其中，n沟道MOSFET中的沟道的材料和p沟道MOSFET中的沟道的材料经受双轴向拉伸应变。

Description

用于CMOS的双轴向拉伸应变的Ge沟道
技术领域
半导体器件。
背景技术
对于过去的十几年，集成电路中的部件的缩放已经成为了在日益增长的半导体产业背后的驱动力。缩放至越来越小的部件实现了半导体芯片的有限区域(real estate)上增大密度的功能单元。例如，缩小的晶体管尺寸允许在芯片上含有增加数量的存储器件，引起了具有增大容量的产品的制造。然而，对日益增大的容量的推动并不是没有问题的。对每个器件的性能进行优化的必要性变得日益显著。
期望增加载流子迁移率(超过硅的载流子迁移率)以继续缩放晶体管器件(包括互补金属氧化物半导体(CMOS)反相器)并产生提高的性能和较低的功率。诸如III-V族化合物半导体材料之类的有前途的材料为n沟道金属氧化物半导体场效应晶体管(MOSFET)提供高的电子迁移率，并且锗基材料为p沟道MOSFET提供高的空穴迁移率。由于III-V族化合物半导体材料与锗材料之间的差异，因此在针对亚-10纳米(nm)节点几何结构的高度缩放的CMOS反相器中，在硅上集成两个独立的系统存在重大挑战。此外，期望包括有缓冲层、栅极叠置体、接触部等等的薄膜叠置体对于III-V族化合物半导体和锗是不同的，锗进一步增加了集成用于经缩放的CMOS的这些不同的沟道材料的复杂性。
附图说明
图1示出了CMOS反相器的实施例的俯视、侧视透视图。
图2示出了CMOS反相器的另一个实施例。
图3例示了根据一个实施方式的计算设备。
具体实施方式
描述了半导体器件以及用于形成和使用半导体器件的方法。还描述了CMOS实施方式(CMOS反相器)的n沟道MOSFET和p沟道MOSFET器件的共同集成，其中，每个晶体管器件都包括经受双轴向拉伸应变的沟道材料。在一个实施例中，n沟道MOSFET和p沟道MOSFET由共同的(common)沟道材料构成，该共同的沟道材料经受双轴向拉伸应变。在一个实施例中，共同的材料是锗材料。
图1示出了CMOS反相器的俯视、侧视透视图。在该实施例中，反相器100包括p沟道MOSFET 130和n沟道MOSFET 140。在该实施例中，p沟道MOSFET 130和n沟道MOSFET 140中的每个都是平面器件。在图1中例示出的实施例中，p沟道MOSFET 130和n沟道MOSFET 140中的每个都形成在衬底110上。衬底110例如是单晶硅衬底或绝缘体上硅(SOI)衬底。上层的硅衬底110是缓冲层120。P沟道MOSFET 130和n沟道MOSFET 140分别形成在缓冲层120上，并且例如通过诸如氧化物之类的电介质材料的浅沟槽隔离(STI)结构150分隔开。P沟道MOSFET130包括栅极电极132、源极区134、漏极区135和被布置在源极区134与漏极区135之间、栅极电极132下方的沟道136。栅极电极132通过被布置在沟道之间的栅极电介质(例如，具有大于二氧化硅(高K材料)的介电常数的电介质材料)而与沟道136分隔开。N沟道MOSFET 140包括栅极电极142、源极区144、漏极区145以及被布置在源极区144与漏极区145之间的沟道146。栅极电极142通过被布置在沟道区之间的例如高K电介质材料的栅极电介质而与沟道区分隔开。P沟道MOSFET 130包括适当地掺杂的或构成p型材料的漏极区135、源极区134、以及栅极电极132。N沟道MOSFET 140包括适当地掺杂的或构成n型材料的漏极区145、源极区144、以及栅极电极142。通过如所例示的将p沟道MOSFET 130的漏极区135连接到n沟道MOSFET 140的漏极区145以及连接每个栅极电极来形成CMOS反相器100。
在一个实施例中，缓冲层120被选择为其材料的晶格常数高于p沟道MOSFET 130的沟道136和n沟道MOSFET 140的沟道146的材料的晶格常数。如所例示的，沟道136和沟道146被布置在缓冲层120上。材料之间的晶格常数的差异将在沟道136和沟道146中的每个沟道中产生双轴向拉伸应变。在一个实施例中，用于沟道区136的材料和用于沟道146的材料是共同的。用于这些沟道的代表性的共同的材料是锗。锗中的双轴向拉伸应变针对电子和空穴两者修改其带结构和载流子的有效质量(迁移率)。在一个实施例中，具有大于锗的晶格常数的用于缓冲层120的材料是III-V族化合物半导体材料，例如磷化铟镓(InGaP)。在一个实施例中，双轴向拉伸应变水平大于百分之1.5。
用于形成诸如反相器100之类的CMOS反相器的一种技术是在衬底110上外延地或以其它方式沉积缓冲层120。应当意识到，在锗上施加(impart)至少百分之1.5的双轴向拉伸应变的用于缓冲层120的期望的材料可以类似地在衬底110上施加应变。为了减小或抑制衬底110上的任何应变，可以使用渐变式缓冲层，例如在沟道界面处具有其最大的晶格常数的渐变的III-V族化合物半导体(例如，InGaP)。
在形成缓冲层120之后，例如可以通过外延沉积来形成沟道136和沟道236以及结区(源极区134和漏极区135以及源极区234和漏极区235)。随后可以针对按照期望掺杂的个体器件和每个器件(栅极电极132、栅极电极232)来引入栅极电介质和栅极电极。制造漏极区与电极之间的接触部以形成CMOS反相器。
图2示出了例如在CMOS反相器中的集成的p沟道MOSFET和n沟道MOSFET的另一个实施例。在该实施例中，p沟道MOSFET和n沟道MOSFET均为非平面器件，具体而言，为纳米线或纳米带器件。参考图2，反相器200包括n沟道MOSFET结构230，其包括栅极电极部分232A、232B、232C和232D；源极区234；漏极区235；以及分别被布置在栅极电极之间的沟道236A、236B和236C。CMOS反相器200还包括n沟道MOSFET结构240，其包括栅极电极部分242A、242B、242C和242D；源极区244；漏极区245；以及被布置在栅极电极部分中的相应的栅极电极部分之间的沟道246A、246B和246C。对于p沟道MOSFET结构230，栅极电极部分232A-232D中的每个栅极电极部分都通过诸如高K电介质之类的栅极电介质材料与相应的沟道(沟道236A-236C)分隔开，并且栅极电极和源极区和漏极区被掺杂为p型或构成p型。类似地，n沟道MOSFET 240中的栅极电极部分242A-242D通过栅极电介质材料(例如，高介电常数材料)与沟道246A-246C中的相应的沟道分隔开，并且栅极电极部分和源极区和漏极区被掺杂为n型或构成n型。通过将p沟道MOSFET结构230的漏极区235连接到n沟道MOSFET结构240的漏极区245以及连接该结构的栅极电极来例示CMOS反相器。
在一个实施例中，用于p沟道MOSFET结构230的沟道236A-236C的材料和用于n沟道MOSFET结构240的沟道246A-246C的材料均经受双轴向拉伸应变。在一个实施例中，用于p沟道MOSFET结构230和n沟道MOSFET结构240两者的这些沟道的材料是共同的或相同的。代表性的材料是锗。在一个实施例中，通过栅极电极部分在沟道上施加双轴向拉伸应变。用于栅极电极的代表性材料包括氮化钛(TiN)和氮化钽(TaN)。对于如图2中所示由纳米带构件构成的沟道，在一个实施例中，该纳米带沟道具有大约15纳米或更小的厚度。为了在纳米带沟道上施加双轴向拉伸应变，在一个实施例中，栅极电极部分具有大于100纳米的长度。在另一个实施例中，源极区和漏极区充当保留沟道中的应变的锚件。用于源极区和漏极区(源极区234、漏极区235、源极区244、漏极区245)的材料和/或被布置在栅极电极部分与源极区和漏极区之间的任何间隔体材料施加应变或用于保留应变。
图2中的结构可以以多种方式形成。一种技术是当在诸如硅之类的牺牲材料层之间交替锗外延层时，对纳米带/纳米线沟道236A-236C和246A-246C进行图案化。随后可以去除牺牲层以留下悬接在衬底上和上方的支撑件之间的不同平面中的纳米带(236A-236C或246A-246C)。此时，例如可以通过适当地掺杂悬接的纳米线的支撑件来形成源极区和漏极区。随后可以在引入栅极电极材料之后，在纳米线中的每条纳米线周围引入诸如高K电介质材料之类的电介质材料。在一个实施例中，可以引入牺牲栅极电极并对其进行图案化，并随后以期望的栅极电极材料来替换牺牲栅极电极。还可以在纳米带沟道与源极区和漏极区之间增加间隔体。为了形成CMOS反相器，可以制造接触部，并且连接在p沟道MOSFET的漏极与n沟道MOSFET的漏极之间并且连接在器件的栅极之间。
以上描述参照了CMOS反相器的两个结构实施例。将意识到，从可以制造各种不同的结构实施例的意义上而言，不必限制特定的结构实施例，在这些实施例中，在CMOS反相器的p沟道MOSFET的沟道和n沟道MOSFET的沟道中的每个沟道上施加双轴向拉伸应变，并且沟道中的每个沟道都具有共同的材料(例如，锗)。因此，预期到诸如多栅极器件和多桥接沟道器件之类的其它结构实施例。
图3例示了根据一个实施方式的计算设备300。计算设备300容纳板302。板302可以包括多个组件，包括，但不限于，处理器304和至少一个通信芯片306。处理器304物理和电气地耦合到板302。在某些实施方式中，至少一个通信芯片306也物理和电气地耦合到板302。在另外的实施方式中，通信芯片306是处理器304的部分。
取决于其应用，计算设备300可以包括其它组件，这些组件可以物理和电气地耦合到板302，也可以不存在这样的耦合。这些其它组件包括，但不限于，易失性存储器(例如，DRAM)、非易失性存储器(例如，ROM)、闪存、图形处理器、数字信号处理器、密码协处理器、芯片组、天线、显示器、触摸屏显示器、触摸屏控制器、电池、音频编解码器、视频编解码器、功率放大器、全球定位系统(GPS)设备、罗盘、加速度计、陀螺仪、扬声器、照相机、以及大容量储存设备(例如，硬盘驱动、压缩盘(CD)、数字多功能盘(DVD)等等)。
通信芯片306实现了无线通信，以便将数据传送到计算设备300以及从计算设备300传送数据。术语“无线”及其派生词可用于描述可通过使用经由非固态介质的经调制的电磁辐射来传送数据的电路、设备、系统、方法、技术、通信信道等。该术语并不暗示所关联的设备不包含任何线，尽管在某些实施例中它们可能不含有。通信芯片306可以实施多个无线标准或协议中的任何标准或协议，这些标准或协议包括，但不限于，Wi-Fi(IEEE 802.11系列)、WiMAX(IEEE 802.16系列)、IEEE 802.20、长期演进(LTE)、Ev-DO、HSPA+、HSDPA+、HSUPA+、EDGE、GSM、GPRS、CDMA、TDMA、DECT、蓝牙、及其衍生物，以及被命名为3G、4G、5G及更高的任何其它无线协议。计算设备300可以包括多个通信芯片306。例如，第一通信芯片306可以专用于较短距离无线通信(例如，Wi-Fi和蓝牙)，并且第二通信芯片306可以专用于较长距离无线通信(例如，GPS、EDGE、GPRS、CDMA、WiMAX、LTE、Ev-DO以及其它)。
计算设备300的处理器304包括封装在处理器304内的集成电路管芯。在本发明的某些实施方式中，处理器的集成电路管芯包括如上面所描述的一个或多个器件，例如，例如公共材料(例如，锗)的双轴向拉伸应变的晶体管器件的一个或多个CMOS反相器。术语“处理器”可以指代对来自寄存器和/或存储器的电子数据进行处理以便将该电子数据转换成可以储存在寄存器和/或存储器中的其它电子数据的任何器件或器件的一部分。
通信芯片306还包括封装在通信芯片306内的集成电路管芯。根据另一种实施方式，通信芯片的集成电路管芯包括根据上面所描述的实施方式所形成的一个或多个器件，例如CMOS反相器。
在另外的实施方式中，在计算设备300内所容纳的另一个组件可以包括集成电路管芯，该集成电路管芯包括根据上面所描述的实施方式所形成的一个或多个器件，例如CMOS反相器。
在各种实施方式中，计算设备300可以是膝上型计算机、上网本、笔记本、超极本、智能电话、平板电脑、个人数字助理(PDA)、超级移动PC、移动电话、台式计算机、服务器、打印机、扫描仪、监视器、机顶盒、娱乐控制单元、数码相机、便携式音乐播放器、或数字视频录像机。在另外的实施方式中，计算设备300可以是处理数据的任何其它电子设备.
示例
以下示例涉及实施例。
示例1是一种装置，该装置包括互补金属氧化物半导体(CMOS)反相器，该反相器包括n沟道金属氧化物半导体场效应晶体管(MOSFET)和p沟道MOSFET，其中，n沟道MOSFET中的沟道的材料和p沟道MOSFET中的沟道的材料均经受双轴向拉伸应变。
在示例2中，示例1的装置的n沟道MOSFET中的沟道的材料和p沟道MOSFET中的沟道的材料是相同的。
在示例3中，示例1的装置的n沟道MOSFET中的沟道的材料和p沟道MOSFET中的沟道的材料均是锗。
在示例4中，示例1的装置的n沟道MOSFET和p沟道MOSFET中的每个MOSFET的沟道都被布置在缓冲层上，并且缓冲层包括具有比n沟道MOSFET中的沟道的材料和p沟道MOSFET中的沟道的材料的晶格常数大的晶格常数的材料。
在示例5中，示例4的装置的缓冲层的材料包括III-V族化合物半导体材料。
在示例6中，示例4的装置的n沟道MOSFET和p沟道MOSFET是平面晶体管。
在示例7中，示例1的装置的n沟道MOSFET中的沟道的材料和p沟道MOSFET中的沟道的材料的晶格常数均小于相应的栅极电极的材料的晶格常数。
在示例8中，示例7的装置的相应的栅极电极具有大于100纳米的长度。
示例9是一种装置，该装置包括n沟道金属氧化物半导体场效应晶体管(MOSFET)，其包括栅极电极、源极区、漏极区和沟道；以及p沟道MOSFET，其包括栅极电极、源极区、漏极区和沟道，其中，n沟道MOSFET的栅极电极耦合到p沟道MOSFET的栅极电极，并且n沟道MOSFET的漏极耦合到p沟道MOSFET的漏极，并且其中，n沟道MOSFET中的沟道的材料和p沟道MOSFET中的沟道的材料是共同的，并且经受双轴向拉伸应变。
在示例10中，示例9的装置中的n沟道MOSFET中的沟道和p沟道MOSFET中的沟道的共同的材料是锗。
在示例11中，示例9的装置中的n沟道MOSFET和p沟道MOSFET中的每个MOSFET的沟道都被布置在缓冲层上，并且缓冲层包括具有比n沟道MOSFET中的沟道和p沟道MOSFET中的沟道的共同的材料的晶格常数大的晶格常数的材料。
在示例12中，示例11的装置中的缓冲层的材料包括III-V族化合物半导体材料。
在示例13中，示例11的装置的n沟道MOSFET和p沟道MOSFET是平面晶体管。
在示例14中，示例9的装置中的n沟道MOSFET中的沟道和p沟道MOSFET中的沟道的共同的材料的晶格常数小于相应的栅极电极的材料的晶格常数。
在示例15中，示例14的装置中的栅极电极具有大于100纳米的长度。
在示例16中，示例14的装置中的n沟道MOSFET的沟道和p沟道MOSFET的沟道包括纳米带。
示例17是一种方法，该方法包括形成n沟道金属氧化物半导体场效应晶体管(MOSFET)；形成p沟道MOSFET；以及连接n沟道MOSFET和p沟道MOSFET的栅极电极，并且连接n沟道MOSFET和p沟道MOSFET的漏极区，其中，n沟道MOSFET中的沟道的材料和p沟道MOSFET中的沟道的材料经受双轴向拉伸应变。
在示例18中，示例17的装置中的n沟道MOSFET中的沟道的材料和p沟道MOSFET中的沟道的材料是共同的。
在示例19中，示例17的方法还包括在衬底上形成缓冲层，该缓冲层被布置为邻近n沟道MOSFET的沟道和p沟道MOSFET的沟道，该缓冲层的晶格常数大于n沟道MOSFET中的沟道和p沟道MOSFET中的沟道的共同的材料的晶格常数。
在示例20中，在示例17的方法中的n沟道MOSFET中的沟道和p沟道MOSFET中的沟道的共同的材料是锗。
在示例21中，在示例17的方法中的n沟道MOSFET中的沟道和p沟道MOSFET中的沟道的共同的材料的晶格常数均小于相应的栅极电极的材料的晶格常数。
在示例22中，示例21的方法中的相应的栅极电极具有大于100纳米的长度。
在示例23中，示例21的方法中的n沟道MOSFET的沟道和p沟道MOSFET的沟道包括纳米带。
在以上描述中，出于解释的目的，已经阐述了许多具体细节，以便提供对实施例的透彻理解。然而，对本领域技术人员将显而易见的是，可以在没有这些具体细节中的某些具体细节的情况下，实施一个或多个其它实施例。所描述的具体实施例并非被提供为限制本发明而是为了例示本发明。本发明的范围并不由上面提供的特定示例来确定，而仅仅由所附权利要求来确定。在其它实例中，已经以框图形式示出或者未详细示出公知的结构、器件、和操作，以免使本说明书难以理解。在认为适当的情况下，在附图中重复了附图标记或附图标记的端部，以指示对应的或相似的元件，这些元件可以可选地具有类似的特征。
还应当意识到，贯穿本说明书例如对“一个实施例”、“实施例”、“一个或多个实施例”、或“不同的实施例”的引用表示可以被包括在对本发明的实施中的特定特征。类似地，应当意识到，在说明书中，为了简化本公开内容并帮助理解各创造性方面，有时在单个实施例、附图或者对其描述中将各特征组合在一起。然而，本公开内容的该方法不应当被解释为反映本发明需要比在每个权利要求中明确记载的特征更多的特征的意图。相反，如所附权利要求反映的，创造性方面可以在于少于单个公开的实施例的所有特征中。因此，在具体实施方式之前的权利要求在此被明确并入到该具体实施方式中，其中每个权利要求都代表其自身作为本发明的独立的实施例。

Claims (23)

1.一种装置，包括：
互补金属氧化物半导体(CMOS)反相器，所述CMOS反相器包括n沟道金属氧化物半导体场效应晶体管(MOSFET)和p沟道MOSFET，其中，所述n沟道MOSFET中的沟道的材料和所述p沟道MOSFET中的沟道的材料均经受双轴向拉伸应变。
2.根据权利要求1所述的装置，其中，所述n沟道MOSFET中的沟道的材料和所述p沟道MOSFET中的沟道的材料是相同的。
3.根据权利要求1所述的装置，其中，所述n沟道MOSFET中的沟道的材料和所述p沟道MOSFET中的沟道的材料均是锗。
4.根据权利要求1所述的装置，其中，所述n沟道MOSFET和所述p沟道MOSFET中的每个MOSFET的沟道都被布置在缓冲层上，并且所述缓冲层包括具有比所述n沟道MOSFET中的沟道的材料和所述p沟道MOSFET中的沟道的材料的晶格常数大的晶格常数的材料。
5.根据权利要求4所述的装置，其中，所述缓冲层的材料包括III-V族化合物半导体材料。
6.根据权利要求4所述的装置，其中，所述n沟道MOSFET和所述p沟道MOSFET是平面晶体管。
7.根据权利要求1所述的装置，其中，所述n沟道MOSFET中的沟道的材料和所述p沟道MOSFET中的沟道的材料的晶格常数均小于相应的栅极电极的材料的晶格常数。
8.根据权利要求7所述的装置，其中，所述相应的栅极电极具有大于100纳米的长度。
9.一种装置，包括：
n沟道金属氧化物半导体场效应晶体管(MOSFET)，所述n沟道MOSFET包括栅极电极、源极区、漏极区和沟道；以及
p沟道MOSFET，所述p沟道MOSFET包括栅极电极、源极区、漏极区和沟道，
其中，所述n沟道MOSFET的栅极电极耦合到所述p沟道MOSFET的栅极电极，并且所述n沟道MOSFET的漏极耦合到所述p沟道MOSFET的漏极，并且
其中，所述n沟道MOSFET中的沟道的材料和所述p沟道MOSFET中的沟道的材料是共同的，并且经受双轴向拉伸应变。
10.根据权利要求9所述的装置，其中，所述n沟道MOSFET中的沟道和所述p沟道MOSFET中的沟道的共同的材料是锗。
11.根据权利要求1所述的装置，其中，所述n沟道MOSFET和所述p沟道MOSFET中的每个MOSFET的沟道都被布置在缓冲层上，并且所述缓冲层包括具有比所述n沟道MOSFET中的沟道和所述p沟道MOSFET中的沟道的所述共同的材料的晶格常数大的晶格常数的材料。
12.根据权利要求11所述的装置，其中，所述缓冲层的材料包括III-V族化合物半导体材料。
13.根据权利要求11所述的装置，其中，所述n沟道MOSFET和所述p沟道MOSFET是平面晶体管。
14.根据权利要求9所述的装置，其中，所述n沟道MOSFET中的沟道和所述p沟道MOSFET中的沟道的共同的材料的晶格常数小于相应的栅极电极的材料的晶格常数。
15.根据权利要求14所述的装置，其中，所述栅极电极具有大于100纳米的长度。
16.根据权利要求14所述的装置，其中，所述n沟道MOSFET的沟道和所述p沟道MOSFET的沟道包括纳米带。
17.一种方法，所述方法包括：
形成n沟道金属氧化物半导体场效应晶体管(MOSFET)；
形成p沟道MOSFET；以及
连接所述n沟道MOSFET和所述p沟道MOSFET的栅极电极，并且连接所述n沟道MOSFET和所述p沟道MOSFET的漏极区，
其中，所述n沟道MOSFET中的沟道的材料和所述p沟道MOSFET中的沟道的材料经受双轴向拉伸应变。
18.根据权利要求17所述的方法，所述n沟道MOSFET中的沟道的材料和所述p沟道MOSFET中的沟道的材料是共同的。
19.根据权利要求17所述的方法，其中，所述方法还包括：在所述衬底上形成缓冲层，所述缓冲层被布置为邻近所述n沟道MOSFET的沟道和所述p沟道MOSFET的沟道，所述缓冲层的晶格常数大于所述n沟道MOSFET中的沟道和所述p沟道MOSFET中的沟道的共同的材料的晶格常数。
20.根据权利要求17所述的方法，其中，所述n沟道MOSFET中的沟道和所述p沟道MOSFET中的沟道的共同的材料是锗。
21.根据权利要求17所述的方法，其中，所述n沟道MOSFET中的沟道和所述p沟道MOSFET中的沟道的共同的材料的晶格常数均小于相应的栅极电极的材料的晶格常数。
22.根据权利要求21所述的方法，其中，所述相应的栅极电极具有大于100纳米的长度。
23.根据权利要求21所述的方法，其中，所述n沟道MOSFET的沟道和所述p沟道MOSFET的沟道包括纳米带。
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Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11450527B2 (en) 2016-07-02 2022-09-20 Intel Corporation Engineering tensile strain buffer in art for high quality Ge channel
WO2019005111A1 (en) * 2017-06-30 2019-01-03 Intel Corporation VARIOUS TRANSISTOR CHANNEL MATERIALS ACTIVATED BY A REVERSE GRADIENT GERMANIUM THIN LAYER
US11056592B2 (en) 2017-06-30 2021-07-06 Intel Corporation Silicon substrate modification to enable formation of thin, relaxed, germanium-based layer
KR102045989B1 (ko) 2018-03-14 2019-11-18 한국과학기술연구원 상호 확산을 사용한 반도체 소자 및 이를 제조하는 방법
US11450739B2 (en) 2018-09-14 2022-09-20 Intel Corporation Germanium-rich nanowire transistor with relaxed buffer layer
US11276694B2 (en) * 2018-09-24 2022-03-15 Intel Corporation Transistor structure with indium phosphide channel
US11355625B2 (en) * 2020-07-23 2022-06-07 Delta Electronics, Inc. Device and semiconductor structure for improving the disadvantages of p-GaN gate high electron mobility transistor
US20230170420A1 (en) * 2021-11-29 2023-06-01 Intel Corporation Strained semiconductor on insulator (ssoi) based gate all around (gaa) transistor structures

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20040135138A1 (en) * 2003-01-15 2004-07-15 Sharp Laboratories Of America, Inc. System and method for isolating silicon germanium dislocation regions in strained-silicon CMOS applications
CN1979787A (zh) * 2005-10-31 2007-06-13 国际商业机器公司 半导体器件及其形成方法
US20080179628A1 (en) * 2007-01-31 2008-07-31 Andy Wei Transistor with embedded silicon/germanium material on a strained semiconductor on insulator substrate
CN101341597A (zh) * 2005-10-31 2009-01-07 飞思卡尔半导体公司 半导体结构形成方法和该结构

Family Cites Families (29)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5198687A (en) * 1992-07-23 1993-03-30 Baliga Bantval J Base resistance controlled thyristor with single-polarity turn-on and turn-off control
US5323044A (en) * 1992-10-02 1994-06-21 Power Integrations, Inc. Bi-directional MOSFET switch
US5770485A (en) * 1997-03-04 1998-06-23 Advanced Micro Devices, Inc. MOSFET device with an amorphized source and fabrication method thereof
US6040220A (en) * 1997-10-14 2000-03-21 Advanced Micro Devices, Inc. Asymmetrical transistor formed from a gate conductor of unequal thickness
US5943562A (en) * 1997-10-14 1999-08-24 Advanced Micro Devices, Inc. Semiconductor fabrication employing a transistor gate coupled to a localized substrate
JP3403076B2 (ja) * 1998-06-30 2003-05-06 株式会社東芝 半導体装置及びその製造方法
US6864149B2 (en) * 2003-05-09 2005-03-08 Taiwan Semiconductor Manufacturing Company SOI chip with mesa isolation and recess resistant regions
US7812340B2 (en) * 2003-06-13 2010-10-12 International Business Machines Corporation Strained-silicon-on-insulator single-and double-gate MOSFET and method for forming the same
US6927414B2 (en) * 2003-06-17 2005-08-09 International Business Machines Corporation High speed lateral heterojunction MISFETs realized by 2-dimensional bandgap engineering and methods thereof
US7101742B2 (en) * 2003-08-12 2006-09-05 Taiwan Semiconductor Manufacturing Company, Ltd. Strained channel complementary field-effect transistors and methods of manufacture
US20050116360A1 (en) * 2003-12-01 2005-06-02 Chien-Chao Huang Complementary field-effect transistors and methods of manufacture
US7662689B2 (en) * 2003-12-23 2010-02-16 Intel Corporation Strained transistor integration for CMOS
US7023018B2 (en) * 2004-04-06 2006-04-04 Texas Instruments Incorporated SiGe transistor with strained layers
TWI463526B (zh) * 2004-06-24 2014-12-01 Ibm 改良具應力矽之ｃｍｏｓ元件的方法及以該方法製備而成的元件
US7227205B2 (en) * 2004-06-24 2007-06-05 International Business Machines Corporation Strained-silicon CMOS device and method
US7282402B2 (en) 2005-03-30 2007-10-16 Freescale Semiconductor, Inc. Method of making a dual strained channel semiconductor device
US8324660B2 (en) * 2005-05-17 2012-12-04 Taiwan Semiconductor Manufacturing Company, Ltd. Lattice-mismatched semiconductor structures with reduced dislocation defect densities and related methods for device fabrication
US20070148939A1 (en) * 2005-12-22 2007-06-28 International Business Machines Corporation Low leakage heterojunction vertical transistors and high performance devices thereof
US20080124858A1 (en) * 2006-08-07 2008-05-29 Bich-Yen Nguyen Selective stress relaxation by amorphizing implant in strained silicon on insulator integrated circuit
US8178446B2 (en) 2007-03-30 2012-05-15 Tokyo Electron Limited Strained metal nitride films and method of forming
US8003454B2 (en) * 2008-05-22 2011-08-23 Freescale Semiconductor, Inc. CMOS process with optimized PMOS and NMOS transistor devices
KR20100081667A (ko) * 2009-01-07 2010-07-15 삼성전자주식회사 스트레인드 채널을 갖는 반도체 장치 및 그 제조 방법
US8048791B2 (en) * 2009-02-23 2011-11-01 Globalfoundries Inc. Method of forming a semiconductor device
DE102009023237B4 (de) * 2009-05-29 2013-11-28 Globalfoundries Dresden Module One Limited Liability Company & Co. Kg Verfahren zum Herstellen von Transistorelementen mit unterschiedlicher Verformung und Halbleiterbauelement
US20110248322A1 (en) * 2010-04-12 2011-10-13 Taiwan Semiconductor Manufacturing Company, Ltd. Piezoelectric Gate-Induced Strain
US8859348B2 (en) * 2012-07-09 2014-10-14 International Business Machines Corporation Strained silicon and strained silicon germanium on insulator
US8890120B2 (en) * 2012-11-16 2014-11-18 Intel Corporation Tunneling field effect transistors (TFETs) for CMOS approaches to fabricating N-type and P-type TFETs
US20140246696A1 (en) * 2013-03-04 2014-09-04 Globalfoundries Inc. Transistor with embedded strain-inducing material formed in cavities formed in a silicon/germanium substrate
US9214395B2 (en) * 2013-03-13 2015-12-15 United Microelectronics Corp. Method of manufacturing semiconductor devices

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20040135138A1 (en) * 2003-01-15 2004-07-15 Sharp Laboratories Of America, Inc. System and method for isolating silicon germanium dislocation regions in strained-silicon CMOS applications
US6903384B2 (en) * 2003-01-15 2005-06-07 Sharp Laboratories Of America, Inc. System and method for isolating silicon germanium dislocation regions in strained-silicon CMOS applications
CN1979787A (zh) * 2005-10-31 2007-06-13 国际商业机器公司 半导体器件及其形成方法
CN101341597A (zh) * 2005-10-31 2009-01-07 飞思卡尔半导体公司 半导体结构形成方法和该结构
US20080179628A1 (en) * 2007-01-31 2008-07-31 Andy Wei Transistor with embedded silicon/germanium material on a strained semiconductor on insulator substrate
TWI408751B (zh) * 2007-01-31 2013-09-11 Globalfoundries Us Inc 具有在應變之絕緣體上覆半導體基板上之嵌入的矽／鍺材料的電晶體

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