TWI617033B - 單軸應變奈米線結構（二） - Google Patents

單軸應變奈米線結構（二） Download PDF

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TWI617033B
TWI617033B TW105116475A TW105116475A TWI617033B TW I617033 B TWI617033 B TW I617033B TW 105116475 A TW105116475 A TW 105116475A TW 105116475 A TW105116475 A TW 105116475A TW I617033 B TWI617033 B TW I617033B
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nanowire
channel region
separation channel
uniaxial
strain
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TW201717397A (zh
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史蒂芬Ｍ 席
金世淵
安娜麗莎 卡佩拉尼
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英特爾公司
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Abstract

本文已描述單軸應變奈米線結構。舉例來說，一半導體裝置包括設置於一基材上方之多個垂直堆疊的單軸應變奈米線。該等單軸應變奈米線之每一者包括設置於該單軸應變奈米線中之一分離通道區域。該分離通道區域具有沿著該單軸應變的方向之一電流流動方向。源極和汲極區域係設置於該奈米線中且在該分離通道區域的兩側之任一側。一閘極電極堆疊完全環圍該等分離通道區域。

Description

單軸應變奈米線結構(二) 發明領域
本發明之實施例係奈米線半導體裝置之領域，特別是單軸應變奈米線結構。
發明背景
在過去數十年，尺寸化(scaling)積體電路內的形貌體已經是一永遠成長的半導體工業背後之一推進力量。尺寸化成更小又更小的形貌體使半導體晶片之有限真實狀態上的功能單元之密度增加。舉例來說，縮小電晶體尺寸允許在一晶片上併入一增加數量的記憶體裝置、給予產品之製造有增加的容量。然而，推進更為多的容量是不是沒有問題的。對於最佳化各個裝置的功能之必要性變得更增重要。
由於微電子裝置大小尺寸超過15奈米(nm)點，維持移動性改進和短通道控制提供裝置製造中的一挑戰。用來製造裝置的奈米線提供改良的短通道控制。舉例來說，矽鍺(SixGe1-x)奈米線通道結構(其中x<0.5)提供在可觀Eg上之行動性增強，Eg係適合用於利用較高電壓操作之許多傳統產品中。更進一步地，矽鍺(SixGe1-x)奈米 線通道(其中x>0.5)提供在較低的Egs(其適合在例如行動/手持領域中的低電壓產品)之行動性增進。
許多不同技術已試圖改良電晶體的移動性。然而，在針對半導體裝置之電子及/或電洞遷移性之領域中仍需要顯著的改良。
發明概要
本發明之實施例包括單軸應變奈米線結構。
在一實施例中，一半導體裝置包括設置於一基材上方之多個垂直堆疊的單軸應變奈米線。該等單軸應變奈米線之每一者包括設置於該單軸應變奈米線中之一分離通道區域。該分離通道區域具有沿著該單軸應變的方向之一電流流動方向。源極和汲極區域係設置於該奈米線中且在該分離通道區域的兩側之任一側。一閘極電極堆疊係完全環圍該等分離通道區域。
在另一實施例中，一半導體結構包括一第一半導體裝置，其包括設置在一基材上方之一第一奈米線。該第一奈米線具有單軸拉伸應變且包括一分離通道區域與在該分離通道區域的兩側之任一側之源極和汲極區域。該分離通道區域具有沿著該單軸拉伸應變的方向之一電流流動方向。該第一半導體裝置亦包括完全環圍該第一奈米線的該分離通道區域之一第一閘極電極堆疊。該半導體結構也包括一第二半導體裝置，其包括設置在該基材上方之一第二奈米線。該第二奈米線具有單軸壓縮應變且包含一分離通 道區域與在該分離通道區域的兩側之任一側之源極和汲極區域。該分離通道區域具有沿著該單軸壓縮應變的方向之一電流流動方向。該第二半導體裝置亦包括完全環圍該第二奈米線的該分離通道區域之一第二閘極電極堆疊。
在另一實施例中，一製造奈米線半導體結構之方法包括在一基材上方形成一第一主動層，該第一主動層具有一第一晶格常數。一第二主動層係在該第一主動層上形成，該第二主動層具有大於該第一晶格常數之一第二晶格常數。具有單軸拉伸應變之一第一奈米線係自該第一主動層形成。該第一奈米線包括一分離通道區域與在該分離通道區域的兩側之任一側之源極和汲極區域。該分離通道區域具有沿著該單軸拉伸應變的方向之一電流流動方向。具有單軸壓縮應變之一第二奈米線係自該第二主動層形成。該第二奈米線包括一分離通道區域與在該分離通道區域的兩側之任一側之源極和汲極區域。該分離通道區域具有沿著該單軸壓縮應變的方向之一電流流動方向。一第一閘極電極堆疊係遭形成以完全環圍該第一奈米線的該分離通道區域。一第二閘極電極堆疊係遭形成以完全環圍該第二奈米線的該分離通道區域。
在另一實施例中，一PMOS半導體裝置包括設置於一基材上方且具有單軸壓縮應變之一奈米線。該奈米線包括一分離通道區域，其具有沿著該單軸壓縮應變的方向之一電流流動方向。該奈米線亦包括設置在該分離通道區域的兩側之任一側之P型源極和汲極區域。一P型閘極電極 堆疊完全環圍該分離通道區域。
100‧‧‧半導體裝置
102、402、402A、512‧‧‧基材
104、104A~104C、104-1、104-2‧‧‧奈米線
106‧‧‧通道區域
108、430、432‧‧‧閘極電極堆疊
110、112‧‧‧源極/汲極區域
114、434‧‧‧接觸點
116、422‧‧‧間隔件
118‧‧‧半導體材料
400‧‧‧初始結構
402B‧‧‧二氧化矽層
404、408‧‧‧矽層
406、410‧‧‧矽鍺層
412‧‧‧鰭狀結構
414A~414C‧‧‧犧牲閘極
416‧‧‧犧牲閘極氧化層
418‧‧‧犧牲多晶矽閘極層
420‧‧‧區域
424‧‧‧介層介電層
426、428‧‧‧溝槽
502‧‧‧鬆弛矽鍺緩衝層
504、508‧‧‧應變矽層
506、510‧‧‧應變矽鍺層
600‧‧‧運算裝置
602‧‧‧板件
604‧‧‧處理器
606‧‧‧通訊晶片
L‧‧‧長度
根據本發明之一實施例，圖1A繪示一奈米線為基礎的半導體結構之一個三維截面檢視圖。
根據本發明之一實施例，圖1B繪示圖1A的該奈米線為基礎的半導體結構當沿著該a-a’軸之一截面通道檢視圖。
根據本發明之一實施例，圖1C繪示圖1A的該奈米線為基礎的半導體結構當沿著該b-b’軸之一截面間隔件檢視圖。
根據本發明之一實施例，圖2繪示具有壓縮單軸應變之一奈米線的一角度檢視圖。
根據本發明之一實施例，圖3繪示具有拉伸單軸應變之一奈米線的一角度檢視圖。
根據本發明之一實施例，圖4A~4F繪示代表於製造一奈米線半導體結構的一方法中的各種操作之三維截面圖。
根據本發明之一實施例，圖5繪示另一個奈米線為基礎的半導體結構之一個三維截面檢視圖。
圖6繪示根據本發明之一實作之一運算裝置。
較佳實施例之詳細說明
單軸應變奈米線結構係或描述。在接下來的敘述中，為了提供本發明之實施例的一通透了解，提出眾多 特定細節，例如特定奈米線整合和材料形態。對於熟於此技者將會明顯的是，本發明之實施例可不需這些特定細節而實現。在其他例子中，為了不要使本發明之實施例不必要地晦澀難懂，例如積體電路設計布局之周知形貌體不會詳細描述。更進一步地，應了解的是在圖式中所顯示的各種實施例係為例示性代表且不必然依比例繪出。
本發明之一或更多實施例係針對改進NMOS或PMOS電晶體或兩者之通道遷移性。遷移性可例如在該通道區域中利用應變而獲改進。因此，下文描述的一或更多方式提供針對NMOS和PMOS電晶體兩者之該通道區域中的合適應變。在一實施例中，提供應變的NMOS和PMOS奈米線。
一應變絕緣體上矽堆疊可被用來作為一起始點以供製造具有應變通道區域之奈米線為基礎的裝置。舉例來說，在一實施例中，此一基材的一應變矽層矽被用來作為一第一主動層。然後利用具有比用於製造該初始應變絕緣體上矽基材高的一較高Ge%之矽鍺(SiGe)，於該第一主動層上形成一第二主動層。當將包括該等第一和第二主動層的堆疊圖案化時，該SiGe層之剩餘部分具有沿著鰭片的電流方向之壓縮單軸壓力，而該矽層的剩餘部分具有沿著該鰭片的該電流方向之拉伸單軸壓力。在一替代金屬閘極操作中，矽(針對PMOS裝置而言)或SiGe(針對NMOS裝置而言)中的任一者係從該鰭片堆疊移除，以製造具有一閘極環繞結構(gate-all-around structure)之奈米線。上 述方式以及用以形成應變的奈米線圍基礎的裝置之其他方式，係與圖式關聯地於下文更詳細地描述。
舉例來說，圖1A繪示一奈米線為基礎的半導體結構之一個三維截面檢視圖。圖1B繪示圖1A的該奈米線為基礎的半導體結構當沿著該a-a’軸之一截面通道檢視圖。圖1C繪示圖1A的該奈米線為基礎的半導體結構當沿著該b-b’軸之一截面間隔件檢視圖。
參照圖1A，一半導體裝置100包括設置在一基材102上方之一或更多個垂直堆疊的奈米線(例如104組)。本文的實施例係目標針對於單一線體裝置和多重線體裝置兩者。如同一範例，具有奈米線104A、104B和104C之一個三奈米線為基礎的裝置係為例示的目的而顯示。為了描述之方便，奈米線104A係被用來作為一範例，其中描述係著重於該等奈米線中的一者。要了解的是，描述一奈米線的特性時，基於多條奈米線之實施例針對該等奈米線之每一者可具有相同的特性。
該等奈米線104中的每一者包括設置於該奈米線中的一通道區域106。該通道區域106具有一長度(L)。參照圖1B，該通道區域也具有與該長度(L)正交之一周邊。參照圖1A和1B兩者，一閘極電極堆疊108環圍該等通道區域106中的每一者之全部的周邊。該閘極電極堆疊108包括一閘極電極，以及設置在該通道區域106和該閘極電極(未繪出)之間的一閘極介電層。該通道區域係分離於其完全地被該閘極電極堆疊108所環圍，且沒有例如下層基材材 料或上層通道製造材料之任何介入材料。於是，在具有多條奈米線104的實施例中，如同圖1B中所描繪者，該等奈米線之該等通道區域106亦會相對於彼此分離。
再次參照圖1A，該等奈米線104之每一者亦包括設置在該通道區域104的兩側之任一側上的該奈米線中之源極和汲極區域110和112。一對接觸點114係設置於源極/汲極區域110/112上方。在一特定的實施例中，如圖1A所描繪者，該對接觸點114環圍該等源極/汲極區域110/112的整個周邊。也就是說，在一實施例中，該等源極/汲極區域110/112係分離，其中其等被接觸點114所完全環圍且沒有例如下層基材材料或上層通道製造材料之任何介入材料。於是，在具有多條奈米線104的此一實施例中，該等奈米線之該等源極/汲極區域110/112亦會相對於彼此分離。
再次參照圖1A，在一實施例中，該半導體裝置100進一步包括一對間隔件116。該等間隔件116係設置在該閘極電極堆疊108以及該對接觸點114之間。如上文所述，該等通道區域與源極/汲極區域在至少數個實施例中，是被製成分離。然而，並非奈米線104的所有區域均需要為分離，或甚至能夠被製成分離。舉例來說，參照圖1C，奈米線104A-104C在間隔件116下方的位置處並未分離。在一實施例中，奈米線104A-104C的堆疊具有介於其間之介入半導體材料118，例如介入於矽奈米線之間的矽鍺，或反之亦然，如同下文與圖4A至4F所關聯描述者。在 一實施例中，該底部奈米線104A仍與基材102的一部分接觸，例如與設置在一主體(bulk)基材上的一絕緣層部分接觸。因此，在一實施例中，在該等間隔件的一或兩者下面的多個垂直堆疊的奈米線之一部分為非分離。
根據本發明之一實施例，該半導體裝置之一或更多奈米線為單軸應變奈米線。因此，如同圖1A所描繪者，一半導體裝置可由一單一單軸應變奈米線(例如104A)或由多條垂直堆疊的單軸應變奈米線(104A-104C)所製造。該單軸應變奈米線或多條奈米線可為以拉伸應變或壓縮應變之單軸應變。舉例來說，根據本發明之一或更多實施例，圖2繪示具有壓縮單軸應變之一奈米線的一角度檢視圖，而圖3繪示具有拉伸單軸應變之一奈米線的一角度檢視圖。
參照圖2，一奈米線104-1具有設置於其中之一分離通道區域(C)。一源極區域(S)和一汲極區域(D)係設置於該奈米線104-1中，且在該通道區域(C)中的兩側之任一側上。該奈米線104-1的該分離通道區域具有沿著一單軸壓縮應變的方向(箭頭指向另一者)、從該源極區域(S)至該汲極區域(D)之一電流流動方向。在一實施例中，具有單軸壓縮應變之該單軸應變奈米線104-1係由矽鍺(SixGey，其中0<x<100且0<y<100)構成。在一特定此種實施例中，x係大約為30且y係大約為70。在一實施例中，一個PMOS半導體裝置係由具有該單軸壓縮應變之奈米線104-1所製造。
參照圖3，一奈米線104-2具有設置於其中之一分離通道區域(C)。一源極區域(S)和一汲極區域(D)係設置於該奈米線104-2中，且在該通道區域(C)中的兩側之任一側上。該奈米線104-2的該分離通道區域具有沿著一單軸拉伸應變的方向(箭頭反向於另一者)、從該源極區域(S)至該汲極區域(D)之一電流流動方向。在一實施例中，具有單軸拉伸應變之該單軸應變奈米線104-2係由矽構成。在一實施例中，一個NMOS半導體裝置係由具有該單軸拉伸應變之奈米線104-2所製造。
再次參照圖1A，該基材102可由適合半導體裝置製造之一材料所組成。在一實施例中，基材102包括由一材料的一單一晶體所組成之較下面的主體基材，該材料可包括但不限於矽、鍺、矽鍺或一個三五族化合物半導體材料。由一材料所組成之一較上面的絕緣體層係設置在該較下面的主體基材上，該材料可包括但不限於氧化矽、氮化矽或氮氧化矽。因此，該結構100可從一起始絕緣體上半導體基材製造，例如一絕緣體上矽(SOI)基材或應變的絕緣體上矽(sSOI)基材。於是，在一實施例中，該等多個垂直堆疊的單軸應變奈米線104係設置在具有上面設置有一介入介電層之一主體晶狀基材上方，如同圖1A-1C所描繪者。可替代地，該結構100係直接地從一主體基材形成，以及局部氧化係被用於形成電性絕緣部分而取代掉上文所述的較上面的絕緣層。於是，在另一實施例中，該等多個垂直堆疊的單軸應變奈米線104係設置在未具有上面 設置一介入介電層之一主體晶狀基材上方。
在一實施例中，該單軸應變奈米線104可被尺寸化為線體或條帶(後者在下文描述)，並且可具有去角(squared-off)或較圓(rounder)的角。在一實施例中，該等單軸應變奈米線104係由例如但不限於矽、鍺或其組合的一材料所組成。在一此種實施例中，該等奈米線為單結晶。舉例來說，針對一單軸應變矽奈米線104，一單結晶奈米線係可根據一(100)全面方向(global orientation)，例如以z方向中的一<100>平面。在一實施例中，從圖1B中所示的一截面觀點，該等單軸應變奈米線104之尺寸係在奈米等級。舉例來說，在一特定實施例中，該等單軸應變奈米線104的最小尺寸係小於大約20奈米。
該等通道區域106中的每一者之寬度和高度在圖1B中顯示為大約相同，然而它們不必然如此。舉例來說，在另一實施例中(未繪示)，該等單軸應變奈米線104之寬度係實質上大於該高度。在一特定實施例中，該寬度係比該高度大2~10倍。具有此種幾何形狀之奈米線可指涉為奈米條帶。在一替代性實施例中(亦未繪出)，該等奈米條帶係垂直定向。亦即，該等單軸應變奈米線104的每一者具有一寬度和一高度，該寬度實質上小於該高度。
在一實施例中，再次參照圖1A，閘極電極堆疊108之該閘極電極係由一金屬閘極所構成，以及該閘極介電層係由一高介電係數(high-K)材料所構成。舉例來說，在一實施例中，該閘極介電層係由一材料所構成，該材料 例如但不限於氧化鉿、氮氧化鉿、矽酸鉿、氧化鑭、氧化鋯、矽酸鋯、氧化鉭、鈦酸鋇鍶、鈦酸鋇、鈦酸鍶、氧化釔、氧化鋁、鉛鈧鉭氧化物、鈮鋅酸鉛、或其等之組合。更進一步地，閘極介電層之一部分可包括形成自該奈米線104的頂部幾層之一層自然氧化層。在一實施例中，該閘極介電層係由有一頂部高介電係數的部分和由一半導體材料之氧化物所構成一較下面的部分所構成。在一實施例中，該閘極介電層係由氧化鉿之一頂部部分和氧化矽或氮氧化矽之一底部部分所構成。
在一實施例中，該閘極電極係由一金屬層所構成，該金屬層例如但不限於金屬氮化物、金屬碳化物、金屬矽化物、金屬鋁化物、鉿、鋯、鈦、鉭、鋁、釕，鈀，鉑，鈷，鎳或導電性金屬氧化物。在一特定實施例中，該閘極電極係由形成於一金屬工作函數設定層上方之一非工作函數設定填充材料所構成。
在一實施例中，該等間隔件116係由一絕緣介電材料所構成，該絕緣介電材料例如但不限於氧化矽、氮氧化矽或氮化矽。在一實施例中，該等接觸點114係製造自一金屬種類。該金屬種類可為諸如鎳或鈷之一純金屬，或是可為諸如一金屬對金屬合金或一金屬對半導體合金(例如，像是一矽化物材料)之一合金。
雖然上文描述的該裝置100係針對一單一裝置，例如一NMOS或一PMOS裝置，但是一CMOS架構亦可被形成來包括NMOS和PMOS兩者的奈米線為基礎應變通道裝 置，其係設置於相同的基材上或上方。舉例來說，根據本發明之另一實施例，一半導體結構包括一第一半導體裝置。該第一半導體裝置包括設置在一基材上方之一第一奈米線。該第一奈米線具有單軸拉伸應變，且包括一分離通道區域、和在該分離通道區域的兩側之任一側之源極與汲極區域。該分離通道區域具有沿著該單軸拉伸應變的方向之一電流流動方向。一第一閘極電極堆疊完全地環圍該第一奈米線之該分離通道區域。
該CMOS半導體結構亦包括一第二半導體裝置，其包括設置在該基材上方之一第二奈米線。該第二奈米線具有一單軸壓縮應變，且包括一分離通道區域、和在該分離通道區域的兩側之任一側之源極與汲極區域。該分離通道區域具有沿著該單軸壓縮應變的方向之一電流流動方向。一第二閘極電極堆疊完全地環圍該第二奈米線之該分離通道區域。
在一實施例中，該第一奈米線係由矽所構成，以及該第二奈米線係由矽鍺(SixGey，其中0<x<100且0<y<100)所構成。在一此種實施例中，該第一半導體裝置係一NMOS裝置，以及該第二半導體裝置係一PMOS裝置。在一實施例中，x係大約為30且y大約為70。然而，只要其他化學計量維持該層內的應變，則其它化學計量亦可獲選擇，例如可用Si40Ge60替代。在一實施例中，該CMOS半導體結構可自一起始絕緣體上半導體結構製造。於是，在一實施例中，該等第一和第二奈米線係設置在一主體晶 狀基材上方，該基材具有設置於其上之一介入介電層。
在一實施例中，該等第一和第二奈米線的每一者之該等源極和汲極區域為分離。並且，在一此種實施例中，該第一半導體裝置進一步包括完全環圍該第一奈米線的該等分離的源極和汲極區域之一第一對接觸點，以及該第二半導體裝置進一步包括完全環圍該第二奈米線的該等分離的源極和汲極區域之一第二對接觸點。在一實施例中，該CMOS半導體結構進一步包括設置在第一閘極電極堆疊和該第一對接觸點之間的一第一對間隔件，以及設置在該第二閘極電極堆疊和該第二對接觸點之間的一第二對間隔件。
在一實施例中，該等第一和第二奈米線的每一者之一部分為非分離。在一實施例中，該第一半導體裝置進一步包括一或更多額外的奈米線，其具有單軸拉伸應變且與該第一奈米線垂直地堆疊。同時，該第二半導體裝置進一步包括一或更多額外奈米線，其具有單軸壓縮應變且與該第二奈米線垂直地堆疊。
另一方面，提出製造一奈米線半導體結構之方法。舉例來說，根據本發明之一實施例，圖4A~4F繪示代表於製造一奈米線半導體結構的一方法中的各種操作之三維截面圖。
在一個實施例中，製造一奈米線半導體結構的一方法可包括形成一PMOS奈米線為基礎的半導體裝置與一鄰近的NMOS奈米線為基礎的半導體裝置兩者。每個裝 置可藉由於一基材上方形成一奈米線而獲製造。在一特定的實施例中，最終地針對該等NMOS與PMOS奈米線為基礎的半導體裝置之每一者提供兩個單軸應變奈米線之形成，圖4A繪示一初始結構400，其具有一基材402(例如由具有一絕緣二氧化矽層402B於其上的一主體基材矽基材402A所構成)、以及設置於其上之一矽層404/矽鍺層406/矽層408/矽鍺層410堆疊。
根據本發明之一實施例，該矽層404、該矽鍺層406、該矽層408和該矽鍺層410之每一者係經應變。在一此種實施例中，該等矽層404和408具有拉伸應變，而該等矽鍺層406和410具有壓縮應變。再次參照圖4A，在一範例性實施例中，結構400係藉由使應變的矽鍺和矽層在一初始應變的矽層之一晶圓上成長而遭提供，該初始應變的矽層係形成於一下方主體基材(其之應變矽部分為層404)的頂部上之一絕緣層上。在一特定的實施例中，該初始結構為在此一晶圓上之一雙軸拉伸應變矽層。在一特定實施例中，該矽層404具有等效於若該層曾於鬆弛的Si70Ge30上成長之應變，例如涉及一「虛擬基材(virtual substrate)」。接著，一Si30Ge70層(層406)係成長。由於該應變矽層404和該Si30GE70的晶格參數之間的差量，該Si70GE30層406係以等效於40%的矽鍺之雙軸應變壓縮地應變。然後一第二拉伸應變矽層408和一第二壓縮應變Si30GE70層會獲成長。
參照圖4B，該等矽層404/矽鍺層406/矽層408/矽鍺層410堆疊的一部分以及二氧化矽層402B的一頂部係例 如以一遮罩與電漿蝕刻程序而圖案化為一鰭狀結構412。從而，在一實施例中，一自由表面藉由圖案化以提供鰭狀結構412而形成於該等矽與矽鍺層的每一者之二側的任一側。在一此種實施例中，在寬度方向中導入該等自由表面使該等矽和矽者層中的雙軸應力降低到某種程度。然後，當形成分離奈米線(如下文與圖4E關聯地描述)時，如同上文與圖2和3關聯地描述者，即便不是全部，於該等矽和矽鍺層中留下的雙軸應力係被轉換為單軸為主。
在顯示出三個閘極結構之形成的一特定範例中，圖4C繪示出具有上面設置有三個犧牲閘極414A、414B和414C的鰭狀結構412。在一此種實施例中，該等三個犧牲閘極414A、414B和414C由一犧牲閘極氧化層416與一犧牲多晶矽閘極層418所構成，其等為例如覆蓋沉積(blank deposit)且以一電漿蝕刻程序圖案化。
在圖型化以形成犧牲閘極414A、414B和414C之後，間隔件可於該等三個犧牲閘極414A、414B和414C的側壁上形成，摻雜可於圖4C中所顯示的鰭狀結構412的區域420中執行(例如尖端及/或源極與汲極類型摻雜)，以及一介層介電層可遭形成以覆蓋且然後再次暴露(re-expose)該等三個犧牲閘極414A、414B和414C。針對一替代閘極程序或閘極最後(gast-last)程序，該介層介電層然後可被拋光以使該等三個犧牲閘極414A、414B、414C暴露。參照圖4D，該等三個犧牲閘極414A、414B、414C係與間隔件422以及介層介電層424一起暴露。
然後該等犧牲閘414A、414B和414C可例如於一替代閘極或閘極最後程序流程中移除，以使鰭狀結構412的通道部分暴露。參照圖4E的左手邊部分，在此情況中，該鰭狀結構412被用來製造一NMOS裝置，該等犧牲閘極414A、414B和414C係被移除以提供溝槽426。該等矽鍺層406和410由溝槽426所暴露的部分以及絕緣的二氧化矽層402B之暴露部分係被移除，以留下該等矽層404和408之分離部分，例如留下具有單軸拉伸應變的分離矽奈米線。
參照圖4E的右手邊部分，在此情況中，該鰭狀結構412被用來製造一PMOS裝置，該等犧牲閘極414A、414B和414C係被移除以提供溝槽428。該等矽層404和408由溝槽428所暴露的部分係被移除，以留下該等矽鍺層406和410之分離部分，例如留下具有單軸壓縮應變的分離矽鍺奈米線。
在一實施例中，該等矽層404和408係以一溼式蝕刻遭選擇性地蝕刻，其係選擇性地移除該等矽層404、408而不蝕刻該等矽鍺奈米線結構406、410。如同液態氫氧化物化學之此類蝕刻化學，包括氫氧化氨與氫氧化鉀，舉例而言可被利用來選擇性地蝕刻矽。在另一個實施例中，該等矽鍺層406和410係以一溼式蝕刻遭選擇性蝕刻，其係選擇性地移除矽鍺而不蝕刻該等矽奈米線結構404和408。如同羧酸/硝酸/氫氟酸(HF)化學，以及檸檬酸/硝酸/氫氟酸(HF)化學之此類蝕刻化學，舉例來說可被利用來選擇性地蝕刻矽鍺。因此，該等矽層可從該鰭狀結構412移除以 形成矽鍺奈米線，亦或是該等矽鍺層可從該鰭片結構412移除以形成矽通道奈米線。
在一實施例中，圖4E中所顯示的該等矽層404和408(NMOS)或矽鍺層(PMOS)之分離部分，在一奈米線為基礎的結構中最終將變成通道區域。因此，在圖4E所描繪的程序階段，可執行通道設建(engineering)或調諧(tuning)。舉例來說，在一實施例中，圖4E的左手邊部分所顯示的該等矽層404和408的分離部分，或圖4E的右手邊部分所顯示的該等矽鍺層406和410的分離部分係利用氧化和蝕刻程序來變薄。此一蝕刻程序可遭執行，同時該等線藉由蝕刻相對的矽或矽鍺層而分離。於是，獨立於該裝置的該等源極和汲極區域之尺寸化，形成自矽層404和408或是形成自矽鍺層406和410之該等初始線開始變得較厚且變薄至適合一奈米線裝置中的一通道區域之一尺寸。
接著如圖4E中所描繪的分離通道區域之形成，高介電係數(high-k)閘極介電層與金屬閘極程序可獲執行，並且源極與汲極接觸點可被增添。在顯示出三個閘極結構覆蓋兩條矽奈米線(NMOS)或覆蓋兩條矽鍺奈米線(PMOS)的形成之特定範例中，圖4F繪示出接著一NMOS閘極堆疊430或一PMOS閘極堆疊432的沉積之結構。該等閘極堆疊可個別地由一高介電係數閘極介電層以及一N型或P型金屬閘極電極層組成。此外，圖4F描繪在永久的閘極堆疊的形成後，該介層介電層424的隨後移除的結果。接觸點可形成於在圖4E中所剩下之介層介電層424的部分 之位置。在一實施例中，在移除424與形成接觸點434的程序過程中的某些階段，源極與汲極設建亦可被執行。
因此，或許在更廣泛的用語中，在一實施例中，製造一奈米線半導體結構的一方法包括於一基材上方形成一第一主動層。該第一主動層具有一第一晶格常數。然後一第二主動層形成於該第一主動層上。該第二主動層具有大於該第一晶格常數的一第二晶格常數。在一此種實施例中，該第一主動層是由矽所構成，且該第二主動層是由矽鍺(SixGey，0<x<100，0<y<100)所構成。主動層的數目可停止於此，例如，針對具有一單線PMOS裝置以及一單線NMOS裝置的一CMOS結構。可替代地，如上文所例示者，額外的第一與第二主動層可遭重複以最終地提供多線裝置。
在一實施例中，該第一主動層係形成於具有其上設置有一介入介電層的一主體晶體基材上方。該第一主動層係形成於該介入介電層上。在一此種實施例中，該第一主動層係由矽所構成，且藉由先形成一矽層於具有一頂部大致為Si70Ge30的層之一基材上而形成。然後該矽層從該Si70Ge30層轉換為該介入介電層。在一特定的此種實施例中，該第二主動層係由大致Si30Ge70所構成。
該方法然後包括自該第一主動層形成具有單軸拉伸應變之一第一奈米線。該第一奈米線包括一分離通道區域和在該分離通道區域的兩側之任一側上之源極和汲極區域。該分離通道區域具有沿著該單軸拉伸應變的方向之 一電流流動方向。具有單軸壓縮應變之一第二奈米線係形成自該第二主動層。該第二奈米線包括一分離通道區域和在該分離通道區域的兩側之任一側上之源極和汲極區域。該分離通道區域具有沿著該單軸壓縮應變的方向之一電流流動方向。在一實施例中，自該第一主動層形成該第一奈米線係包括選擇性地移除該第二主動層之一部分。同時，自該第二主動層形成該第二奈米線係包括選擇性地移除該第一主動層之一部分。
該方法然後包括形成一第一閘極電極堆疊以完全地環圍該第一奈米線之該分離通道區域。一第二閘極電極堆疊係遭形成以完全地環圍該第二奈米線之該分離通道區域。諸如接觸點形成與後端互連形成之隨後程序操作可接著被執行。
在一替代性實施例中，代替絕緣體上矽晶圓，類似於上文描述的奈米線裝置之裝置係於主體晶圓上製造。舉例來說，根據本發明之一實施例，圖5繪示另一個奈米線為基礎的半導體結構之一個三維截面檢視圖。
參照圖5，一鬆弛矽鍺緩衝層502係被用來提供用於應變矽層504和508(NMOS)或應變矽鍺層506和510(PMOS)之一樣板。上面有該鬆弛矽鍺緩衝層502之該基材512係利用摻雜(例如使得底部的線為一歐米茄FET(omega-FET))亦或是在接著鰭片圖案化的鰭片氧化程序下之一柱體來與該等線隔開。因此，在一實施例中，一第二主動層(例如一第一化學計量的SiGe)係形成於一第一 主動層(例如矽)，其係形成於具有一頂部表面層(例如一緩衝層)的一主體晶狀基材上，該頂部表面層具有該等第一和第二晶格常數之間的一晶格常數(例如一不同的第二化學計量的SiGe層)。沒有介入的整體(global)介電層係設置在該第一主動層以及該主體基材的該緩衝層之間。在一特定的實施例中，拉伸應變矽奈米線和壓縮應變矽鍺奈米線兩者皆係製造於鬆弛矽鍺基材上。
因此，本發明之一或更多實施例包括用以針對PMOS奈米線為基礎裝置改善電洞遷移性之壓縮應變，以及用以針對NMOS奈米線為基礎裝置改善電子遷移性之壓縮應變。在一實施例中，一或更多應變矽層(例如與鬆弛的Si70Ge30相配之晶格)以及一或更多應變SiGe層係製造於相同基材上方。在一實施例中，為了改善或最大化裝置效能，應變矽和應變矽鍺裝置係從此種層形成。在一實施例中，NMOS和PMOS單軸應變奈米線或奈米條帶裝置可藉由上文所描述的一或更多方式所製造。該等PMOS電晶體可包括具有沿著該電流流動方向之單軸壓縮應變之SiGe，而該等NMOS電晶體可包括具有沿著該電流流動方向之單軸拉伸應變之矽。
圖6繪示根據本發明之一實作之一運算裝置600。該運算裝置600收容一板件602。該板件602可包括數個構件，其包括但不限於一處理器604和至少一通訊晶片606。該處理器604係實體且電氣地耦接到該板件602。在某些實作中，該至少一通訊晶片606亦係實體且電氣地耦 接到該板件602。在進一步的實作中，該通訊晶片606係該處理器604之部分。
依據其之應用，運算裝置600可包括可與或不與該板件602實體且電氣地耦接之其他構件。這些其他構件包括但不限於：依電性記憶體(例如DRAM)、非依電性記憶體(例如ROM)、快閃記憶體、一圖形處理器、一數位信號處理器、一保密處理器、一晶片組、一天線、一顯示器、一觸碰式螢幕顯示器、一觸碰式螢幕控制器、一電池、一音訊編碼器、一視訊編碼器、一電源放大器、一全球定位系統(GPS)裝置、一羅盤、一加速計、一陀螺儀、一揚聲器、一攝影機和一大量儲存裝置(諸如硬碟驅動機、光碟片(CD)、數位多功能碟片(DVD)等等)。
該通訊晶片606使無線通訊能夠將資料傳送到該運算裝置600以及從該運算裝置600傳送。詞彙「無線」和其衍生詞可被用來描述電路、裝置、系統、方法、技術、通訊通道等，其等可透過使用經由一非固態媒體之經調變電磁輻射使資料通訊。該詞彙並非意指相關聯的裝置不會含有任何線體，即使在某些實施例中它們沒有。該通訊晶片606可實作為數個無線標準或協定中的任一者，包括但不限於Wi-Fi(IEEE 802.11家族)、WiMAX(IEEE 802.16家族)、IEEE 802.20、長期演進(LTE)、Ev-DO、HSPA+、HSDPA+、HSUPA+、EDGE、GSM、GPRS、CDMA、TDMA、DECT、藍牙、其衍生者，以及被指定為3G、4G、5G和超過者之任何其他無線協定。該運算裝置600可 包括多個通訊晶片606。舉例而言，一第一通訊晶片606可專屬於諸如Wi-Fi和藍牙之較短範圍的無線通訊，以及一第二通訊晶片606可專屬於諸如GPS、EDGE、GPRS、CDMA、WiMAX、LTE、Ev-DO和其他之較長範圍的無線通訊。
該運算裝置600的該處理器604包括封裝於該處理器604內之一積體電路晶粒。在本發明之某些實作中，該處理器的該積體電路晶粒包括一或更多個裝置，諸如根據本發明之實作所造出之奈米線電晶體。詞彙「處理器」可表示任何裝置、或處理來自暫存器及/或記憶體的電子資料以將該電子資料轉換為可儲存於暫存器及/或記憶體中的其他電子資料之裝置的部分。
該通訊晶片606亦包括封裝於該通訊晶片606內之一積體電路晶粒。根據本發明之另一實作，該通訊晶片之積體電路晶粒包括一或更多個裝置，諸如根據本發明之實作所造出之奈米線電晶體。
在進一步的實作中，被容納於該運算裝置600之另一個構件可含有一積體電路晶粒，其包括諸如根據本發明之實作所造出之奈米線電晶體的一或更多裝置。
在各種實作中，該運算裝置600可為一膝上型電腦、一上網型電腦、一筆記型電腦、一超輕薄電腦、一智慧型手機、一平板電腦、一個人數位助理(PDA)、一超行動PC、一行動電話、一桌上型電腦、一伺服器、一印表機、一掃描器、一監視器、一機上盒、一娛樂控制單元、 一數位攝影機、一可攜式音樂播放器或一數位視訊紀錄器。在進一步的實作中，該運算裝置600可為處理資料之任何其他電子裝置。
從而，單軸應變奈米線結構已獲揭露。在一實施例中，一半導體裝置包括設置於一基材上方之多個垂直堆疊的單軸應變奈米線。該等單軸應變奈米線的每一者各包括設置在該單軸應變奈米線中之一分離通道區域。該分離通道區域具有沿著該單軸應變的方向之一電流流動方向。源極和汲極區域係設置在該奈米線中，且在該分離通道區域的兩側中任一側上。一閘極電極堆疊完全地環圍該等分離通道區域。在一實施例中，該等單軸應變奈米線的每一者各係由矽所構成，且該單軸應變為一單軸拉伸應變。在一實施例中，該等單軸應變奈米線的每一者各係由矽鍺(SixGey，其中0<x<100且0<y<100)所構成，且該單軸應變為一單軸壓縮應變。

Claims (20)

  1. 一種半導體結構，該半導體結構包含於一基材上方的一奈米線，該奈米線包含：一分離通道區域，其具有一第一側與相對於該第一側的一第二側，該分離通道區域具有在該分離通道區域之該第一側與該分離通道區域之該第二側之間的單軸應變之方向；鄰近於該分離通道區域之該第一側的一分離源極區域；以及鄰近於該分離通道區域之該第二側的一分離汲極區域；完全圍繞該分離通道區域的一閘極電極，完全圍繞該分離源極區域的一導電源極接觸部，以及完全圍繞該分離汲極區域的一導電汲極接觸部。
  2. 如請求項1的半導體結構，該半導體結構進一步包含：在該分離通道區域與該閘極電極之間的一閘極介電層。
  3. 如請求項2的半導體結構，其中，該閘極介電層包含一高介電係數介電材料，並且其中，該閘極電極包含一金屬。
  4. 如請求項1的半導體結構，其中，該奈米線主要係由矽所組成，並且該分離通道區域的該單軸應變為一單軸拉 伸應變。
  5. 如請求項1的半導體結構，其中，該奈米線主要係由矽鍺(SixGey，其中，0<x<100且0<y<100)所組成，並且該分離通道區域的該單軸應變為一單軸壓縮應變。
  6. 如請求項5的半導體結構，其中，x約為30且y約為70。
  7. 如請求項1的半導體結構，其中，該奈米線係在具有一中介介電層於其上的一主體晶狀基材上方。
  8. 如請求項1的半導體結構，其中，該奈米線係在不具有中介介電層於其上的一主體晶狀基材上方。
  9. 如請求項1的半導體結構，該半導體裝置進一步包含：在該導電源極接觸部與該閘極電極之間的一第一介電間隔件；以及在該導電汲極接觸部與該閘極電極之間的一第二介電間隔件。
  10. 如請求項9的半導體結構，其中，位於該第一間隔件與該第二間隔件下方的該奈米線之一部份是非分離的。
  11. 一種製造半導體結構的方法，該方法包含下列步驟：在一基材上方形成一奈米線，該奈米線包含：一分離通道區域，其具有一第一側與相對於該第一側的一第二側，該分離通道區域具有在該分離通道區域之該第一側與該分離通道區域之該第二側之間的單軸應變之方向；鄰近於該分離通道區域之該第一側的一分離源極區域；以及 鄰近於該分離通道區域之該第二側的一分離汲極區域；形成完全圍繞該分離通道區域的一閘極電極，形成完全圍繞該分離源極區域的一導電源極接觸部，以及形成完全圍繞該分離汲極區域的一導電汲極接觸部。
  12. 如請求項11的方法，該方法進一步包含下列步驟：形成圍繞該分離通道區域的一閘極介電層，其中，形成該閘極電極的步驟包含：形成圍繞該閘極介電層的該閘極電極。
  13. 如請求項12的方法，其中，形成該閘極介電層的步驟包含：形成一高介電係數介電層，並且其中，形成該閘極電極的步驟包含：形成一金屬閘極電極。
  14. 如請求項11的方法，其中，該奈米線基本上係由矽所組成，並且該分離通道區域的該單軸應變為一單軸拉伸應變。
  15. 如請求項11的方法，其中，該奈米線基本上係由矽鍺(SixGey，其中，0<x<100且0<y<100)所組成，並且該分離通道區域的該單軸應變為一單軸壓縮應變。
  16. 如請求項15的方法，其中，x約為30且y約為70。
  17. 如請求項11的方法，其中，該奈米線係形成在具有一中介介電層於其上的一主體晶狀基材上。
  18. 如請求項11的方法，其中，該奈米線係形成在不具有中 介介電層於其上的一主體晶狀基材上。
  19. 如請求項11的方法，該方法進一步包含下列步驟：在該閘極電極的一第一側之處形成一第一介電間隔件，其中，該導電源極接觸部係形成於鄰近該第一介電間隔件之處；以及在相對於該第一側的該閘極電極之一第二側之處形成一第二介電間隔件，其中，該導電汲極接觸部係形成於鄰近該第二介電間隔件之處。
  20. 如請求項19的方法，其中，位於該第一間隔件與該第二間隔件下方的該奈米線之一部份是非分離的。
TW105116475A 2011-12-23 2012-12-22 單軸應變奈米線結構（二） TWI617033B (zh)

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