JP2006332210A - 半導体装置、積層型半導体装置、および半導体装置の製造方法 - Google Patents
半導体装置、積層型半導体装置、および半導体装置の製造方法 Download PDFInfo
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Abstract
【解決手段】 本発明の半導体装置の製造方法は、外部電極と接続する接続用電極12を形成する接続用電極形成工程(b)〜(j)を含み、上記接続用電極形成工程は、シリコン基板1に、その内壁が導電層5で覆われた凹部8を形成する凹部形成工程(b)〜(e)と、上記凹部8を上記導電層5とは異なる材料からなる充填材9で充填する充填工程(f)と、シリコン基板1の裏面から上記導電層5を露出させる露出工程(j)とを含む。
【選択図】 図1
Description
本発明の半導体装置の実施の一形態を、図2・3に基づいて説明すると以下の通りである。
<半導体装置の製造方法>
本発明の半導体装置の製造方法は、表面に半導体素子を備えた基板に対して、当該表面に開口部を有し、かつ内壁が導電層で覆われた凹部を形成する凹部形成工程と、上記凹部を充填材で充填する充填工程と、上記基板の裏面から上記導電材料を露出させる露出工程とを含めばよい。
2(2a,2b) 半導体素子形成領域
3(3a,3b) 第一絶縁膜
4(4a,4b) 第二絶縁膜
5(5a,5b) 導電層
7、70 フォトレジスト層
8 凹部
9(9a,9b) 充填材(芯部)
10(10a,10b) 半導体基板
11(11a,11b) 配線パターン(導電領域)
12(12a,12b) 接続用電極
13(13a,13b) 接続領域(第一接続領域)
15(15a,15b) 接続用端子(第二接続領域)
18 貫通孔
20(20a,20b) 半導体チップ(半導体装置)
21 マルチチップ半導体装置(積層型半導体装置)
Claims (9)
- その表面に半導体素子が設けられた基板に、該半導体素子と外部電極とを電気的に接続するための接続用電極を形成する接続用電極形成工程を含む半導体装置の製造方法であって、
上記接続用電極形成工程は、
基板表面に開口部を形成し、かつ該開口部の内壁を導電層で覆うことにより凹部を形成する凹部形成工程と、
上記基板の裏面から上記導電層を露出させる露出工程とを含むことを特徴とする半導体装置の製造方法。 - 上記導電層の材料とは異なる材料からなる充填材を上記凹部に充填する充填工程をさらに含むことを特徴とする請求項1に記載の半導体装置の製造方法。
- 上記露出工程は、上記基板の裏面を表面に向かって後退させることにより導電層を露出させることを特徴とする請求項1または2に記載の半導体装置の製造方法。
- 上記凹部形成工程は、基板表面の開口部の内壁から該開口部周辺にまで上記導電層を連続して形成することによって、導電領域を形成する導電領域形成工程を含むことを特徴とする請求項1〜3のいずれか1項に記載の半導体装置の製造方法。
- 上記凹部形成工程は、メッキ法、CVD法、およびPVD法の少なくとも1つによって導電層を形成することを特徴とする請求項1〜4のいずれか1項に記載の半導体装置の製造方法。
- 基板と、当該基板表面に設けられた半導体素子とを備える半導体装置であって、
上記基板は、その表面に外部電極と接続する第一接続領域、および、その裏面に外部電極と接続する第二接続領域を有すると共に、該基板を貫通し、かつ上記第一および第二接続領域と電気的に接続するように形成された接続用電極を備え、
上記接続用電極は、少なくともその一部が、上記基板表面に平行な断面において、芯部と、芯部を囲む導電層とを備え、
上記芯部は上記導電層とは異なる材料からなることを特徴とする半導体装置。 - 上記第二接続領域は上記接続用電極の下端面であり、
上記接続用電極の下端面は導電層で覆われていることを特徴とする請求項6に記載の半導体装置。 - 請求項6または7に記載の半導体装置が複数積層され、隣り合う半導体装置同士が一方の第一接続領域と他方の第二接続領域とを介して電気的に接続されていることを特徴とする積層型半導体装置。
- 上記半導体装置の第一接続領域は、当該半導体装置に積層される半導体装置の第二接続領域よりも大きいことを特徴とする請求項8に記載の積層型半導体装置。
Priority Applications (4)
Application Number | Priority Date | Filing Date | Title |
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JP2005151624A JP4170313B2 (ja) | 2005-05-24 | 2005-05-24 | 半導体装置の製造方法 |
KR1020060044716A KR100815098B1 (ko) | 2005-05-24 | 2006-05-18 | 반도체 장치, 적층형 반도체 장치, 및 반도체 장치의 제조방법 |
US11/438,281 US20060267190A1 (en) | 2005-05-24 | 2006-05-23 | Semiconductor device, laminated semiconductor device, and method for producing semiconductor device |
TW095118360A TW200742030A (en) | 2005-05-24 | 2006-05-24 | Semiconductor device, laminated semiconductor device, and method for producing semiconductor device |
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JP2005151624A JP4170313B2 (ja) | 2005-05-24 | 2005-05-24 | 半導体装置の製造方法 |
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JP2006332210A true JP2006332210A (ja) | 2006-12-07 |
JP4170313B2 JP4170313B2 (ja) | 2008-10-22 |
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US (1) | US20060267190A1 (ja) |
JP (1) | JP4170313B2 (ja) |
KR (1) | KR100815098B1 (ja) |
TW (1) | TW200742030A (ja) |
Families Citing this family (5)
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CN100580911C (zh) * | 2005-10-20 | 2010-01-13 | 株式会社村田制作所 | 电路模块和使用该电路模块的电路装置 |
US7566657B2 (en) | 2007-01-17 | 2009-07-28 | Hewlett-Packard Development Company, L.P. | Methods of forming through-substrate interconnects |
EP2096115A1 (en) * | 2008-02-26 | 2009-09-02 | Nestec S.A. | Oligosaccharide ingredient |
KR100984729B1 (ko) * | 2008-06-25 | 2010-10-01 | 앰코 테크놀로지 코리아 주식회사 | 반도체 장치 및 그 제조 방법 |
JP5331427B2 (ja) | 2008-09-29 | 2013-10-30 | 株式会社日立製作所 | 半導体装置 |
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US6809421B1 (en) * | 1996-12-02 | 2004-10-26 | Kabushiki Kaisha Toshiba | Multichip semiconductor device, chip therefor and method of formation thereof |
JP3920399B2 (ja) * | 1997-04-25 | 2007-05-30 | 株式会社東芝 | マルチチップ半導体装置用チップの位置合わせ方法、およびマルチチップ半導体装置の製造方法・製造装置 |
KR101384035B1 (ko) * | 1999-09-02 | 2014-04-09 | 이비덴 가부시키가이샤 | 프린트배선판 및 그 제조방법 |
CN1279605C (zh) * | 2002-03-19 | 2006-10-11 | 精工爱普生株式会社 | 半导体装置及其制造方法、电路基板以及电子仪器 |
TWI239629B (en) * | 2003-03-17 | 2005-09-11 | Seiko Epson Corp | Method of manufacturing semiconductor device, semiconductor device, circuit substrate and electronic apparatus |
TWI251313B (en) * | 2003-09-26 | 2006-03-11 | Seiko Epson Corp | Intermediate chip module, semiconductor device, circuit board, and electronic device |
JP3990347B2 (ja) * | 2003-12-04 | 2007-10-10 | ローム株式会社 | 半導体チップおよびその製造方法、ならびに半導体装置 |
US20060252262A1 (en) * | 2005-05-03 | 2006-11-09 | Rockwell Scientific Licensing, Llc | Semiconductor structures having via structures between planar frontside and backside surfaces and methods of fabricating the same |
-
2005
- 2005-05-24 JP JP2005151624A patent/JP4170313B2/ja not_active Expired - Fee Related
-
2006
- 2006-05-18 KR KR1020060044716A patent/KR100815098B1/ko not_active IP Right Cessation
- 2006-05-23 US US11/438,281 patent/US20060267190A1/en not_active Abandoned
- 2006-05-24 TW TW095118360A patent/TW200742030A/zh unknown
Also Published As
Publication number | Publication date |
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US20060267190A1 (en) | 2006-11-30 |
KR20060121687A (ko) | 2006-11-29 |
KR100815098B1 (ko) | 2008-03-20 |
TW200742030A (en) | 2007-11-01 |
JP4170313B2 (ja) | 2008-10-22 |
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