JP2006237257A - 半導体装置およびその製造方法 - Google Patents
半導体装置およびその製造方法 Download PDFInfo
- Publication number
- JP2006237257A JP2006237257A JP2005049502A JP2005049502A JP2006237257A JP 2006237257 A JP2006237257 A JP 2006237257A JP 2005049502 A JP2005049502 A JP 2005049502A JP 2005049502 A JP2005049502 A JP 2005049502A JP 2006237257 A JP2006237257 A JP 2006237257A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor device
- manufacturing
- semiconductor substrate
- gas
- pressure
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 99
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 41
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims abstract description 55
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 41
- 239000010703 silicon Substances 0.000 claims abstract description 41
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 40
- 239000007789 gas Substances 0.000 claims abstract description 37
- 239000000758 substrate Substances 0.000 claims abstract description 35
- 238000012545 processing Methods 0.000 claims abstract description 31
- 229910052757 nitrogen Inorganic materials 0.000 claims abstract description 27
- 238000000034 method Methods 0.000 claims abstract description 23
- 239000010410 layer Substances 0.000 claims description 37
- 150000004767 nitrides Chemical class 0.000 claims description 23
- 238000009832 plasma treatment Methods 0.000 claims description 20
- 239000002344 surface layer Substances 0.000 claims description 20
- 239000010949 copper Substances 0.000 claims description 19
- QGZKDVFQNNGYKY-UHFFFAOYSA-N Ammonia Chemical compound N QGZKDVFQNNGYKY-UHFFFAOYSA-N 0.000 claims description 18
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 15
- 229910045601 alloy Inorganic materials 0.000 claims description 15
- 239000000956 alloy Substances 0.000 claims description 15
- 229910052802 copper Inorganic materials 0.000 claims description 14
- 230000006837 decompression Effects 0.000 claims description 12
- 238000009792 diffusion process Methods 0.000 claims description 10
- 229910021529 ammonia Inorganic materials 0.000 claims description 9
- 229910052751 metal Inorganic materials 0.000 claims description 6
- 239000002184 metal Substances 0.000 claims description 6
- 230000002265 prevention Effects 0.000 claims description 6
- -1 nitrogen-containing compound Chemical class 0.000 claims description 4
- 230000001678 irradiating effect Effects 0.000 claims description 3
- 239000002210 silicon-based material Substances 0.000 claims description 3
- 230000008569 process Effects 0.000 abstract description 11
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 abstract description 10
- 229910000077 silane Inorganic materials 0.000 abstract description 9
- 239000000463 material Substances 0.000 abstract description 5
- 150000001875 compounds Chemical class 0.000 abstract description 4
- QGZKDVFQNNGYKY-UHFFFAOYSA-O Ammonium Chemical compound [NH4+] QGZKDVFQNNGYKY-UHFFFAOYSA-O 0.000 abstract 1
- 239000002244 precipitate Substances 0.000 description 7
- 230000007423 decrease Effects 0.000 description 6
- 230000000052 comparative effect Effects 0.000 description 4
- JUZTWRXHHZRLED-UHFFFAOYSA-N [Si].[Cu].[Cu].[Cu].[Cu].[Cu] Chemical compound [Si].[Cu].[Cu].[Cu].[Cu].[Cu] JUZTWRXHHZRLED-UHFFFAOYSA-N 0.000 description 3
- 229910021360 copper silicide Inorganic materials 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- 238000005530 etching Methods 0.000 description 3
- QPLDLSVMHZLSFG-UHFFFAOYSA-N Copper oxide Chemical compound [Cu]=O QPLDLSVMHZLSFG-UHFFFAOYSA-N 0.000 description 2
- 230000004888 barrier function Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 230000010354 integration Effects 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 238000005121 nitriding Methods 0.000 description 2
- 238000002360 preparation method Methods 0.000 description 2
- 230000009467 reduction Effects 0.000 description 2
- 229910000838 Al alloy Inorganic materials 0.000 description 1
- 239000005751 Copper oxide Substances 0.000 description 1
- 229910000881 Cu alloy Inorganic materials 0.000 description 1
- 229910008045 Si-Si Inorganic materials 0.000 description 1
- 229910006411 Si—Si Inorganic materials 0.000 description 1
- 238000013459 approach Methods 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 238000012512 characterization method Methods 0.000 description 1
- 229910000431 copper oxide Inorganic materials 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- BUMGIEFFCMBQDG-UHFFFAOYSA-N dichlorosilicon Chemical compound Cl[Si]Cl BUMGIEFFCMBQDG-UHFFFAOYSA-N 0.000 description 1
- PZPGRFITIJYNEJ-UHFFFAOYSA-N disilane Chemical compound [SiH3][SiH3] PZPGRFITIJYNEJ-UHFFFAOYSA-N 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 238000001465 metallisation Methods 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
- 238000007781 pre-processing Methods 0.000 description 1
- 230000001681 protective effect Effects 0.000 description 1
- 238000011160 research Methods 0.000 description 1
- 229920006395 saturated elastomer Polymers 0.000 description 1
- 150000003376 silicon Chemical class 0.000 description 1
- 230000036962 time dependent Effects 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76867—Barrier, adhesion or liner layers characterized by methods of formation other than PVD, CVD or deposition from a liquids
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/314—Inorganic layers
- H01L21/3143—Inorganic layers composed of alternated layers or of mixtures of nitrides and oxides or of oxinitrides, e.g. formation of oxinitride by oxidation of nitride layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76822—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc.
- H01L21/76826—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc. by contacting the layer with gases, liquids or plasmas
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
- H01L21/76849—Barrier, adhesion or liner layers formed in openings in a dielectric the layer being positioned on top of the main fill metal
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76886—Modifying permanently or temporarily the pattern or the conductivity of conductive members, e.g. formation of alloys, reduction of contact resistances
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
- H01L21/0217—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02203—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being porous
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
- H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
- H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
- H01L21/02274—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition in the presence of a plasma [PECVD]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02296—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer
- H01L21/02318—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment
- H01L21/02321—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment introduction of substances into an already existing insulating layer
- H01L21/02329—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment introduction of substances into an already existing insulating layer introduction of nitrogen
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Plasma & Fusion (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Electrodes Of Semiconductors (AREA)
Abstract
【解決手段】 真空チャンバにシリコン含有化合物からなる処理ガス(第1のガス)を導入し、チャンバ内に配された半導体基板10を第1のガス雰囲気に晒す(シリコン処理工程)。次に、真空チャンバ内の圧力を、シリコン処理工程を開始する直前のチャンバ内の圧力よりも低い圧力まで減圧する(減圧工程)。続いて、真空チャンバに窒素含有化合物からなる処理ガス(第2のガス)を導入し、そのプラズマを半導体基板10に照射する(窒素プラズマ処理工程)。
【選択図】 図4
Description
(第1実施形態)
(第2実施形態)
2 半導体装置
10 半導体基板
20 絶縁膜
20a 凹部
22,24,26,28 絶縁膜
30 導電膜
32 合金層
34 合金層
40 窒化層
50 拡散防止膜
Claims (6)
- 一方の面に銅含有金属からなる導電膜が露出した半導体基板を真空チャンバ内に配する準備工程と、
前記半導体基板が配された前記真空チャンバにシリコン含有化合物からなる第1のガスを導入し、前記半導体基板を当該第1のガス雰囲気に晒すシリコン処理工程と、
前記シリコン処理工程の後に、前記真空チャンバ内の圧力を、前記シリコン処理工程を開始する直前の前記真空チャンバ内の圧力である第1の圧力よりも低い第2の圧力まで減圧する減圧工程と、
前記減圧工程の後に、前記真空チャンバに窒素含有化合物からなる第2のガスを導入し、前記半導体基板に当該第2のガスのプラズマを照射する窒素プラズマ処理工程と、
を含むことを特徴とする半導体装置の製造方法。 - 請求項1に記載の半導体装置の製造方法において、
前記第2の圧力は0.13Pa以下である半導体装置の製造方法。 - 請求項1または2に記載の半導体装置の製造方法において、
前記第2のガスは、アンモニアまたは窒素である半導体装置の製造方法。 - 請求項1乃至3いずれかに記載の半導体装置の製造方法において、
前記窒素プラズマ処理工程よりも後に、前記半導体基板の前記一方の面を覆うように、SiC、SiCNまたはSiOCからなる拡散防止膜を形成する拡散防止膜形成工程を含む半導体装置の製造方法。 - 半導体基板と、
前記半導体基板上に設けられた絶縁膜と、
前記絶縁膜に設けられた凹部に埋設された、銅含有金属からなる導電膜と、
前記導電膜の表層に形成された、銅およびシリコンを含む合金層と、
前記絶縁膜の表層に均一な厚みで形成され、前記絶縁膜が窒化されてなる窒化層と、
を備えることを特徴とする半導体装置。 - 請求項5に記載の半導体装置において、
前記絶縁膜はポーラス膜である半導体装置。
Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2005049502A JP4516447B2 (ja) | 2005-02-24 | 2005-02-24 | 半導体装置の製造方法 |
US11/355,003 US7745937B2 (en) | 2005-02-24 | 2006-02-16 | Semiconductor device and method of manufacturing the same |
CN2006100094729A CN1832130B (zh) | 2005-02-24 | 2006-02-23 | 半导体器件及其制造方法 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2005049502A JP4516447B2 (ja) | 2005-02-24 | 2005-02-24 | 半導体装置の製造方法 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2006237257A true JP2006237257A (ja) | 2006-09-07 |
JP4516447B2 JP4516447B2 (ja) | 2010-08-04 |
Family
ID=36911824
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2005049502A Expired - Fee Related JP4516447B2 (ja) | 2005-02-24 | 2005-02-24 | 半導体装置の製造方法 |
Country Status (3)
Country | Link |
---|---|
US (1) | US7745937B2 (ja) |
JP (1) | JP4516447B2 (ja) |
CN (1) | CN1832130B (ja) |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2009010016A (ja) * | 2007-06-26 | 2009-01-15 | Fujitsu Microelectronics Ltd | 配線の形成方法及び半導体装置の製造方法 |
JP2009130369A (ja) * | 2007-11-27 | 2009-06-11 | Interuniv Micro Electronica Centrum Vzw | Cuキャップ層としてCuゲルマナイドおよびCuシリサイドを集積および作製する方法 |
US9595601B2 (en) | 2014-12-03 | 2017-03-14 | Joled, Inc. | Method of fabricating thin-film semiconductor substrate |
Families Citing this family (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7749896B2 (en) * | 2005-08-23 | 2010-07-06 | Taiwan Semiconductor Manufacturing Co., Ltd. | Semiconductor device and method for forming the same |
EP2064737A1 (en) * | 2006-09-04 | 2009-06-03 | Nxp B.V. | CuSiN/SiN DIFFUSION BARRIER FOR COPPER IN INTEGRATED-CIRCUIT DEVICES |
WO2008074672A1 (en) * | 2006-12-20 | 2008-06-26 | Nxp B.V. | Improving adhesion of diffusion barrier on cu containing interconnect element |
JP4294696B2 (ja) * | 2007-02-02 | 2009-07-15 | 東京エレクトロン株式会社 | 半導体装置の製造方法および製造装置、ならびに記憶媒体 |
JP2008258431A (ja) * | 2007-04-05 | 2008-10-23 | Toshiba Corp | 半導体装置、およびその製造方法 |
WO2009055450A1 (en) * | 2007-10-25 | 2009-04-30 | Applied Materials, Inc. | Adhesion improvement of dielectric barrier to copper by the addition of thin interface layer |
US20090269923A1 (en) * | 2008-04-25 | 2009-10-29 | Lee Sang M | Adhesion and electromigration improvement between dielectric and conductive layers |
JP6318188B2 (ja) * | 2016-03-30 | 2018-04-25 | 株式会社日立国際電気 | 半導体装置の製造方法、基板処理装置およびプログラム |
Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH11204523A (ja) * | 1998-01-07 | 1999-07-30 | Toshiba Corp | 半導体装置の製造方法 |
JP2001053076A (ja) * | 1999-08-10 | 2001-02-23 | Hitachi Ltd | 半導体集積回路装置および半導体集積回路装置の製造方法 |
JP2002246391A (ja) * | 2001-02-21 | 2002-08-30 | Nec Corp | 半導体装置の製造方法 |
JP2004096052A (ja) * | 2002-03-13 | 2004-03-25 | Nec Electronics Corp | 半導体装置およびその製造方法ならびに金属配線 |
JP2004193544A (ja) * | 2002-05-08 | 2004-07-08 | Nec Electronics Corp | 半導体装置、および半導体装置の製造方法 |
JP2004296515A (ja) * | 2003-03-25 | 2004-10-21 | Renesas Technology Corp | 半導体装置およびその製造方法 |
Family Cites Families (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
TW379387B (en) | 1996-11-29 | 2000-01-11 | Texas Instruments Inc | A process for encapsulation of copper surfaces |
US6596631B1 (en) | 2000-07-26 | 2003-07-22 | Advanced Micro Devices, Inc. | Method of forming copper interconnect capping layers with improved interface and adhesion |
US6696360B2 (en) * | 2001-03-15 | 2004-02-24 | Micron Technology, Inc. | Barrier-metal-free copper damascene technology using atomic hydrogen enhanced reflow |
US6599827B1 (en) | 2001-05-02 | 2003-07-29 | Advanced Micro Devices, Inc. | Methods of forming capped copper interconnects with improved electromigration resistance |
CN1254854C (zh) * | 2001-12-07 | 2006-05-03 | 东京毅力科创株式会社 | 绝缘膜氮化方法、半导体装置及其制造方法、基板处理装置和基板处理方法 |
US7687917B2 (en) * | 2002-05-08 | 2010-03-30 | Nec Electronics Corporation | Single damascene structure semiconductor device having silicon-diffused metal wiring layer |
US7187081B2 (en) * | 2003-01-29 | 2007-03-06 | International Business Machines Corporation | Polycarbosilane buried etch stops in interconnect structures |
JP2004292641A (ja) * | 2003-03-27 | 2004-10-21 | Shin Etsu Chem Co Ltd | 多孔質膜形成用組成物、多孔質膜の製造方法、多孔質膜、層間絶縁膜、及び半導体装置 |
DE10314504B4 (de) * | 2003-03-31 | 2007-04-26 | Advanced Micro Devices, Inc., Sunnyvale | Verfahren zur Herstellung einer nitridhaltigen Isolationsschicht durch Kompensieren von Stickstoffungleichförmigkeiten |
-
2005
- 2005-02-24 JP JP2005049502A patent/JP4516447B2/ja not_active Expired - Fee Related
-
2006
- 2006-02-16 US US11/355,003 patent/US7745937B2/en not_active Expired - Fee Related
- 2006-02-23 CN CN2006100094729A patent/CN1832130B/zh not_active Expired - Fee Related
Patent Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH11204523A (ja) * | 1998-01-07 | 1999-07-30 | Toshiba Corp | 半導体装置の製造方法 |
JP2001053076A (ja) * | 1999-08-10 | 2001-02-23 | Hitachi Ltd | 半導体集積回路装置および半導体集積回路装置の製造方法 |
JP2002246391A (ja) * | 2001-02-21 | 2002-08-30 | Nec Corp | 半導体装置の製造方法 |
JP2004096052A (ja) * | 2002-03-13 | 2004-03-25 | Nec Electronics Corp | 半導体装置およびその製造方法ならびに金属配線 |
JP2004193544A (ja) * | 2002-05-08 | 2004-07-08 | Nec Electronics Corp | 半導体装置、および半導体装置の製造方法 |
JP2004296515A (ja) * | 2003-03-25 | 2004-10-21 | Renesas Technology Corp | 半導体装置およびその製造方法 |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2009010016A (ja) * | 2007-06-26 | 2009-01-15 | Fujitsu Microelectronics Ltd | 配線の形成方法及び半導体装置の製造方法 |
JP2009130369A (ja) * | 2007-11-27 | 2009-06-11 | Interuniv Micro Electronica Centrum Vzw | Cuキャップ層としてCuゲルマナイドおよびCuシリサイドを集積および作製する方法 |
US9595601B2 (en) | 2014-12-03 | 2017-03-14 | Joled, Inc. | Method of fabricating thin-film semiconductor substrate |
Also Published As
Publication number | Publication date |
---|---|
CN1832130B (zh) | 2011-08-03 |
US20060186549A1 (en) | 2006-08-24 |
JP4516447B2 (ja) | 2010-08-04 |
CN1832130A (zh) | 2006-09-13 |
US7745937B2 (en) | 2010-06-29 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JP4516447B2 (ja) | 半導体装置の製造方法 | |
US7858519B2 (en) | Integrated circuit and manufacturing method of copper germanide and copper silicide as copper capping layer | |
US7964496B2 (en) | Schemes for forming barrier layers for copper in interconnect structures | |
US8440562B2 (en) | Germanium-containing dielectric barrier for low-K process | |
US20100090342A1 (en) | Metal Line Formation Through Silicon/Germanium Soaking | |
JP4638140B2 (ja) | 半導体素子の銅配線形成方法 | |
TWI438865B (zh) | 半導體裝置及其製造方法 | |
US20040152336A1 (en) | Semiconductor device and its manufacturing method | |
JP2007180408A (ja) | 半導体装置およびその製造方法 | |
JP2011082308A (ja) | 半導体装置の製造方法 | |
JP5217272B2 (ja) | 配線の形成方法及び半導体装置の製造方法 | |
US7338897B2 (en) | Method of fabricating a semiconductor device having metal wiring | |
KR101152203B1 (ko) | 반도체 장치 및 그의 제조 방법 | |
JP2004207604A (ja) | 半導体装置およびその製造方法 | |
US20040219795A1 (en) | Method to improve breakdown voltage by H2 plasma treat | |
JP2006179645A (ja) | 半導体装置及びその製造方法 | |
JP2005129849A (ja) | 半導体装置の製造方法 | |
JPH1041471A (ja) | 半導体装置およびその製造方法 | |
JP2006203019A (ja) | 半導体装置及びその形成方法 | |
JP2006237163A (ja) | 半導体装置の製造方法 | |
JP2005032854A (ja) | 半導体装置の製造方法 | |
JP2007019283A (ja) | 半導体装置の製造方法 | |
JP2006080451A (ja) | 半導体装置の製造方法 | |
JP2007220795A (ja) | 半導体装置の製造方法 | |
JP2006100462A (ja) | 半導体装置の製造方法 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A621 | Written request for application examination |
Free format text: JAPANESE INTERMEDIATE CODE: A621 Effective date: 20071116 |
|
A977 | Report on retrieval |
Free format text: JAPANESE INTERMEDIATE CODE: A971007 Effective date: 20100205 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20100216 |
|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20100414 |
|
TRDD | Decision of grant or rejection written | ||
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 20100511 |
|
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 |
|
A61 | First payment of annual fees (during grant procedure) |
Free format text: JAPANESE INTERMEDIATE CODE: A61 Effective date: 20100514 |
|
R150 | Certificate of patent or registration of utility model |
Free format text: JAPANESE INTERMEDIATE CODE: R150 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20130521 Year of fee payment: 3 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20140521 Year of fee payment: 4 |
|
LAPS | Cancellation because of no payment of annual fees |