JP2006093209A - 半導体装置の作製方法 - Google Patents
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1259—Multistep manufacturing methods
- H01L27/1262—Multistep manufacturing methods with a particular formation, treatment or coating of the substrate
- H01L27/1266—Multistep manufacturing methods with a particular formation, treatment or coating of the substrate the substrate on which the devices are formed not being the final device substrate, e.g. using a temporary substrate
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/7806—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices involving the separation of the active layers from a substrate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
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Abstract
【解決手段】 本発明は、エッチングの進行方向を一方向に固定し、エッチングの進行に合わせて被剥離層の反りを一方向にすることで亀裂の発生を抑えるというものである。例えば、基板上に設けた剥離層をパターニングして、下地絶縁層を形成し、基板と下地絶縁層とが接する部分で固定させれば、基板と下地絶縁層とが接する部分はエッチングされないことを利用してエッチングの進行を制御することができる。
【選択図】 図1
Description
絶縁表面を有する基板上に剥離層を形成する第1の工程と、
前記剥離層を選択的に除去する第2の工程と、
前記剥離層および前記基板上に接する下地絶縁層を形成する第3の工程と、
前記剥離層と重なる下地絶縁層上に複数の薄膜集積回路を含む層を形成する第4の工程と、
薄膜集積回路を覆う保護層を形成する第5の工程と、
下地絶縁層を選択的に除去して隣り合う薄膜集積回路の境界領域の剥離層を露呈させる第6の工程と、
露呈させた部分から剥離層をエッチングして、前記薄膜集積回路の下方に空間を形成する第7の工程と、
前記薄膜集積回路を、接着面を備える基体へ転置する第8の工程と、を有し、
前記エッチングは、前記下地絶縁層によってエッチングの進行方向を制御されることを特徴とする半導体装置の作製方法である。
絶縁表面を有する基板上に剥離層を形成する第1の工程と、
前記剥離層を選択的に除去する第2の工程と、
前記剥離層および前記基板上に接する下地絶縁層を形成する第3の工程と、
前記剥離層と重なる下地絶縁層上に複数の薄膜集積回路を含む層を形成する第4の工程と、
薄膜集積回路を覆う保護層を形成する第5の工程と、
下地絶縁層を選択的に除去して隣り合う薄膜集積回路の境界領域の剥離層を露呈させる第6の工程と、
露呈させた部分から剥離層をエッチングして、前記薄膜集積回路の下方に空間を形成する第7の工程と、
前記薄膜集積回路を、第1のラミネートフィルムへ転置し、第2のラミネートフィルムとでラミネートする第8の工程と、を有し、
前記エッチングは、前記下地絶縁層によってエッチングの進行方向を制御されることを特徴とする半導体装置の作製方法である。
絶縁表面を有する基板上に剥離層を形成する第1の工程と、
前記剥離層上に下地絶縁層を形成する第2の工程と、
前記剥離層上に第1の薄膜集積回路および第2の薄膜集積回路を含む層を形成する第3の工程と、
第1の薄膜集積回路および第2の薄膜集積回路を覆う保護層を形成する第4の工程と、
第1の薄膜集積回路および第2の薄膜集積回路を囲む下地絶縁層を選択的に除去して剥離層を露呈させる第5の工程と、
露呈させた部分から剥離層を部分的エッチングして、前記第1の薄膜集積回路および前記第2の薄膜集積回路の下方に空間を形成し、且つ、第1の薄膜集積回路と第2の薄膜集積回路との間に剥離層の一部を残存させる第6の工程と、
前記薄膜集積回路を、接着面を備える基体へ転置する第7の工程と、を有していることを特徴とする半導体装置の作製方法である。
ここでは、本発明の半導体装置の作製方法について以下に説明する。
また、ここでは実施の形態1とは異なる作製方法を図3を用いて説明する。
また、ここでは実施の形態1および実施の形態2とは異なる作製方法を図4、および図5を用いて説明する。
本実施の形態では、薄膜集積回路の製造装置の例を示す。
本実施の形態では実施の形態4で示した製造装置とは異なる製造装置を示す。実施の形態4では基板を第2基板移動用アームで押し付ける例であったが、本実施の形態ではロールを用いる。
本発明により作製される薄膜集積回路は、複数の素子と、アンテナとして機能する導電層とを有する。複数の素子とは、例えば、薄膜トランジスタ、容量素子、抵抗素子、ダイオード等に相当する。
本発明により作製される薄膜集積回路の用途は広範にわたるが、例えば、紙幣、硬貨、有価証券類、無記名債券類、証書類(運転免許証や住民票等、図9(A)参照)、包装用容器類(包装紙やボトル等、図9(B)参照)、記録媒体(DVDソフトやビデオテープ等、図9(C)参照)、乗物類(自転車等、図9(D)参照)、身の回り品(鞄や眼鏡等、図9(E)参照)、食品類、衣類、生活用品類、電子機器等に設けて使用することができる。電子機器とは、液晶表示装置、EL表示装置、テレビジョン装置(単にテレビ、テレビ受像機、テレビジョン受像機とも呼ぶ)及び携帯電話等を指す。
11a:剥離層
11b:剥離層の一部
12a:下地絶縁層
12b:一部除去された下地絶縁層
13:第1の素子群を含む被剥離層
13a:第1の層間絶縁層
13b:第2の層間絶縁層
13c:複数のTFT
16:保護層
17:レジストマスク
18a:第1の接着性合成樹脂
18b:分断後の第1の接着性合成樹脂
19a:第1のラミネートフィルム
19b:分断後の第1のラミネートフィルム
20:分断後の第2の接着性合成樹脂
21:分断後の第2のラミネートフィルム
Claims (7)
- 絶縁表面を有する基板上に剥離層を形成する第1の工程と、
前記剥離層を選択的に除去する第2の工程と、
前記剥離層および前記基板上に接する下地絶縁層を形成する第3の工程と、
前記剥離層と重なる下地絶縁層上に複数の薄膜集積回路を含む層を形成する第4の工程と、
薄膜集積回路を覆う保護層を形成する第5の工程と、
下地絶縁層を選択的に除去して隣り合う薄膜集積回路の境界領域の剥離層を露呈させる第6の工程と、
露呈させた部分から剥離層をエッチングして、前記薄膜集積回路の下方に空間を形成する第7の工程と、
前記薄膜集積回路を、接着面を備える基体へ転置する第8の工程と、を有し、
前記エッチングは、前記下地絶縁層によってエッチングの進行方向を制御されることを特徴とする半導体装置の作製方法。 - 絶縁表面を有する基板上に剥離層を形成する第1の工程と、
前記剥離層を選択的に除去する第2の工程と、
前記剥離層および前記基板上に接する下地絶縁層を形成する第3の工程と、
前記剥離層と重なる下地絶縁層上に複数の薄膜集積回路を含む層を形成する第4の工程と、
薄膜集積回路を覆う保護層を形成する第5の工程と、
下地絶縁層を選択的に除去して隣り合う薄膜集積回路の境界領域の剥離層を露呈させる第6の工程と、
露呈させた部分から剥離層をエッチングして、前記薄膜集積回路の下方に空間を形成する第7の工程と、
前記薄膜集積回路を、第1のラミネートフィルムへ転置し、第2のラミネートフィルムとでラミネートする第8の工程と、を有し、
前記エッチングは、前記下地絶縁層によってエッチングの進行方向を制御されることを特徴とする半導体装置の作製方法。 - 請求項1または請求項2において、前記第8の工程の後に、前記薄膜集積回路を個々に又は各組ごとに分断する第9の工程を有することを特徴とする半導体装置の作製方法。
- 請求項1乃至3のいずれか一において、前記薄膜集積回路の上面形状は、矩形であり、前記露呈させた剥離層の領域は、前記薄膜集積回路の一辺または対向する二辺と平行に位置していることを特徴とする半導体装置の作製方法。
- 絶縁表面を有する基板上に剥離層を形成する第1の工程と、
前記剥離層上に下地絶縁層を形成する第2の工程と、
前記剥離層上に第1の薄膜集積回路および第2の薄膜集積回路を含む層を形成する第3の工程と、
第1の薄膜集積回路および第2の薄膜集積回路を覆う保護層を形成する第4の工程と、
第1の薄膜集積回路および第2の薄膜集積回路を囲む下地絶縁層を選択的に除去して剥離層を露呈させる第5の工程と、
露呈させた部分から剥離層を部分的エッチングして、前記第1の薄膜集積回路および前記第2の薄膜集積回路の下方に空間を形成し、且つ、第1の薄膜集積回路と第2の薄膜集積回路との間に剥離層の一部を残存させる第6の工程と、
前記薄膜集積回路を、接着面を備える基体へ転置する第7の工程と、を有していることを特徴とする半導体装置の作製方法。 - 請求項1乃至5のいずれか一において、前記下地絶縁層は、フッ化ハロゲンを含む気体又は液体と化学反応しない材料であることを特徴とする半導体装置の作製方法。
- 請求項1乃至6のいずれか一において、前記保護層はフッ化ハロゲンを含む気体又は液体と化学反応しない有機樹脂であることを特徴とする半導体装置の作製方法。
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TW094132331A TWI376031B (en) | 2004-09-21 | 2005-09-19 | Method for manufacturing semiconductor device |
US11/229,497 US7354801B2 (en) | 2004-09-21 | 2005-09-20 | Method for manufacturing semiconductor device |
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JP2004273426A Expired - Fee Related JP4801337B2 (ja) | 2004-09-21 | 2004-09-21 | 半導体装置の作製方法 |
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JP4801337B2 (ja) | 2011-10-26 |
TWI376031B (en) | 2012-11-01 |
TW200623400A (en) | 2006-07-01 |
US7354801B2 (en) | 2008-04-08 |
US20060063309A1 (en) | 2006-03-23 |
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