JP2006073843A - 半導体装置およびその製造方法 - Google Patents
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Abstract
【解決手段】中央部1aの厚さと周辺部1bの厚さとを比較すると、周辺部1bの厚さの方が小さい。そのため、相対的に厚さの小さい周辺部1bのチップは、肉厚が小さいので撓みやすくなっている。したがって、たとえば温度降下により、実装基板2が収縮し、LSIチップ1と実装基板2とを接続する半田バンプ3において歪が生じても、周辺部1bは実装基板2の収縮に追随して収縮するため、周辺部1bにかかる応力は低減される。
【選択図】図1
Description
図1は、本実施形態に係る半導体装置10の構造を表わした図で、図1(a)は、半導体装置10を上方から見た平面図であり、図1(b)は、図1(a)のA−A’線における断面図である。
図3に、本実施形態に係る半導体装置20を示す。半導体装置20は、中央部21aの部分の形状が異なる以外は、第1の実施の形態で説明した半導体装置10と同じ構造を有する。
図4に、本実施形態に係る半導体装置30の構造を示す。半導体装置30は、周辺部の肉厚が薄い部分である周辺部31bの形状が異なる以外は、第1の実施の形態で説明した半導体装置10と同じ構造を有する。
第1の実施の形態と同様のプロセスで製造された、図8(b)に示すLSIチップ1の周辺部1bの厚さが中央部1aの厚さよりも小さい半導体装置においては、LSI全体を必要以上に反らせることなく、最外周半田バンプ3dにおける応力を低減することができることがわかった。
図7(a)に示す従来の半導体装置においては、LSIチップ201が実装基板202の収縮に追随しにくいため、最外周半田バンプ203dにおける応力が大きくなることがわかった。
図7(b)に示す従来の半導体装置(特許文献1記載)においては、LSIチップ51は実装基板52の収縮にある程度追随する。そのため、特に最外周半田バンプ53dにおける応力は、ある程度緩和される。しかし、その効果は比較的大きくないことがわかった。また、LSI全体の反りが、やや大きくなることがわかった。
図8(a)に示す従来の半導体装置(特許文献2記載)においては、LSIチップ101全体が実装基板102に追随しやすいため、特に最外周半田バンプ103dでの応力は低減されることがわかった。しかし、LSI全体の反りが大きくなることがわかった。
1a 中央部
1b 周辺部
2 実装基板
3 半田バンプ
4 樹脂材
5 旋盤又はレーザ
6 LSIチップ1の収縮方向
7 実装基板2の収縮方向
21 LSIチップ
21a 中央部
21b 周辺部
31 LSIチップ
31a 中央部
31b 周辺部
41 LSIチップ
41a 中央部
41b 周辺部
42 実装基板
48 溝
51 LSIチップ
52 実装基板
53 半田バンプ
54 樹脂材
56 LSIチップ51の収縮方向
57 実装基板52の収縮方向
58 溝
59 応力(収縮)の方向
101 LSIチップ
102 実装基板
103 半田バンプ
104 樹脂材
106 LSIチップ101の収縮方向
107 実装基板102の収縮方向
201 LSIチップ
202 実装基板
203 半田バンプ
206 LSIチップ201の収縮方向
207 実装基板202の収縮方向
Claims (7)
- 基板と、複数のバンプと、半導体チップとがこの順に積層された半導体装置であって、
前記複数のバンプのそれぞれの上端面と前記半導体チップ素子形成面とが接触し、
前記半導体チップの周縁における厚さは、前記半導体チップの中央部における厚さよりも小さいことを特徴とする半導体装置。 - 請求項1に記載の半導体装置において、
前記周縁近傍において、前記中央部の厚さよりも前記半導体チップの厚さが小さい領域を有することを特徴とする半導体装置。 - 請求項2に記載の半導体装置において、
前記領域の幅をc(μm)、前記複数のバンプのうち最も外に設けられたバンプの内端を通り前記基板と略直角に交わる面と前記基板の裏面とが交わる線と前記半導体チップの端部とを結ぶ線の長さをa(μm)、前記半導体チップの一辺の長さをb(μm)としたときに、a≦c≦b/4である関係を満たすことを特徴とする半導体装置。 - 請求項2または3に記載の半導体装置において、
前記領域における厚さと前記中央部における厚さとの差は、200μm以上500μm以下であることを特徴とする半導体装置。 - 請求項2乃至4いずれかに記載の半導体装置において、
前記領域における厚さが、前記半導体チップの中央部方向へ向けて漸増する領域を有することを特徴とする半導体装置。 - 請求項1乃至5いずれかに記載の半導体装置において、
前記複数のバンプを覆うように、前記基板上面と前記半導体チップ素子形成面との間に樹脂が備えられることを特徴とする半導体装置。 - 基板と半導体チップとを用意する工程と、
前記半導体チップ表面に複数のバンプを設ける工程と、
前記基板上面と前記半導体チップの前記複数のバンプが形成された面とが接するように前記基板上に前記半導体チップを設ける工程と、
前記半導体チップ裏面の外周縁を選択的に除去し、段差を形成する工程と、
を含むことを特徴とする半導体装置の製造方法。
Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
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JP2004256519A JP2006073843A (ja) | 2004-09-03 | 2004-09-03 | 半導体装置およびその製造方法 |
KR1020050081432A KR100675374B1 (ko) | 2004-09-03 | 2005-09-01 | 열적 스트레스 및 변형감소를 위한 반도체장치 탑재구조 |
US11/217,292 US7317254B2 (en) | 2004-09-03 | 2005-09-02 | Semiconductor device mounting structure for reducing thermal stress and warpage |
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JP2004256519A JP2006073843A (ja) | 2004-09-03 | 2004-09-03 | 半導体装置およびその製造方法 |
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JP2006073843A true JP2006073843A (ja) | 2006-03-16 |
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US (1) | US7317254B2 (ja) |
JP (1) | JP2006073843A (ja) |
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Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2009164206A (ja) * | 2007-12-28 | 2009-07-23 | Spansion Llc | 半導体装置及びその製造方法 |
WO2017199278A1 (ja) * | 2016-05-16 | 2017-11-23 | 株式会社日立製作所 | 半導体装置 |
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US8217514B2 (en) * | 2008-04-07 | 2012-07-10 | Stats Chippac Ltd. | Integrated circuit packaging system with warpage control system and method of manufacture thereof |
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WO2017199278A1 (ja) * | 2016-05-16 | 2017-11-23 | 株式会社日立製作所 | 半導体装置 |
Also Published As
Publication number | Publication date |
---|---|
KR100675374B1 (ko) | 2007-01-30 |
US7317254B2 (en) | 2008-01-08 |
KR20060050943A (ko) | 2006-05-19 |
US20060049520A1 (en) | 2006-03-09 |
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