JP2006060234A - 漏れ電流を減少させた誘電体層を備えるキャパシタ及びその製造方法 - Google Patents
漏れ電流を減少させた誘電体層を備えるキャパシタ及びその製造方法 Download PDFInfo
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- JP2006060234A JP2006060234A JP2005240043A JP2005240043A JP2006060234A JP 2006060234 A JP2006060234 A JP 2006060234A JP 2005240043 A JP2005240043 A JP 2005240043A JP 2005240043 A JP2005240043 A JP 2005240043A JP 2006060234 A JP2006060234 A JP 2006060234A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
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- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
- H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
- H01L27/105—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration including field-effect components
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/40—Capacitors
- H01L28/60—Electrodes
- H01L28/65—Electrodes comprising a noble metal or a noble metal oxide, e.g. platinum (Pt), ruthenium (Ru), ruthenium dioxide (RuO2), iridium (Ir), iridium dioxide (IrO2)
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/40—Capacitors
Abstract
【解決手段】 シリコン基板と、下部電極と、下部電極上に形成された誘電体層と、誘電体層上に形成された上部電極と、を備えるキャパシタにおいて、誘電体層は、遷移金属及びランタン系物質の複合酸化物を含む物質で形成される。これにより、遷移金属酸化物を含むキャパシタの漏れ電流を大きく減少させうる。
【選択図】 図3
Description
すなわち、誘電膜の厚さを薄くして、有効面積を大きくすれば、キャパシタの容量は大きくなるが、半導体素子の集積率が高くなっている中で、平面キャパシタ構造でキャパシタの面積を大きくしつつ集積化させるには限界がある。
22…下部電極、
23…誘電体層、
24…上部電極。
Claims (15)
- シリコン基板と、
下部電極と、
前記下部電極上に形成された誘電体層と、
前記誘電体層上に形成された上部電極と、を備えるキャパシタにおいて、
前記誘電体層は、遷移金属及びランタン系物質の複合酸化物を含むことを特徴とするキャパシタ。 - 前記遷移金属は、Tiであることを特徴とする請求項1に記載のキャパシタ。
- 前記ランタン系物質は、La、Ce、Pr、Nd、Pm、Eu、Gd、Tb、Dy、Ho、Er、Tm、Yb、Luのうち少なくともいずれか一つであることを特徴とする請求項1に記載のキャパシタ。
- 前記誘電体層の物質は、ランタン系物質とTiO2とを含んで形成されたことを特徴とする請求項1に記載のキャパシタ。
- 前記誘電体層は、遷移金属及びランタン系物質の複合酸化物を窒化処理したものであることを特徴とする請求項1に記載のキャパシタ。
- 半導体基板、前記半導体基板に導電性不純物がドーピングされて形成された第1不純物領域及び第2不純物領域、前記第1不純物領域と第2不純物領域との間に形成されたゲート構造体及び前記第2不純物領域と電気的に連結されたキャパシタを備える半導体メモリ装置において、
前記キャパシタは、
下部電極と、
前記下部電極上に形成された誘電体層と、
前記誘電体層上に形成された上部電極と、を備えるキャパシタであって、
前記誘電体層は、遷移金属及びランタン系物質の複合酸化物を含むことを特徴とする半導体メモリ装置。 - 前記遷移金属は、Tiであることを特徴とする請求項6に記載の半導体メモリ装置。
- 前記ランタン系物質は、La、Ce、Pr、Nd、Pm、Eu、Gd、Tb、Dy、Ho、Er、Tm、Yb、Luのうち少なくともいずれか一つであることを特徴とする請求項6に記載の半導体メモリ装置。
- 前記誘電体層は、遷移金属及びランタン系物質の複合酸化物を窒化処理したものであることを特徴とする請求項6に記載の半導体キャパシタ。
- 下部電極、前記下部電極上に形成された誘電体層及び前記誘電体層上に形成された上部電極を備えるキャパシタの製造方法において、
前記下部電極上に遷移金属及びランタン系物質を含む複合酸化物を塗布して誘電体層を製造する工程を含むことを特徴とするキャパシタの製造方法。 - 前記複合酸化物は、
(a)遷移金属物質の前駆体及びランタン系物質の前駆体を反応チャンバー内に投入する工程と、
(b)前記下部電極上に前記遷移金属前駆体及びランタン系物質の前駆体混合層を形成させる工程と、
(c)前記遷移金属前駆体及びランタン系物質の前駆体混合層を酸化させる工程と、を含んで形成することを特徴とする請求項10に記載のキャパシタの製造方法。 - 前記(c)段階は、
前記反応チャンバー内に残留した前駆体を前記反応チャンバーの外部に排出する工程と、
前記反応チャンバー内に酸素含有物質を注入して、前記遷移金属前駆体及びランタン系物質の前駆体混合層を酸化させる工程と、を含むことを特徴とする請求項11に記載のキャパシタの製造方法。 - 前記遷移金属の前駆体は、Ti(i−OPr)2(TMHD)2、Ti(i−OPr)4またはTi(DMPD)(TMHD)2のうち少なくともいずれか一つを含むことを特徴とする請求項11に記載のキャパシタの製造方法。
- 前記ランタン系物質の前駆体は、Ln(TMHD)3またはLn(i−PrCp)3の構造式を持つことを特徴とする請求項11に記載のキャパシタの製造方法。
- (d)前記酸化された前駆体混合層に対して窒化処理を行う工程をさらに含むことを特徴とする請求項11に記載のキャパシタの製造方法。
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Cited By (3)
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JP2009027017A (ja) * | 2007-07-20 | 2009-02-05 | Elpida Memory Inc | 絶縁体膜、キャパシタ素子、dram及び半導体装置 |
JP2011525699A (ja) * | 2008-05-23 | 2011-09-22 | シグマ−アルドリッチ・カンパニー、エルエルシー | 高k誘電性膜およびセリウム系前駆体を用いる製造方法 |
JPWO2021044824A1 (ja) * | 2019-09-03 | 2021-03-11 |
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KR100718155B1 (ko) * | 2006-02-27 | 2007-05-14 | 삼성전자주식회사 | 두 개의 산화층을 이용한 비휘발성 메모리 소자 |
US7662693B2 (en) * | 2007-09-26 | 2010-02-16 | Micron Technology, Inc. | Lanthanide dielectric with controlled interfaces |
JP2009283658A (ja) * | 2008-05-22 | 2009-12-03 | Elpida Memory Inc | キャパシタ素子用の絶縁膜、キャパシタ素子及び半導体装置 |
KR20200099406A (ko) | 2019-02-14 | 2020-08-24 | 삼성전자주식회사 | 단결정 재료 및 그 제조 방법, 적층체, 세라믹 전자 부품 및 장치 |
KR20210042745A (ko) | 2019-10-10 | 2021-04-20 | 삼성전자주식회사 | 유전체 단층 박막, 이를 포함하는 커패시터 및 반도체 소자, 및 이의 제조방법 |
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KR100590592B1 (ko) | 2006-06-19 |
CN100530698C (zh) | 2009-08-19 |
US7352022B2 (en) | 2008-04-01 |
KR20060017262A (ko) | 2006-02-23 |
CN1738062A (zh) | 2006-02-22 |
US20060040445A1 (en) | 2006-02-23 |
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