JP2006060030A - 半導体記憶装置 - Google Patents

半導体記憶装置 Download PDF

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Publication number
JP2006060030A
JP2006060030A JP2004240594A JP2004240594A JP2006060030A JP 2006060030 A JP2006060030 A JP 2006060030A JP 2004240594 A JP2004240594 A JP 2004240594A JP 2004240594 A JP2004240594 A JP 2004240594A JP 2006060030 A JP2006060030 A JP 2006060030A
Authority
JP
Japan
Prior art keywords
electrode
semiconductor substrate
charge
region
memory cell
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
JP2004240594A
Other languages
English (en)
Japanese (ja)
Other versions
JP2006060030A5 (enExample
Inventor
Hideaki Kurata
英明 倉田
Kazuo Otsuga
一雄 大津賀
Yoshitaka Sasako
佳孝 笹子
Takashi Kobayashi
小林　　孝
Takeshi Arikane
有金　　剛
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Renesas Technology Corp
Original Assignee
Renesas Technology Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Renesas Technology Corp filed Critical Renesas Technology Corp
Priority to JP2004240594A priority Critical patent/JP2006060030A/ja
Priority to TW094123603A priority patent/TW200617969A/zh
Priority to US11/197,485 priority patent/US7184318B2/en
Publication of JP2006060030A publication Critical patent/JP2006060030A/ja
Priority to US11/652,023 priority patent/US7471563B2/en
Publication of JP2006060030A5 publication Critical patent/JP2006060030A5/ja
Withdrawn legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
    • G11C16/0408—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors
    • G11C16/0425—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors comprising cells containing a merged floating gate and select transistor
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
    • G11C16/0408—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors
    • G11C16/0433—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors comprising cells containing a single floating gate transistor and one or more separate select transistors
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/10—Programming or data input circuits
    • G11C16/12—Programming voltage switching circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
    • G11C16/3436—Arrangements for verifying correct programming or erasure
    • G11C16/3454—Arrangements for verifying correct programming or for detecting overprogrammed cells
    • G11C16/3459—Circuits or methods to verify correct programming of nonvolatile memory cells
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
    • H10B41/35—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region with a cell select transistor, e.g. NAND
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B69/00—Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Non-Volatile Memory (AREA)
  • Semiconductor Memories (AREA)
  • Read Only Memory (AREA)
JP2004240594A 2004-08-20 2004-08-20 半導体記憶装置 Withdrawn JP2006060030A (ja)

Priority Applications (4)

Application Number Priority Date Filing Date Title
JP2004240594A JP2006060030A (ja) 2004-08-20 2004-08-20 半導体記憶装置
TW094123603A TW200617969A (en) 2004-08-20 2005-07-12 Semiconductor memory device
US11/197,485 US7184318B2 (en) 2004-08-20 2005-08-05 Semiconductor memory device
US11/652,023 US7471563B2 (en) 2004-08-20 2007-01-11 Semiconductor memory device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2004240594A JP2006060030A (ja) 2004-08-20 2004-08-20 半導体記憶装置

Publications (2)

Publication Number Publication Date
JP2006060030A true JP2006060030A (ja) 2006-03-02
JP2006060030A5 JP2006060030A5 (enExample) 2007-05-10

Family

ID=35909435

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2004240594A Withdrawn JP2006060030A (ja) 2004-08-20 2004-08-20 半導体記憶装置

Country Status (3)

Country Link
US (2) US7184318B2 (enExample)
JP (1) JP2006060030A (enExample)
TW (1) TW200617969A (enExample)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100871606B1 (ko) 2007-06-18 2008-12-02 삼성전자주식회사 비휘발성 메모리 소자의 프로그래밍 방법 및 이를 이용한낸드 플래시 메모리 소자의 구동 방법
JP2017195010A (ja) * 2016-04-20 2017-10-26 株式会社フローディア 不揮発性半導体記憶装置のデータ書き込み方法

Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101091252B (zh) * 2004-12-28 2012-09-05 斯班逊有限公司 半导体装置以及控制半导体装置操作的方法
US7345917B2 (en) * 2005-12-05 2008-03-18 Macronix International Co., Ltd. Non-volatile memory package and method of reading stored data from a non-volatile memory array
US7463525B2 (en) * 2006-12-22 2008-12-09 Spansion Llc Negative wordline bias for reduction of leakage current during flash memory operation
US8320191B2 (en) 2007-08-30 2012-11-27 Infineon Technologies Ag Memory cell arrangement, method for controlling a memory cell, memory array and electronic device
US8072072B2 (en) * 2007-09-20 2011-12-06 Qimonda Ag Integrated circuit including different types of gate stacks, corresponding intermediate integrated circuit structure and corresponding integrated circuit
US7619933B2 (en) * 2007-10-05 2009-11-17 Micron Technology, Inc. Reducing effects of program disturb in a memory device
US8355278B2 (en) 2007-10-05 2013-01-15 Micron Technology, Inc. Reducing effects of program disturb in a memory device
US20100277456A1 (en) * 2007-12-13 2010-11-04 Bridgestone Corporation Information display panel driving method and information display panel
US7672175B2 (en) * 2008-01-11 2010-03-02 Qualcomm Incorporated System and method of selectively applying negative voltage to wordlines during memory device read operation
US9461055B2 (en) * 2014-05-16 2016-10-04 Qualcomm Incorporated Advanced metal-nitride-oxide-silicon multiple-time programmable memory

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3378879B2 (ja) * 1997-12-10 2003-02-17 松下電器産業株式会社 不揮発性半導体記憶装置及びその駆動方法
US6521958B1 (en) * 1999-08-26 2003-02-18 Micron Technology, Inc. MOSFET technology for programmable address decode and correction
JP4058219B2 (ja) 1999-09-17 2008-03-05 株式会社ルネサステクノロジ 半導体集積回路
JP3829088B2 (ja) * 2001-03-29 2006-10-04 株式会社東芝 半導体記憶装置
US6754105B1 (en) * 2003-05-06 2004-06-22 Advanced Micro Devices, Inc. Trench side wall charge trapping dielectric flash memory device
US7049651B2 (en) * 2003-11-17 2006-05-23 Infineon Technologies Ag Charge-trapping memory device including high permittivity strips
JP2005223234A (ja) * 2004-02-09 2005-08-18 Renesas Technology Corp 半導体記憶装置およびその製造方法

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100871606B1 (ko) 2007-06-18 2008-12-02 삼성전자주식회사 비휘발성 메모리 소자의 프로그래밍 방법 및 이를 이용한낸드 플래시 메모리 소자의 구동 방법
JP2017195010A (ja) * 2016-04-20 2017-10-26 株式会社フローディア 不揮発性半導体記憶装置のデータ書き込み方法

Also Published As

Publication number Publication date
US7184318B2 (en) 2007-02-27
US20060039195A1 (en) 2006-02-23
US7471563B2 (en) 2008-12-30
TW200617969A (en) 2006-06-01
US20070109870A1 (en) 2007-05-17

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