TW200617969A - Semiconductor memory device - Google Patents

Semiconductor memory device

Info

Publication number
TW200617969A
TW200617969A TW094123603A TW94123603A TW200617969A TW 200617969 A TW200617969 A TW 200617969A TW 094123603 A TW094123603 A TW 094123603A TW 94123603 A TW94123603 A TW 94123603A TW 200617969 A TW200617969 A TW 200617969A
Authority
TW
Taiwan
Prior art keywords
memory
increased
memory device
reduced
leak current
Prior art date
Application number
TW094123603A
Other languages
English (en)
Chinese (zh)
Inventor
Hideaki Kurata
Kazuo Otsuga
Yoshitaka Sasago
Takashi Kobayashi
Tsuyoshi Arigane
Original Assignee
Renesas Tech Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Renesas Tech Corp filed Critical Renesas Tech Corp
Publication of TW200617969A publication Critical patent/TW200617969A/zh

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
    • G11C16/0408—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors
    • G11C16/0425—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors comprising cells containing a merged floating gate and select transistor
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
    • G11C16/0408—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors
    • G11C16/0433—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors comprising cells containing a single floating gate transistor and one or more separate select transistors
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/10—Programming or data input circuits
    • G11C16/12—Programming voltage switching circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
    • G11C16/3436—Arrangements for verifying correct programming or erasure
    • G11C16/3454—Arrangements for verifying correct programming or for detecting overprogrammed cells
    • G11C16/3459—Circuits or methods to verify correct programming of nonvolatile memory cells
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
    • H10B41/35—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region with a cell select transistor, e.g. NAND
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B69/00—Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Non-Volatile Memory (AREA)
  • Semiconductor Memories (AREA)
  • Read Only Memory (AREA)
TW094123603A 2004-08-20 2005-07-12 Semiconductor memory device TW200617969A (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2004240594A JP2006060030A (ja) 2004-08-20 2004-08-20 半導体記憶装置

Publications (1)

Publication Number Publication Date
TW200617969A true TW200617969A (en) 2006-06-01

Family

ID=35909435

Family Applications (1)

Application Number Title Priority Date Filing Date
TW094123603A TW200617969A (en) 2004-08-20 2005-07-12 Semiconductor memory device

Country Status (3)

Country Link
US (2) US7184318B2 (enExample)
JP (1) JP2006060030A (enExample)
TW (1) TW200617969A (enExample)

Families Citing this family (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101091252B (zh) * 2004-12-28 2012-09-05 斯班逊有限公司 半导体装置以及控制半导体装置操作的方法
US7345917B2 (en) * 2005-12-05 2008-03-18 Macronix International Co., Ltd. Non-volatile memory package and method of reading stored data from a non-volatile memory array
US7463525B2 (en) * 2006-12-22 2008-12-09 Spansion Llc Negative wordline bias for reduction of leakage current during flash memory operation
KR100871606B1 (ko) 2007-06-18 2008-12-02 삼성전자주식회사 비휘발성 메모리 소자의 프로그래밍 방법 및 이를 이용한낸드 플래시 메모리 소자의 구동 방법
US8320191B2 (en) 2007-08-30 2012-11-27 Infineon Technologies Ag Memory cell arrangement, method for controlling a memory cell, memory array and electronic device
US8072072B2 (en) * 2007-09-20 2011-12-06 Qimonda Ag Integrated circuit including different types of gate stacks, corresponding intermediate integrated circuit structure and corresponding integrated circuit
US7619933B2 (en) * 2007-10-05 2009-11-17 Micron Technology, Inc. Reducing effects of program disturb in a memory device
US8355278B2 (en) 2007-10-05 2013-01-15 Micron Technology, Inc. Reducing effects of program disturb in a memory device
US20100277456A1 (en) * 2007-12-13 2010-11-04 Bridgestone Corporation Information display panel driving method and information display panel
US7672175B2 (en) * 2008-01-11 2010-03-02 Qualcomm Incorporated System and method of selectively applying negative voltage to wordlines during memory device read operation
US9461055B2 (en) * 2014-05-16 2016-10-04 Qualcomm Incorporated Advanced metal-nitride-oxide-silicon multiple-time programmable memory
JP6783447B2 (ja) * 2016-04-20 2020-11-11 株式会社フローディア 不揮発性半導体記憶装置のデータ書き込み方法

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3378879B2 (ja) * 1997-12-10 2003-02-17 松下電器産業株式会社 不揮発性半導体記憶装置及びその駆動方法
US6521958B1 (en) * 1999-08-26 2003-02-18 Micron Technology, Inc. MOSFET technology for programmable address decode and correction
JP4058219B2 (ja) 1999-09-17 2008-03-05 株式会社ルネサステクノロジ 半導体集積回路
JP3829088B2 (ja) * 2001-03-29 2006-10-04 株式会社東芝 半導体記憶装置
US6754105B1 (en) * 2003-05-06 2004-06-22 Advanced Micro Devices, Inc. Trench side wall charge trapping dielectric flash memory device
US7049651B2 (en) * 2003-11-17 2006-05-23 Infineon Technologies Ag Charge-trapping memory device including high permittivity strips
JP2005223234A (ja) * 2004-02-09 2005-08-18 Renesas Technology Corp 半導体記憶装置およびその製造方法

Also Published As

Publication number Publication date
JP2006060030A (ja) 2006-03-02
US7184318B2 (en) 2007-02-27
US20060039195A1 (en) 2006-02-23
US7471563B2 (en) 2008-12-30
US20070109870A1 (en) 2007-05-17

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